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| 8-bit Microcontroller TLCS-870/C Series Application Note (TMP86CM29) Rev.1.0 22-May-2000 TOSHIBA CORPORATION TMP86CM29 Preface Thank you very much for making use of TOSHIBA semiconductor products. Toshiba has a broad range of microcomputers which are applicable to various fields ranging from consumer to industrial. The microcomputers have the development support systems and the reference application software to reduce application software development periods. Toshiba 4-bit and 8-bit single chip microcomputers include wide range lineups from small-scale system 4-bit microcomputers, TLCS-47E series and 4-bit microcomputers, TLCS-47, 470 and 470A series which have various peripheral circuits and abundant types to 8-bit microcomputers, TLCS-870, 870/X, and 90 series which have large memory and realize high-level processing to support diverse applications and satisfy various needs. This document describes the specifications of the demonstration set for Toshiba original 8-bit microcontroller TMP86Cx29. Specific examples that can be referred to for software development are also provided. TLCS-870/C series attains design optimization with TLCS-870/X series at a base, and has realized further low power consumption. In addition, it adopts the command system which has improved an object efficiency of the C language, and offers the high cost performance. Toshiba intends the microcomputers which have one-time PROM to add to the lineup, which are used for program debugging, system evaluation and pre-production at the application system development stage. It enables operating in low voltage and low power consumption. For any engineering questions of the product described in this document, please do not hesitate to contact the local Toshiba sales representative. Toshiba endeavors to write exactly and includes the latest information in this document. If any idea that may occur to your mind regarding this documentation, please do not hesitate to point out. 2000-05-22 TMP86CM29 Contents 1. Overview.................................................................................................................................................... 1 1.1 Overview of Voltmeter Mode ............................................................................................................ 1 1.2 Overview of Test Mode...................................................................................................................... 1 1.3 Overview of ROM/RAM Check Mode............................................................................................... 1 2. Setting Operating Mode ........................................................................................................................... 3 3. Display and Key Placement ..................................................................................................................... 4 3.1 Key Placement and Names .............................................................................................................. 4 3.2 Display Section ................................................................................................................................. 4 4. I/O Port ..................................................................................................................................................... 5 4.1 Pin Assignments ............................................................................................................................... 5 4.2 Pin Functions (TMP86CM29F) ........................................................................................................ 6 5. Software Specifications ............................................................................................................................ 8 5.1 Digital Voltmeter by AD Converter ................................................................................................. 8 5.1.1 Overview.................................................................................................................................... 8 5.1.2 Mode Transition Diagram ........................................................................................................ 9 5.1.3 Detailed Description of Each Mode of Voltmeter .................................................................. 10 5.1.3.1 Voltmeter Mode................................................................................................................ 10 5.1.3.2 Voltage Level Monitor Mode ........................................................................................... 11 5.1.3.3 Voltage Change Monitor Mode........................................................................................ 14 5.1.3.4 Voltage Level Compare Mode.......................................................................................... 15 5.1.3.5 Power-Saving Mode ......................................................................................................... 16 5.1.4 Infrared Transmit Format...................................................................................................... 16 5.1.4.1 Basic Format of Header and Data Sections ................................................................... 16 5.1.4.2 Common Rules of Infrared Transmit Data Format....................................................... 17 5.1.4.3 Infrared Transmit Data Format in Voltmeter Mode ..................................................... 17 5.1.4.4 Infrared Transmit Data Format in Voltage Level Monitor Mode................................. 17 5.1.4.5 Infrared Transmit Data Format in Voltage Change Monitor Mode ............................. 18 5.1.4.6 Infrared Transmit Data Format in Voltage Level Compare Mode ............................... 18 5.2 Test Mode ........................................................................................................................................ 19 5.2.1 Overview.................................................................................................................................. 19 5.2.1.1 Operation State in Test Mode ......................................................................................... 19 5.2.1.2 Description of LED Display in Test Mode...................................................................... 19 5.2.1.3 LCD Display in Test Mode .............................................................................................. 19 5.2.1.4 Key Input in Test Mode ................................................................................................... 21 5.2.2 Transition of Test Mode State ................................................................................................ 21 5.2.3 Specifications of Test Mode Test Items.................................................................................. 22 5.2.3.1 Time Base Timer Test [Test number: 0] ........................................................................ 22 5.2.3.2 Watchdog Timer Test [Test number: 1] .......................................................................... 22 5.2.3.3 Divider Output Test [Test number: 2] ............................................................................ 24 5.2.3.4 TC1 Test [Test number: 3].............................................................................................. 24 5.2.3.5 TC3 Test [Test number: 4].............................................................................................. 27 5.2.3.6 TC4 Test [Test number: 5].............................................................................................. 30 5.2.3.7 16-bit TC3 + 4 Test [Test number: 6]............................................................................. 33 5.2.3.8 TC5 Test [Test number: 7].............................................................................................. 36 5.2.3.9 TC6 Test [Test number: 8].............................................................................................. 37 5.2.3.10 16-bit TC5 + 6 Test [Test number: 9]............................................................................. 40 5.2.3.11 UART Test [Test number: 10] ......................................................................................... 42 5.2.3.12 SIO Test [Test number: 11] ............................................................................................ 45 5.2.3.13 ADC Test [Test number: 12]........................................................................................... 48 5.2.3.14 LCD Test [Test number: 13] ............................................................................................ 50 5.2.3.15 Continuous Test [Test number: 14] ............................................................................... 50 i 2000-05-22 TMP86CM29 5.3 ROM/RAM Check Mode.................................................................................................................. 52 6. Circuit Diagram ...................................................................................................................................... 53 ii 2000-05-22 TMP86CM29 1. Overview This system is used to perform demonstrations and tests for the TMP86Cx29. There are three types of operating modes as shown below: * * * Voltmeter mode Test mode ROM/RAM Check mode The operating mode of the system can be judged by LED1. When LED1 is "ON", the system is in Voltmeter mode. When LED1 is "OFF", the system is either in Test mode or ROM/RAM Check mode. For the position of LEDs , see "3.2 Display Section". 1.1 Overview of Voltmeter Mode In Voltmeter mode, a voltmeter is realized by using a 10-bit AD converter, LCD driver, etc. Voltmeter mode has the following four types of modes: * * * * Standard voltmeter mode Voltage level monitor mode Voltage change monitor mode Voltage level compare mode Note also that if no key input is made for a fixed period of time (ca. 60 seconds), Voltage mode shifts to the "power-saving mode" to temporarily suspend the functions of the microcontroller. 1.2 Overview of Test Mode In Test mode, the waveforms of timer cycle, serial communication data, etc are measured by using an external connecting pin so that the system can check whether each function of the microcontroller is operating according to the set values. Tests can be made on the following functions: * * * * * * * * * * * * * TBT WDT TC1 TC3 TC4 16bit TC3 + 4 TC5 TC6 16bit TC5+6 UART SIO AD converter Continuous test 1.3 Overview of ROM/RAM Check Mode ROM/RAM Check mode is used to display the check sum of internal ROM and address in RAM where Read/Write are not performed properly. Key operation is not available in this mode. After the check sum and abnormal RAM address are displayed, only "Reset Key" is accepted. 1 2000-05-22 TMP86CM29 VDD input Power SW Buzzer Infrared LED Measuring pins (*1) SW1/SW2 (Analog voltage input external/internal switching SW) VR1 VR2 GND LCD LED 1~4 Key0 to F(4x4) TMP86CM29F Reset Key (*1) "AIN4" printed on the board should be "AIN0". Please accept our apologies for any inconvenience this may have caused you. INT0 Interrupt Key STOP Release Key From top F1 Key F2 Key F3 Key F4 Key 2 2000-05-22 TMP86CM29 2. Setting Operating Mode The operating mode can be selected by pressing an appropriate key at power-up/reset. When Key0 is pressed at power-up/reset, it becomes Test mode. When Key1 is pressed, it becomes ROM/RAM Check mode. When one of other keys or no key is pressed, Voltmeter mode is selected. For the placement of keys, see "3.1 Key Placement and Names". 3 2000-05-22 TMP86CM29 3. 3.1 Display and Key Placement Key Placement and Names Figure 3.1.1 shows the key placement and key names. F1 Key Key 0 Key 1 Key 2 Key 3 Reset Key F2 Key Key 4 Key 5 Key 6 Key 7 INT0 Interrupt Key F3 Key Key 8 Key 9 Key A Key B STOP Release Key F4 Key Key C Key D Key E Key F Figure 3.1.1 Key Placement 3.2 Display Section Figure 3.2.1 shows an external view of the display section. 9th digit 8th digit 7th digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit LED1 LED2 LED3 LED4 Figure 3.2.1 External View of Display Section 4 2000-05-22 4. Analog Input 1 Analog Input 2 Reset INT0 Input fs fs fc fc STOP ECNT ECIN GND GND VDD Analog key 9 8 7 6 5 4 3 2 1 11 15 XIN VSS VDD TEST XOUT RESET LED Output 16 P21(XTIN) P22(XTOUT) P66 P61(ECIN) P63( INT 0 ) P62(ECNT) P20( STOP ) P60(AIN0) P65(AIN5) P64(AIN4) 14 13 12 10 4.1 Pin Assignments I/O Port LED2 Output 17 64 63 62 61 C0 C1 V1 V2 V3 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 60 59 58 57 56 55 49 53 52 51 50 49 18 19 P31(PWM3/PDO3) P30(DVO) 20 21 22 23 24 25 26 P16(TXD/SO) P17(SCK) P50 P51 P52 P53 P54 27 28 29 30 31 32 P15(RXD/SI) P14 P13 P12 P11 P10 AVDD VAREF P32(PWM4/PDO4) P67 P33(PWM6/PDO6) TC6/Infrared modulation pulse TC4 Output TC3 Output DVO Output LCD booster Input LCD booster Input LCD booster Input LCD booster Input LCD booster Input LCD COM0 Output LCD COM1 Output LCD COM2 Output LCD COM3 Output LCD Output LCD Output LCD Output A/D Reference Voltage A/D Reference Voltage COMMON Output Infrared transmit control signal LED3 Output LED4 Output Buzzer Output UART/SIO Input Figure 4.1.1 TMP86CM29F Pins for Measurement 5 SCK Output SEG7 SEG6 SEG5 P74(SEG11) P76(SEG9) P77(SEG8) P70(SEG15) P71(SEG14) P72(SEG13) P73(SEG12) P75(SEG10) P55 P56 P57 33 34 35 36 37 38 39 40 41 42 43 44 45 46 CD Output LCD Output LCD Output LCD Output LCD Output LCD Output LCD Output LCD Output LCD Output LCD Output LCD Output Key Data Input 1 Key Data Input 2 Key Data Input 3 UART/SIO Output Key Digit Output 0 Key Digit Output 1 Key Digit Output 2 Key Digit Output 3 Key Data input 0 SEG4 47 LCD Output SEG3 48 LCD Output TMP86CM29 2000-05-22 TMP86CM29 4.2 No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Pin Functions (TMP86CM29F) Pin Name VSS XIN XOUT TEST VDD P21(XTIN) P22(XTOUT) RESET Signal Name Ground High-frequency Resonator Connection High-frequency Connection Test Input Power Supply Input Low-frequency Resonator Connection Low-frequency Resonator Connection Reset Input STOP Input Analog Input 1 ECIN Output ECNT Output INT0 Input Analog Key Input (AIN4) Analog Input 2 LED LED Output Output Resonator Structure (Initial Value) SkOd(Z) SkOd(Z) SkOd(Z) TriS(Z) TriS(Z) TriS(Z) TriS(Z) TriS(Z) TriS(Z) TriS(Z) TriS(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) SkOd(Z) Reset input 8MHz 8MHz Remarks Not used (GND) VDD = 5[V] 32.768KHz P20( INT5 / STOP ) P60(AIN0) P61(AIN1/ECIN) P62(AIN2/ECNT) P63(AIN3/ INT0 ) P64(AIN4/STOP2) P65(AIN5/STOP3) P66(AIN6/STOP4) P67(AIN7/STOP5) VAREF AVDD P10(SEG31) P11(SEG30) P12(SEG29/INT1) P13(SEG28/INT2) P14(SEG27/INT3) P15(SEG26/RXD/SI) P16(SEG25/TXD/SO) P17(SEG24/ SCK ) P50(SEG23) P51(SEG22) P52(SEG21) P53(SEG20) P54(SEG19) P55(SEG18) P56(SEG17) P57(SEG16) P70(SEG15) P71(SEG14) P72(SEG13) P73(SEG12) P74(SEG11) P75(SEG10) P76(SEG9) P77(SEG8) VR/external input to be switched by SW1 VR/external input to be switched by SW2 AD Reference Voltage AD Reference Voltage COMMON Output Infrared Transmit Control Signal LED3 Output LED4 Output Buzzer Output UART/SIO Input UART/SIO Output SCK Output Key Digit Output 0 Key Digit Output 1 Key Digit Output 2 Key Digit Output 3 Key Data Input 0 Key Data Input 1 Key Data Input 2 Key Data Input 3 LCD Data Output LCD Data Output LCD Data Output LCD Data Output LCD Data Output LCD Data Output LCD Data Output LCD Data Output 6 2000-05-22 TMP86CM29 Sk0d (Z) TriS (Z) PcPp (Z) Sink Open Drain (Z) Tri-state (Z) Push Pull with P-channel Control (Z) No 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 V2 V1 C1 Pin Name Signal Name LCD Data Output LCD Data Output LCD Data Output LCD Data Output LCD data Output LCD data Output LCD data Output LCD data Output LCD COM3 Output LCD COM2 Output LCD COM1 Output LCD COM0 Output Booster Pin for LCD Drive Booster Pin for LCD Drive Booster Pin for LCD Drive Booster Pin for LCD Drive Booster Pin for LCD Drive DVO Output TC3 Output TC4 Output TC6/Infrared Modulation Pulse Structure (Initial Value) PcPp(Z) PcPp(Z) PcPp(Z) PcPp(Z) Remarks C0 P30( DVO ) P31( PWM3 / PDO3 / TC3) P32( PWM4 / PDO4 / PPG4 / TC4) P33( PWM6 / PDO6 / PPG6 TC6) 38KHz carrier output Sk0d (Z) TriS (Z) PcPp (Z) Sink Open Drain (Z) Tri-state (Z) Push Pull with P-channel Control (Z) 7 2000-05-22 TMP86CM29 5. 5.1 Software Specifications Digital Voltmeter by AD Converter Overview A digital voltmeter is realized by using Analog Input 1 and Analog Input 2 of the 10-bit AD converter. Analog Input 1 and Analog Input 2 are connected to the AIN0 and AIN5 pins of the microcontroller, respectively. With the AD input switching switches (SW1/SW2), "input from voltage value divided by VR1/VR2" and "external input" can be switched. The maximum input voltage to the AD converter is VDD. This voltmeter has the four main modes: * * * * Standard voltmeter mode Voltage level monitor mode Voltage change monitor mode Voltage level compare mode 5.1.1 Analog Input 1 and Analog Input 2 can be selected in the standard mode and the voltage change monitor mode, respectively. In the AD converter, the reference voltage is 0 to 5V, and the input voltage is sampled as shown in the following equation: AD conversion value[bit] = 10[bit] Input voltage [V]/5[V] Each analog input gets a sampling value per 0.1[ms] and a mean value is calculated after a certain times. Then processing is executed. Values measured in each mode can be displayed on LCD. They can also be transmitted with "F4Key" input by using infrared LED. While data is transmitted, Key input is suspended. The infrared transmit data format will be shown in the description of each mode. In this voltmeter, if no key operation is made for more than 1 minute, the power-saving mode is entered to suspend AD conversion, key operation, and LCD display. Only by pressing "STOP Release Key" can the power-saving mode be released to return to normal processing. * * Some infrared transmit data may cause other home appliance to malfunction. Please check before using this voltmeter. This voltmeter uses VDD input voltage (5V) as a reference voltage of AD conversion (VAREF). Note therefore that there may be a difference between an actual voltage and displayed voltage due to VDD input voltage. 8 2000-05-22 TMP86CM29 5.1.2 Mode Transition Diagram Figure 5.1.1 shows the transition of voltmeter modes. F1 Key Standard voltmeter mode F1 Key No key input for one minute STOP mode STOP Release Key Voltage level monitor mode F1 Key Votlage change monitor mode F1 Key Voltage level compare mode Infrared transmit mode F4 Key Figure 5.1.1 Mode Transition Diagram 9 2000-05-22 TMP86CM29 5.1.3 Detailed Description of Each Mode of Voltmeter Voltmeter Mode In this mode, a voltage from the specified analog input is measured and displayed on LCD. LED/LCD display Only LED1 is "ON" and LED 2 to LED 4 are "OFF". The 8th digit on LCD displays the analog input number currently selected. The 6th digit displays the first digit of a voltage measurement value, which is followed by up to the third decimal place. In the initial state, Analog Input 1 is selected for analog input. Figure 5.1.2 shows an example of LED/LCD display with Analog Input 1 and a voltage measurement value of 3.267[V]. 5.1.3.1 LED1 LED2 LED3 LED4 9th digit 8th digit 7th digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit Figure 5.1.2 Key operation Example of Display in Voltmeter Mode "F1 Key" input ends the voltmeter mode and the mode changes to the voltage level monitor mode. "F2 Key" input can be used to switch between Analog Input 1 and Analog Input 2. Switching updates the 8th digit on LCD and it displays the number of analog input currently used. "F4 Key" input can be used to transmit the analog input number currently selected and a 10-bit AD measurement value by using infrared LED. For the transmit format, see "5.1.4 Infrared Transmit Format". Figure 5.1.3 shows an example of display when "F2 Key" input is made. 10 2000-05-22 TMP86CM29 Analog Input 1 input F2 Key input Analog Input 2 input F2 Key input Analog Input 1 input Figure 5.1.3 5.1.3.2 Example of Switching Input in Voltmeter Mode Voltage Level Monitor Mode In this mode, measurement values from analog input are monitored. When the value gets lower than the voltage monitor level, a buzzer sounds and LED 2 blinks as a warning. LED/LCD display LED2 is "ON" and LED 3 and LED 4 are "OFF". The 9th digit on LCD displays the first digit of the voltage monitor level, which is followed by up to the second decimal place. The 4th digit displays the first digit of a voltage measurement value, which is followed by up to the second decimal place. In the voltage level monitor mode, the analog input number is fixed to Analog Input 1. Upon power-up and reset, the voltage monitor level is cleared to 0.00[V]. Figure 5.1.4 shows an example of LED/LCD display when the voltage monitor level is 2.13[V] and the voltage measurement value is 3.47[V]. LED1 LED2 LED3 LED4 9th digit 8th digit 7th digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit Figure 5.1.4 Example of Display in Voltage Level Monitor Mode 11 2000-05-22 TMP86CM29 Key operation "F1 Key" input ends the voltage monitor mode and the mode changes to the voltage change monitor mode. At this time, the voltage monitor level that has been set is maintained. "F3 Key" input is used to enter the monitor level setting state. When this state is entered, monitoring of voltage level is stopped and the 9th digit on LCD starts blinking. The 4th to 1st digits that normally display a voltage measurement value are all lit during the monitor level setting state. When one of the keys from "Key0" to "Key9" is pressed while LCD is blinking ( "Key0 - Key5" while the 9th digit is blinking), the number of pressed key is input to the blinking digit and is temporarily set and displayed as the monitor level. The voltage monitor level can be set to 0.00 to 5.00. Once in the monitor level setting state, by further pressing "F3Key", the position of blinking digit moves from the 9th to the lower digits so that the 7th and 6th digits can be set. Note that when "5" is input to the 9th digit, "0" is automatically set to both the 7th and 6th digits. When "F3 Key" is input while the 6th digit is blinking or "F3 Key" is input after "5" is input to while the 9th digit is blinking, LCD stops blinking and the values set to the 9th to 6th digits are fixed as the monitor level. The state then goes back to the voltage level monitor state. The voltage monitor level is not fixed until "F3 Key" is input on the 6th digit or "F3 Key" is input after "5" is set to the 9th digit. Therefore, if "F1Key" is pressed to enter the voltage change monitor mode while the monitor level setting is performed, the monitor level before change is saved. "F4 Key" input can be used to transmit a current voltage monitor level and a 10-bit A/D measurement value from Analog Input 1 by using infrared LED. For the transmit format, see "5.1.4 Infrared Transmit Format". Figure 5.1.5 shows an example for setting the monitor level by "F3 Key" input. 12 2000-05-22 TMP86CM29 "F3 Key" input 9th digit blinking "Key4" input 4 is displayed on 9th digit "F3 Key" input 7th digit blinking "Key7" input 7 is displayed on 7th digit "F3 Key" input 6th digit blinking "Key8" input 8 is displayed on 6th digit "F3 Key" input Monitor level is set Figure 5.1.5 Example of Setting Monitor Level 13 2000-05-22 TMP86CM29 5.1.3.3 Voltage Change Monitor Mode In this mode, changes in the voltage measurement value from analog input are measured. If there is a change of more than fixed amount, a warming is issued. In the voltage change monitor mode, the voltage AD value of the last sampling is always held. This value is compared with the new sampling value and if a difference is 0.04[V] or more, a buzzer sounds and LED3 blinks as a warning. LED/LCD display LED1 and LED3 are "ON" and LED2 and LED 4 are "OFF". The 6th digit on LCD displays the analog input number currently selected. The 4th digit displays the first digit of a voltage measurement value from analog input, which is followed by up to the second decimal place. Figure 5.1.6 shows an example of LED/LCD display with Analog Input 1 and a voltage measurement value of 2.96[V]. LED1 LED2 LED3 LED4 9th digit 8th digit 7th digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit Figure 5.1.6 Example of Display in Voltage Change Monitor Mode Key operation "F1 Key" input ends the voltage change monitor mode and the mode changes to the voltage level compare mode. "F2 Key" input can be used to switch between Analog Input 1 and Analog Input 2. Switching updates the 8the digit on LCD and it displays the number of analog input currently used. "F4 Key" input can be used to transmit the analog input number currently selected and a 10-bit AD measurement value by using infrared LED. For the transmit format, see "5.1.4 Infrared Transmit Format". Figure 5.1.7 shows an example of "F2 Key" input. 14 2000-05-22 TMP86CM29 Analog Input 1 "F2 Key" input Analog Input 2 "F2 Key" input Analog Input 1 Figure 5.1.7 5.1.3.4 Example of Switching Input in Voltage Change Monitor Mode Voltage Level Compare Mode In this mode, a voltage from Analog Input 1 and Analog Input 2 are measured. When measurement values of both inputs are the same, a buzzer sounds and LED4 blinks. LED/LCD display In the voltage level compare mode, LED1 and LED4 are "ON" and LED 2 and LED3 are "OFF". The 9th digit on LCD displays the first digit of a measurement value of Analog Input 1, which is followed by up to the second decimal place. Figure 5.1.8 shows an example of LEC/LCD display when Analog Input 1 is 3.64[V] and Analog Input 2 is 1.85[V]. LED1 LED2 LED3 LED4 9th digit 8th digit 7h digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit Figure 5.1.8 Example of Display in Voltage Level Compare Mode Key operation "F4 Key" input can be used to transmit 10-bit AD measurement values of Analog Input 1 and Analog Input 2 by using infrared LED. For the transmit format, see "5.1.4 Infrared Transmit Format". "F1 Key" input ends the voltage level compare mode and the mode changes to the voltmeter mode. 15 2000-05-22 TMP86CM29 5.1.3.5 Power-Saving Mode This voltmeter enters the power-saving mode when no key operation is made for about one minute. The power-saving mode suspends AD conversion, key input, and LCD/LED display. In this mode, only "STOP Release Key" input is accepted. By pressing "STOP Release Key", the voltmeter is restored to the previous Voltmeter mode and processing is continued. 5.1.4 Infrared Transmit Format Basic Format of Header and Data Sections Figure 5.1.9 shows the basic format of transmit header and transmit data. Transmit direction 5.1.4.1 9ms Header Section 4.5ms Transmit direction 0.4ms 0.4ms Data Section "0" Transmit direction 0.4ms 1.2ms Data Section "1" Figure 5.1.9 Infrared Transmit Data Format In transmitting, the transmit header is firstly transmitted. Then, 6-byte data (3byte data + 3-byte inverted data) is transmitted according to the infrared transmit data format of each Voltmeter mode. 16 2000-05-22 TMP86CM29 5.1.4.2 Common Rules of Infrared Transmit Data Format * * * * Measurement data is transmitted from the upper bit. Every1-byte data transmitted is followed by its inverted value. This method enables the receiving end to check if there is any data error. "1" is transmitted as a reserved bit. 10-bit AD measurement values are transmitted in the original format before being converted to volt units. 5.1.4.3 Infrared Transmit Data Format in Voltmeter Mode Figure 5.1.10 shows the infrared transmit data format in the voltmeter mode. Transmit direction A 5bit Reserved 3bit Analog input number A 8bit 6bit Reserved B 2bit Analog input measurement value B 8bit C 8bit Analog input measurement value C 8bit Figure 5.1.10 Infrared Transmit Format in Voltmeter Mode For the analog input number, "001" is transmitted for Analog Input 1 and "010" is transmitted for Analog Input 2. 5.1.4.4 Infrared Transmit Data Format in Voltage Level Monitor Mode Figure 5.1.11 shows the infrared transmit data format in the voltage level monitor mode. Transmit direction A 8bit Voltage monitor level A 8bit B 2bit 4bit Voltage monitor level Reserved 2bit Analog input measurement value B 8bit C 8bit Analog input measurement value C 8bit Figure 5.1.11 Infrared Transmit Format in Voltage Level Monitor Mode 17 2000-05-22 TMP86CM29 For the voltage monitor level, the voltage value that is input at monitor level setting is transmitted after being converted to a 10-bit value. Conversion is performed by dividing the voltage value by 1024 with a reference voltage of 0 to 5V. The voltage monitor level and measurement data are both transmitted from the upper bit. 5.1.4.5 Infrared Transmit Data Format in Voltage Change Monitor Mode Figure 5.1.12 shows the infrared transmit data format in the voltage change monitor mode. Transmit direction A 8bit Voltage monitor level A 8bit B 2bit 4bit Voltage monitor level Reserved 2bit Analog input measurement value B 8bit C 8bit Analog input measurement value C 8bit Figure 5.1.12 Infrared Transmit Format in Voltage Change Monitor Mode For the analog input number, "001" is transmitted for Analog Input 1 and "010" is transmitted for Analog Input 2. 5.1.4.6 Infrared Transmit Data Format in Voltage Level Compare Mode Figure 5.1.13 shows the infrared transmit data format in the voltage change compare mode. Transmit direction A 8bit Analog Input 1 measurement value A 8bit 2bit Analog Input 1 measurement value B 4bit Reserved 2bit Analog Input 2 measurement value B 8bit C 8bit Analog Input 2 measurement value C 8bit Figure 5.1.13 Infrared Transmit Data Format in Voltage Level Compare Mode 18 2000-05-22 TMP86CM29 5.2 Test Mode Overview Operation State in Test Mode In Test mode, the three types of state are available: "test item setting state", "test in progress state", and "test completed state". The current state of Test mode is displayed by LED. 5.2.1.2 Description of LED Display in Test Mode LED display indicates the Test mode state in the following manner: * * * * LED1 off = Test mode LED2 on = Test item setting state LED3 on = Test in progress state LED4 on = Test completed state 5.2.1 5.2.1.1 Note that the 2nd to 4th digits are all "ON" when the interrupt cycle is shorter than the interrupt processing time and interrupts are continuously generated in the timer counter test, etc. This enables interrupt cycle errors to be detected. 5.2.1.3 LCD Display in Test Mode Figure 5.2.1 shows the initial display in Test mode. LED1 LED2 LED3 LED4 9th digit 8th digit 7th digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit Figure 5.2.1 External View of Test Mode The 6th and 7th digits on LCD display the test number currently selected. The 4th digit displays the mode number which shows the operating mode of the selected test. Table 5.2.1 on the next page shows the test numbers and the test details for each mode number. Displayed on the 1st and 2nd digits is the setting number for test execution, which enables the register values to be selected and set from predetermined settings when the test specified by the test and mode numbers is executed. 19 2000-05-22 TMP86CM29 Table 5.2.1 Description of Tests Test No 0 1 2 Mode No 0 0 1 0 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 0 1 2 3 0 TBT test WDT test DVO test Description of Test Time Base Timer Interrupt request Reset output DVO 18bit timer TC1 test 18bit event counter Pulse width measurement Frequency measurement 8bit timer TC3 test 8bit event counter 8bit PDO 8bit PWM 8bit timer TC4 test 8bit event counter 8bit PDO 8bit PWM 16bit timer TC3 + 4 test 16bit event counter 16bit PWM 16bit PPG TC5 test 8bit timer 8bit timer TC6 test 8bit event counter 8bit PDO 8bit PWM 16bit timer TC5 + 6 test 16bit PWM 16bit PPG UART test Tx Rx SIO Tx SIO test SIO Rx SIO TxRx ADC test LCD test Continuous test Single mode Repeat mode LCD operation check test Output Pin COMMON COMMON RESET DVO COMMON COMMON COMMON, LCD display COMMON, LCD display COMMON COMMON COMMON, TC3 COMMON, TC3 COMMON COMMON COMMON, TC4 COMMON, TC4 COMMON COMMON COMMON,TC4 COMMON,TC4 COMMON COMMON COMMON COMMON, TC6 COMMON,TC6 COMMON COMMON, TC6 COMMON,TC6 TxD, LCD display LCD display SO, SCK, LCD display SCK, LCD display SO, SCK, LCD display COMMON, LCD display COMMON, LCD display LCD display COMMON, DVO, TC3, TC4, TC6, TxD, SO, SCK, LCD display Input Pin ECIN ECIN ECIN, ECNT TC3 TC4 TC3 TC6 RxD SCK SI, SCK SI, SCK AIN0 AIN0 ECIN, ECNT, TC3, TC4, TC6, RxD, SCK, SI, AIN0 3 4 5 6 7 8 9 1 2 0 1 0 1 2 0 1 0 10 11 12 13 14 0 Continuous test 20 2000-05-22 TMP86CM29 5.2.1.4 Key Input in Test Mode In Test mode, "F1 Key" input is used to select the test number. Each time "F1 Key" is pressed, the test number on the 6th and 7th digits is incremented. The display number reaches 14, then it returns to 0. "F2 Key" input is used to select the mode number. The mode number is selected on the 4th digit in the same manner as the test number and each test number has its own range of numbers to choose from. The setting number can be assigned for 16 settings (0 to 15) according to the combination of test number and mode number. The setting number can be set by using "Key 0 to Key F" and the specified number (0 to 15) is displayed on the 1st and 2nd digits on LCD. "F3 Key" input sets each register value according to the selected test details and executes an operation test. When it is necessary to display register values to check operation results as in the case of pulse width measurement, frequency measurement, and serial transmit/receive, the test completed state is entered after each measurement or serial transmit/receive is completed. At this time, data is displayed on LCD so that operation can be checked. For tests that include the test completed state, data displayed on LCD can be switched with "F4 Key" input after test completion. While tests are executed, only "INT0 Interrupt Key" is accepted. When "INT0 Interrupt Key" is pressed during test execution, the test is immediately stopped and the test item setting state is entered. When "INT0 Interrupt Key" is pressed for more than 3 seconds, `Int0 Err' is displayed on LCD and the test is stopped. In this case, press "Reset Key" and execute the test again. 5.2.2 Transition of Test Mode State Test Item Setting State F3 Key input Test in Progress State INT0 Interrupt Key input Test Complited State INT0 Interrupt Key input. Figure 5.2.2 Transition of Test Mode State 21 2000-05-22 TMP86CM29 5.2.3 Specifications of Test Mode Test Items Time Base Timer Test [Test number: 0] In the Time Base Timer (TBT) test, TBT interrupts are generated and COMMON pin outputs are inverted in interrupt processing. By monitoring the COMMON pin, the interrupt cycle can be measured to check whether the TBT is operating according to the setting. The test number of TBT test is 0. No mode selection is performed. In the TBT test, each setting pattern specifies the operating mode (SYSCR2, NORMAL/SLOW), high-/low-frequency selection (DV7CK), and TBT interrupt frequency (TBTCR). Table 5.2.2 shows the register set values for each setting pattern. Table 5.2.2 Register Set Values for TBT Test Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW (0xE0) NORMAL (0xC0) Operating Mode (SYSCR2) Selected Output Frequency (TBTCR) (0x08) (0x09) (0x0A) (0x0B) (0x0C) (0x0D) (0x0E) (0x0F) (0x1A) (0x1B) (0x1C) (0x1D) (0x1E) (0x1F) (0x08) (0x09) TBT Interrupt Cycle 1.047s 262ms 8.19ms 2.04ms 1.023ms 512s 256s 64ms 7.81ms 1.95ms 977s 488s 244s 64s 1s 250ms 5.2.3.1 5.2.3.2 Watchdog Timer Test [Test number: 1] The watchdog timer (WDT) test has the following two modes: * WDT Output Interrupt Request Mode WDT interrupts are generated and the COMMON pin is inverted in WDT interrupt processing. By monitoring the COMMON pin, the WDT interrupt cycle is measured to check whether the WDT is operating according to the setting. WDT Output Reset Output Mode After the WDT test is started, not clearing the WDT counter activates the WDT and resets internal hardware. By measuring the time between test start and reset operation, whether operation is performed according to the setting can be checked. * The test number of WDT test is 1. Table 5.2.3 shows the mode numbers and setting items of WDT test. 22 2000-05-22 TMP86CM29 Table 5.2.3 Modes and Setting Items of WDT Test Mode Name Interrupt request Reset output Mode No 0 1 Setting Item Operating mode, High-/Low-frequency selection, Watchdog timer detecting time Operating mode, High-/Low-frequency selection, Watchdog timer detecting time Table 5.2.4 and Table 5.2.5 show the register set values for each setting pattern. Table 5.2.4 Register Set Values for WDT Reset Output Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 For continuous test NORMAL (0xC0) fc (0x00) (0x0A) 1.049s SLOW(0xE0) fc (0x00) NORMAL(0xC0) fc (0x00) Operating Mode (SYSCR2) High-/Low-Frequency Selection (TBTCR) (WDTCR1) (0x08) (0x0A) (0x0C) (0x0E) (0x08) fs (0x10) (0x0A) (0x0C) (0x0E) (0x08) (0x0A) (0x0C) (0x0E) WDT Reset Cycle 4.194s 1.049s 262ms 65.5ms 4s 1s 250ms 62.5ms 4s 1s 250ms 62.5ms Table 5.2.5 Register Set Values for WDT Interrupt Request Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 For continuous test NORMAL (0xC0) fc (0x00) (0x0A) 1.049s SLOW(0xE0) fc (0x00) NORMAL(0xC0) fc (0x00) Operating Mode (SYSCR2) High-/Low-Frequency Selection (TBTCR) (WDTCR1) (0x08) (0x0A) (0x0C) (0x0E) (0x08) fs (0x10) (0x0A) (0x0C) (0x0E) (0x08) (0x0A) (0x0C) (0x0E) WDT Reset Cycle 4.194s 1.049s 262ms 65.5ms 4s 1s 250ms 62.5ms 4s 1s 250ms 62.5ms 23 2000-05-22 TMP86CM29 5.2.3.3 Divider Output Test [Test number: 2] In the divider output test, duty-50% pulses are output from the DVO pin. By monitoring the DVO pin, whether the divider output is operating according to the setting can be checked. The test number of divider output test is 2. No mode selection is performed. In this test, each setting pattern specifies the operating mode (SYSCR2, NORMAL/SLOW), high-/low-frequency selection (DV7CK), and DVO output frequency. Table 5.2.6 shows the register set values for the divider output test. Table 5.2.6 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 For continuous test NORMAL (0xC0) 976.5Hz (0x80) 1.024ms SLOW(0xE0) NORMAL(0xC0) Register Set Values for Divider Output Test Output Frequency Selection (TBTCR) 976.5Hz (0x80) 1.953KHz (0xA0) 3.9065KHz (0xC0) 7.8125KHz (0xE0) 1.024KHz (0x90) 2.048KHz (0xB0) 4.096KHz (0xD0) 8.192KHz (0xF0) 1.024KHz (0x80) 2.048KHz (0xA0) 4.096KHz (0xC0) 8.192KHz (0xE0) Divider Output Frequency/Cycle 1.024ms 512s 256s 128s 977s 488s 244s 122s 977s 488s 244s 122s Operating Mode (SYSCR2) 5.2.3.4 TC1 Test [Test number: 3] The timer counter 1 (TC1) test has the following four modes: * 18-bit Timer Mode By activating the 18-bit timer, TC1 interrupts are generated and COMMON pin outputs are inverted in TC1 interrupt processing. By monitoring the COMMON pin, the TC1 interrupt cycle can be measured to check whether the TC1 18-bit timer counter is operating according to the setting. Event Counter Mode By using the counter by input pulses from the ECIN pin, TC1 interrupts are generated and COMMON pin outputs are inverted in TC1 interrupt processing. By monitoring the COMMON pin, the TC1 interrupt cycle can be measured to check whether the TC1 event counter is operating according to the setting. * 24 2000-05-22 TMP86CM29 * Pulse Width Measurement Mode By input pulse width measurements from the ECIN pin, TC1 interrupts are generated and COMMON pin outputs are inverted in TC1 interrupt processing. By displaying on LCD the pulse width measurement value of pulses input from the ECIN pin, whether TC1 pulse width measurement is operating according to the setting can be checked. Frequency Measurement Mode By input pulse frequency measurements from the ECIN pin, TC1 interrupts are generated and COMMON pin outputs are inverted in TC1 interrupt processing. By displaying on LCD the frequency measurement value of pulses input from the ECIN pin, whether TC1 frequency measurement is operating according to the setting can be checked. * The test number of TC1 test is 3. Table 5.2.7 shows the mode numbers and setting items of TC1 test. Table 5.2.7 Modes and Setting Items of TC1 Test Mode Name TC1 18bit Timer TC1 Event Counter TC1 Pulse Width Measurement TC1 Frequency Measurement Mode No 0 1 2 Operating mode, TREG1A Operating mode, High-/Low-frequency selection, Window gate pulse interrupt edge High-/Low-frequency selection, ECIN edge selection, Window gate pulse selection, Window gate pulse interrupt edge, Internal window gate pulse set register, TC6 operation clock, TC6 operating mode, TTREG6, PWREG6 Setting Item Operating mode, High-/Low-frequency selection, TREG1A TC1 source clock 3 In the TC1 pulse width measurement and TC1 frequency measurement modes, the test completed state is entered after measurement is performed three times. LCD displays the TREG1A value, which is the measurement result. The display number (1 to 3) indicates the number of measurements and selected by "F4 Key" input. If an overflow error occurs during a test, the 6th digit displays "E". In this case, change the set value and perform measurement again. By pressing "INT0 Interrupt Key" in the test completed state, the state returns to the test item setting state. LED1 LED2 LED3 LED4 9th digit 8th digit 7th digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit Display number TREG1A Figure 5.2.3 TC1 Test Result Display 25 2000-05-22 TMP86CM29 Table 5.2.8 to Table 5.2.11 show the register set values for each setting pattern. Table 5.2.8 Register Set Values for TC1 18-bit Timer Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Operating Mode (SYSCR2) High-/Low-Frequency Selection (TBTCR) Frequency Selection (TC1CR1) (TREG1A) (0x0001F4) (0x00C350) (0x0186A0) (0x00000A) (0x000019) (0x000028) (0x00000A) (0x000002) (0x000020) (0x000029) (0x000033) (0x000002) (0x000052) (0x000033) (0x000002) (0x027100) TC1 Interrupt Cycle 500s 50ms 100ms 10s(*) 400s 10.24ms 10.24ms 2.096s 976s 10ms 49.776ms 2s 20ms 49.776ms 2s 20ms fc/2 (0x58) 3 fc (0x00) NORMAL(0xC0) fs (0x10) SLOW(0xE0) fc (0x00) fc/27(0x54) fc/211(0x50) fc/213(0x4C) fc/223(0x48) fs(0x44) fs/23(0x50) fs/25(0x4C) fs/215(0x48) fs/23(0x50) fs/25(0x4C) fs/215(0x48) fc(0x40) * In this setting, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not generated according to the setting. Table 5.2.9 Register Set Values for TC1 18-bit Event Counter Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Operating Mode (SYSCR2) (TC1CR1) (TREG1A) (0x03FFFF) (0x010000) (0x00FFFF) (0x00F000) (0x000F00) (0x0000FF) (0x00000F) (0x000001) (0x03FFFF) (0x010000) (0x00FFFF) (0x00F000) (0x000F00) (0x0000FF) (0x00000F) (0x000001) NORMAL(0xC0) (0x5C) SLOW(0xE0) 26 2000-05-22 TMP86CM29 Table 5.2.10 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fc (0x00) fs (0x00) NORMAL(0xC0) fc (0x00) Operating Mode (SYSCR2) Register Settings for TC1 Pulse Width Measurement High-/Low-Frequency Selection (TBTCR) Frequency Selection (TC1CR1) fc(0x42) fs(0x46) fc/223(0x4A) fc/213(0x4E) fc/211(0x52) fc/27(0x56) fc/23(0x5A) fs/215(0x4A) fs/25(0x4E) fs/23(0x52) fs/215(0x4A) fs/2 (0x4E) fs/23(0x52) 5 Interrupt Edge (TC1CR2) rising edge (0x00) both edges (0x10) Internal Clock 8MHz 32.768KHz 0.953Hz 976.56Hz falling edge (0x00) 3.906KHz 62.5KHz 4.096KHz both edges (0x10) falling edge (0x00) both edges (0x10) falling edge (0x00) 1Hz 1.024KHz 4.096KHz 1Hz 1.024KHz 4.096KHz Table 5.2.11 Register Settings for TC1 Frequency Measurement Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) NORMAL(0xC0) (0x5F) Operating Mode (SYSCR2) (TC1CR2) (TC1CR1) (0x00) (0x90) (0x10) (0x80) (0x20) (0xB0) (0x34) (0xA8) (0x22) (0xD2) (0x52) (0xC2) (0x00) (0x90) (0x34) (0xC2) SEG falling both falling both falling both falling both falling both falling both falling both falling both SEGDG falling both both falling falling both both falling falling both both falling falling both both falling WGP (TREG1B) (TC6CR) (TTREG6) (PWREG6) ECNT (0x00) (0x00) (0xFF) (0x00) (0x00) 212/fc 2 /fc 213/fc 214/fc 12 (0x09) TC6 (0x00) (0xB9) (0x19) (0x2A) ECNT 25/fs TC6 (0x00) (0xFF) (0xFF) (0x00) (0x00) (0x00) (0x00) (0x09) (0xFF) (0xFF) (0xFF) (0x00) (0x00) (0xFF) (0x00) (0x00) (0x00) (0xFF) (0x00) (0x00) 5.2.3.5 TC3 Test [Test number: 4] The TC3 test has the following four modes: * 8-bit Timer Mode The 8-bit timer is activated and COMMON pin outputs are inverted in TC3 interrupt processing. By monitoring the COMMON pin, the TC3 interrupt cycle can be measured to check whether the TC3 8-bit timer mode is operating according to the setting. * 8-bit Event Counter Mode By using the counter by input pulses from the ECIN pin, TC3 interrupts are generated and COMMON pin outputs are inverted in TC3 interrupt processing. By monitoring the COMMON pin, the TC3 interrupt cycle can be measured to check whether the TC3 event counter mode is operating according to the setting. 27 2000-05-22 TMP86CM29 * 8-bit PDO Mode 8-bit PDO is output to the TC3 pin and COMMON pin outputs are inverted in TC3 interrupt processing. By monitoring signals output from the COMMON and TC3 pins, whether the TC3 interrupt cycle and PDO output are operating according to the setting can be checked. * 8-bit PWM Mode 8-bit PWM is output to the TC3 pin and COMMON pin outputs are inverted in TC3 interrupt processing. By monitoring signals output from the COMMON and C3 pins, whether the TC3 interrupt cycle and PWM output are operating according to the setting can be checked. The test number of TC3 test is 4. Table 5.2.12 shows the mode numbers and setting items of TC3 test. Table 5.2.12 Mode Name 8bit Timer 8bit Event Counter 8bit PDO 8bit PWM Mode No 0 1 2 3 TTREG3 Operating mode, High-/Low-frequency selection, TTREG3, TC3 source clock, TTF Operating mode, High-/Low-frequency selection, TTREG3, TC3 source clock, TTF Modes and Setting Items of TC3 Test Setting Item Operating mode, High-/Low-frequency selection, TTREG3, TC3 source clock Table 5.2.13 to Table 5.2.16 show the register set values for each setting pattern. Table 5.2.13 Setting Item 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fs (0x10) fc (0x00) fs/23(0x08) fs/23(0x08) NORMAL(0xC0) fc/23(0x38) fc (0x00) Operating Mode (SYSCR2) Register Setting for TC3 8-bit Timer Frequency Selection (TC3CR) fc/211(0x08) fc/2 (0x18) fc/25(0x28) 7 High-/Low-Frequency Selection (TBTCR) (TTREG3) (0x04) (0xC8) (0x19) (0x3F) (0x0E) (0x32) (0x01) (0x05) (0x32) (0x64) (0xC8) (0xFF) (0x01) (0x29) (0x01) (0x29) TC3 Interrupt Cycle 1.024ms 51.2ms 400s 1.0008ms 60s 200s 1s(*) 5s(*) 50s 100s 200s 255s 244s 10.004ms 244s(*) 10.004ms * In these settings, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not generated according to the setting. 28 2000-05-22 TMP86CM29 Table 5.2.14 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Register Settings for TC3 8-bit Event Counter (TC3CR) (TTREG3) (0xFF) (0x7F) (0x3F) (0x1F) (0x0F) (0x08) (0x02) (0x01) (0xFF) (0x7F) (0x3F) (0x1F) (0x0F) (0x08) (0x02) (0x01) Operating Mode (SYSCR2) NORMAL(0xC0) (0x78) SLOW(0xE0) Table 5.2.15 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) NORMAL(0xC0) Operating Mode (SYSCR2) Register Settings for TC3 8-bit PDO Mode Frequency Selection (TC3CR) (TTREG3) Frequency High-/Low-Frequency Selection (TBTCR) TFF CLR SET (0x04) (0x28) (0x64) (0xC8) (0x3F) (0xFA) CLR (0x05) (0x32) (0x02) (0xC8) (0x29) (0xCD) Inversion interval 1.024ms 10.24ms 25.6ms 51.2ms 1ms 4ms 20s(*) 200s 2s(*) 200s 10ms 50ms 10ms 50ms (0x09) (0x89) fc/2 (0x09) fc (0x00) 11 (0x19) (0x29) (0x39) fc/27 fc/25 fc/23 fs (0x10) (0x09) (0x09) fs/23 SET CLR fc (0x00) (0x89) (0x09) (0x29) (0xCD) * In these settings, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not generated according to the setting. 29 2000-05-22 TMP86CM29 Table 5.2.16 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fc (0x00) fs (0x10) NORMAL(0xC0) fc (0x00) Operating Mode (SYSCR2) Register Settings for TC3 8-bit PWM (TC3CR) (PWREG3) fc (0x0A) (0x8A) (0x2A) (0xAA) (0x5A) (0xDA) (0x4A) (0xCA) (0x6A) (0xEA) (0x0A) (0x8A) (0x0A) (0x8A) (0x4A) (0xCA) fc/211 fc/25 fc/2 fs fc fs/23 fs/2 fs 3 High-/Low-Frequency Selection (TBTCR) TTF CLR SET CLR SET CLR SET CLR SET CLR SET CLR SET CLR SET CLR SET (0x40) Inversion Interval 16.38ms 256s 16s(*) 1.95ms 8s(*) 15.616ms 1.95ms * In these settings, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not generated according to the settng. 5.2.3.6 TC4 Test [Test number: 5] The TC4 test has the following four modes: * 8-bit Timer Mode The 8-bit timer is activated and COMMON pin outputs are inverted in TC4 interrupt processing. By monitoring the COMMON pin, the TC4 interrupt cycle can be measured to check whether the TC4 8-bit timer mode is operating according to the setting. * 8-bit Event Counter Mode By using the counter by input pulses from the ECIN pin, TC4 interrupts are generated and COMMON pin outputs are inverted in TC4 interrupt processing. By monitoring the COMMON pin, the TC4 interrupt cycle can be measured to check whether the TC4 event counter mode is operating according to the setting. * 8-bit PDO Mode 8-bit PDO is output to the TC4 pin and COMMON pin outputs are inverted in TC4 interrupt processing. By monitoring signals output from the COMMON and TC4 pins, whether the TC4 interrupt cycle and PDO output are operating according to the setting can be checked. * 8-bit PWM Mode 8-bitPWM is output to the TC4 pin and COMMON pin outputs are inverted in TC4 interrupt processing. By monitoring signals output from the COMMON and C4 pins, whether the TC4 interrupt cycle and PWM output are operating according to the setting can be checked. 30 2000-05-22 TMP86CM29 The test number of TC4 test is 5. Table 5.2.17 shows the mode numbers and setting items of TC4 test. Table 5.2.17 Mode Name 8bit Timer 8bit Event Counter 8bit PDO 8bit PWM Mode No 0 1 2 3 Operating mode, TTREG4 Operating mode, High-/Low-frequency selection, TTREG4, TC4 source clock, TTF Operating mode, High-/Low-frequency selection, TREG4, TC4 source clock, TTF Modes and Setting Items of TC4 Test Setting Item Operating mode, High-/Low-frequency selection, TTREG4, TC4 source clock Table 5.2.18 to Table 5.2.21 show the register set values for each setting pattern. Table 5.2.18 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fs (0x10) fc (0x00) fs/23(0x08) fs/23(0x08) NORMAL(0xC0) fc/2 (0x38) 3 Register Set Values for TC4 8-bit Timer Frequency Selection (TC4CR) fc/211(0x08) fc/27(0x18) fc/25(0x28) fc (0x00) (TTREG4) (0x04) (0xC8) (0x19) (0x3F) (0x0E) (0x32) (0x01) (0x05) (0x32) (0x64) (0xC8) (0xFF) (0x01) (0x29) (0x01) (0x29) TC4 Interrupt Cycle 1.024ms 51.2ms 400s 1.0008ms 60s 200s 1s(*) 5s(*) 50s 100s 200s 255s 244s 10.004ms 244s(*) 10.004ms Operating Mode (SYSCR2) High-/Low-Frequency Selection (TBTCR) * In these settings, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not geneated acording to the setting. Table 5.2.19 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Register Settings for TC4 8-bit Event Counter (TC4CR) (TTREG4) (0xFF) (0x7F) (0x3F) (0x1F) (0x0F) (0x08) (0x02) (0x01) (0xFF) (0x7F) (0x3F) (0x1F) (0x0F) (0x08) (0x02) (0x01) Operating Mode (SYSCR2) NORMAL(0xC0) (0x78) SLOW(0xE0) 31 2000-05-22 TMP86CM29 Table 5.2.20 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fc (0x00) fs (0x10) NORMAL(0xC0) fc (0x00) (0x19) (0x29) (0x39) (0x09) (0x09) (0x89) (0x09) fs/23 SET CLR fc/27 fc/25 fc/23 CLR (0x09) Operating Mode (SYSCR2) Register Settings for TC4 8-bit PDO Mode Frequency Selection (TC4CR) (TTREG4) Frequency High-/Low-Frequency Selection (TBTCR) TFF CLR SET (0x04) (0x28) (0x64) (0xC8) (0x3F) (0xFA) (0x05) (0x32) (0x02) (0xC8) (0x29) (0xCD) (0x29) (0xCD) Inversion Interval 1.024ms 10.24ms 25.6ms 51.2ms 1ms 4ms 20s(*) 200s 2s(*) 200s 10ms 50ms 10ms 50ms (0x09) (0x89) fc/211 * In these settings, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not generated according to the seting. Table 5.2.21 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) NORMAL(0xC0) Operating Mode (SYSCR2) Register Settings for TC4 8-bit PWM (TC4CR) (PWREG4) fc (0x0A) (0x8A) (0x2A) (0xAA) (0x5A) (0xDA) (0x4A) (0xCA) (0x6A) (0xEA) (0x0A) (0x8A) (0x0A) (0x8A) (0x4A) (0xCA) fc/211 fc/25 fc/2 fs fc fs/23 fs/2 fs 3 High-/Low-Frequency Selection (TBTCR) TTF CLR SET CLR SET CLR SET CLR SET CLR SET CLR SET CLR SET CLR SET (0x40) Inversion Interval 16.38ms 256s 16s(*) 1.95ms 8s(*) fc (0x00) fs (0x10) 15.616ms fc (0x00) 1.95ms * In these settings, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not generated according to the seting. 32 2000-05-22 TMP86CM29 5.2.3.7 16-bit TC3 + 4 Test [Test number: 6] The 16-bit TC3 + 4 test has the following four modes: * 16-bit Timer Mode The 16-bit timer is activated and COMMON pin outputs are inverted in TC4 interrupt processing. By monitoring the COMMON pin, the TC4 interrupt cycle can be measured to check whether the 16-bit timer mode is operating according to the setting. 16-bit Event Counter Mode By using the counter by input pulses from the ECIN pin, TC4 interrupts are generated and COMMON pin outputs are inverted in TC4 interrupt processing. By monitoring the COMMON pin, the TC4 interrupt cycle can be measured to check whether the 16-bit event counter mode is operating according to the setting. 16-bit PWM Mode 16-bit PWM is output to the TC4 pin and COMMON pin outputs are inverted in TC4 interrupt processing. By monitoring signals output from the COMMON and TC4 pins, the TC4 interrupt cycle and PWM output can be measured to check whether the 16-bit PWM mode is operating according to the setting. 16-bit PPG Mode 16-bit PPG is output to the TC4 pin and COMMON pin outputs are inverted in TC4 interrupt processing. By monitoring signals output from the COMMON and TC4 pins, the TC4 interrupt cycle and PPG output can be measured to check whether the 16-bit PPG mode is operating according to the setting. * * * The test number of 16-bit TC3 + 4 test is 6. Table 5.2.22 shows the mode numbers and setting items of 16-bit TC3 + 4 test. Table 5.2.22 Mode Name 16-bit Timer Mode 16-bit Event Counter Mode 16-bit PDO Mode 16-bit PPG Mode Mode No 0 1 2 3 Modes and Setting Items of 16-bit TC3 + 4 Test Setting Item Operating mode, High-/Low-frequency selection, TTREG3, TTREG4, TC4 source clock Operating mode, TTREG3, TTREG4 Operating mode, High-/Low-frequency selection, PWREG3, PWREG4, TC4 source clock, TTF Operating mode, High-/Low-frequency selection, TTREG3, TTREG4, PWREG3, PWREG4, TC4 source clock, TTF 33 2000-05-22 TMP86CM29 Table 5.2.23 to Table 5.2.26 show the register set values for each setting pattern. Table 5.2.23 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fs (0x10) fs/23(0x08) fc (0x00) NORMAL(0xC0) (0x0C) fc/2 (0x38) 3 Register Set Values for TC3 + 4 16-bit Timer Frequency Selection (TC3CR) fc/211(0x08) fc/27(0x18) fc/25(0x28) fc (0x00) (TC4CR) (TTREG34) (0x0001) (0x0F42) (0x0001) (0xF424) (0x0005) (0xC350) (0x0100) (0x0014) (0x0064) (0x03E8) (0x2710) (0xC350) (0x0001) (0x1002) (0x0001) (0x1002) TC34 Interrupt Cycle 256s 1s 16s 1s 20s 200ms 1s(*) 20s 100s 1ms 10ms 50ms 244s 1s 244s(*) 1s Operating Mode (SYSCR2) High-/Low-Frequency Selection (TBTCR) * In these settngs, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not genrated according to the setting. Table 5.2.24 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Register Set Values for TC3 + 4 16-bit Event Counter (TC3CR) (TC4CR) (TTREG34) (0xFFFF) (0x7FFF) (0x3FFF) (0x1FFF) (0x0FFF) (0x07FF) (0x03FF) (0x01FF) (0x00FF) (0x007F) (0x001F) (0x000F) (0x0002) (0xFFFF) (0x7FFF) (0x00FF) Operating Mode (SYSCR2) NORMAL(0xC0) (0x78) (0x0C) SLOW(0xE0) 34 2000-05-22 TMP86CM29 Table 5.2.25 Setting No Operating Mode (SYSCR2) Register Set Values for TC3 + 4 16-bit PWM High-/Low-Frequency Selection (TBTCR) Frequency Selection (TC3CR) TTF (TC4CR) (TTREG 34) Inversion Interval 4.19s CLR(0x0E) 262.144ms (0x4000) 65.536ms 16.384ms (0x2000) 8.191ms 4.0955ms 2.04775ms 1.023875ms 511.9375s 499.712ms 4.096ms (0x4000) 2.048ms 3.997696s 3.997696s 499.712ms 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fs (0x10) fc (0x00) NORMAL(0xC0) fc (0x00) fc/211(0x0B) fc/27(0x1B) fc/25(0x2B) SET(0x8E) fc/23(0x3B) (0x1000) (0x0800) (0x0400) (0x0200) fs(0x4B) fc/2(0x5B) fc(0x6B) fs/23(0x0B) fs/23(0x0B) fs(0x4B) CLR(0x0E) Table 5.2.26 Setting No Operating Mode (SYSCR2) High-/LowFrequency Selection (TBTCR) Register Set Values for TC3 + 4 16-bit PWM Frequency Selection (TC3CR) fc/211(0x0B) TFF (TC4CR) CLR(0x0F) SET(0x8F) CLR(0x0F) SET(0x8F) CLR(0x0F) SET(0x8F) CLR(0x0F) SET(0x8F) fc/23(0x3B) CLR(0x0F) SET(0x8F) CLR(0x0F) SET(0x8F) (0x4E20) (0x0014) (0x0005) (0x9C40) (TTREG 34) (PWREG 34) Inversion Interval Interrupt Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW (0xE0) fs (0x10) NORMAL (0xC0) fc (0x00) (0x0640) (0x0190) 100ms 400ms fc/27(0x1B) (0x09c4) (0x0271) 10ms 40ms fc/25(0x2B) (0x2710) (0x09C4) 10ms 40ms (0x2710) (0x1388) (0x2710) (0x000A) (0x0001) 10ms 5ms 10ms 10s 1s(*) 40ms 40ms 20ms 20s 5s CLR(0x0F) fs/23(0x0B) SET(0x8F) CLR(0x0F) SET(0x8F) (0x0668) (0x019A) 100ms 400ms fc (0x00) * Because the inversion interval is short, inversion waveforms may not be output properly. Also, interrupts may not be generated according to the setting. 35 2000-05-22 TMP86CM29 5.2.3.8 TC5 Test [Test number: 7] The TC5 test has only the TC5 timer mode. In this test, by activating the 8-bit timer, TC5 interrupts are generated and COMMON pin outputs are inverted in TC5 interrupt processing. By monitoring the COMMON pin output, the TC5 interrupt cycle can be measured to check whether TC5 is operating according to the setting. The test number of TC5 test is 7. No mode selection is performed. In this test, each setting pattern specifies the operating mode, high-/low-frequency selection, TTREG5, and TC5 source clock. Table 5.2.27 shows the register set values for each setting pattern. Table 5.2.27 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fs (0x10) fc (0x00) fs/23(0x08) fs/23(0x08) NORMAL(0xC0) fc/2 (0x38) 3 Register Set Values for TC5 Test Frequency Selection (TC5CR) fc/211(0x08) fc/2 (0x18) fc/25(0x28) 7 Operating Mode (SYSCR2) High-/Low-Frequency Selection (TBTCR) (TTREG5) (0x04) (0xC8) (0x19) (0x3F) (0x0E) (0x32) (0x01) (0x05) (0x32) (0x64) (0xC8) (0xFF) (0x01) (0x29) (0x01) (0x29) TC5 Interrupt Cycle 1.024ms 51.2ms 400s 1.0008ms 60s 200s 1s(*) 5s(*) 50s 100s 200s 255s 244s 10.004ms 244s(*) 10.004ms fc (0x00) * In these settings, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not generated according to the setting. 36 2000-05-22 TMP86CM29 5.2.3.9 TC6 Test [Test number: 8] The TC6 test has the following four modes: * 8-bit Timer Mode The 8-bit timer is activated and COMMON pin outputs are inverted in TC6 interrupt processing. By monitoring the COMMON pin, the TC6 interrupt cycle can be measured to check whether the 8-bit timer mode is operating according to the setting. 8-bit Event Counter Mode By using the counter by input pulses from the ECIN pin, TC6 interrupts are generated and COMMON pin outputs are inverted in TC6 interrupt processing. By monitoring the COMMON pin, the TC6 interrupt cycle can be measured to check whether the 8-bit event counter mode is operating according to the setting. 8-bit PDO Mode 8-bit PDO is output to the TC6 pin and COMMON pin outputs are inverted in TC6 interrupt processing. By monitoring signals output from the COMMON and C6 pins, the TC6 interrupt cycle and PDO output can be measured to check whether the 8-bit PDO mode is operating according to the setting. 8-bit PWM Mode 8-bit PWM is output to the TC6 pin and COMMON pin outputs are inverted in TC6 interrupt processing. By monitoring signals output from the COMMON and TC6 pins, whether the TC6 interrupt cycle and PWM output are operating according to the setting can be checked. * * * The test number of TC6 test is 8. Table 5.2.28 shows the mode numbers and setting items of TC6 test. Table 5.2.28 Mode Name 8bit Timer Mode 8bit Event Counter Mode 8bit PDO Mode 8bit PWM Mode Mode No 0 1 2 3 Modes and Setting Items of TC6 Test Setting Item Operating mode, High-/Low-frequency selection, TTREG6, TC6 source clock Operating mode, TTREG6 Operating mode, High-/Low-frequency selection, TTREG6, TC6 source clock, TTF Operating mode, High-/Low-frequency selection, PWREG6, TC6 source clock, TTF 37 2000-05-22 TMP86CM29 Table 5.2.29 to Table 5.2.32 show the register set values for each setting pattern. Table 5.2.29 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fs (0x10) fc (0x00) fs/23(0x08) fs/23(0x08) NORMAL(0xC0) fc/2 (0x38) 3 Register Set Values for TC6 8-bit Timer High-/Low-Frequency Selection (TBTCR) Frequency Selection (TC6CR) fc/211(0x08) fc/27(0x18) fc/25(0x28) fc (0x00) (TTREG6) (0x04) (0xC8) (0x19) (0x3F) (0x0E) (0x32) (0x01) (0x05) (0x32) (0x64) (0xC8) (0xFF) (0x01) (0x29) (0x01) (0x29) TC3 Interrupt Cycle 1.024ms 51.2ms 400s 1.0008ms 60s 200s 1s(*) 5s(*) 50s 100s 200s 255s 244s 10.004ms 244s(*) 10.004ms Operating Mode (SYSCR2) * In these settings, because the interupt cycle is shorter than the interrupt processing time, interrupts are not generated according to the setting. Table 5.2.30 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Register Set Values for TC6 8-bit Event Counter (TC6CR) (TTREG6) (0xFF) (0x7F) (0x3F) (0x1F) (0x0F) (0x08) (0x02) (0x01) (0xFF) (0x7F) (0x3F) (0x1F) (0x0F) (0x08) (0x02) (0x01) Operating Mode (SYSCR2) NORMAL(0xC0) (0x78) SLOW(0xE0) 38 2000-05-22 TMP86CM29 Table 5.2.31 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fc (0x00) fs (0x10) NORMAL(0xC0) fc (0x00) (0x19) (0x29) (0x39) (0x09) (0x09) (0x89) (0x09) fs/23 SET CLR fc/27 fc/25 fc/23 CLR (0x09) Operating Mode (SYSCR2) Register Set Values for TC6 8-bit PDO Frequency Selection (TC6CR) (TTREG6) Frequency High-/Low-Frequency Selection (TBTCR) Inversion Interval TFF CLR SET (0x04) (0x28) (0x64) (0xC8) (0x3F) (0xFA) (0x05) (0x32) (0x02) (0xC8) (0x29) (0xCD) (0x29) (0xCD) 1.024ms 10.24ms 25.6ms 51.2ms 1ms 4ms 20s(*) 200s 2s(*) 200s 10ms 50ms 10ms 50ms (0x09) (0x89) fc/2 11 * In these settings, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not generated according to the setting. Table 5.2.32 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) NORMAL(0xC0) Operating Mode (SYSCR2) Register Set Values for TC6 8-bit PWM (TC6CR) (PWREG6) fc (0x0A) (0x8A) (0x2A) (0xAA) fc (0x00) (0x5A) (0xDA) (0x4A) (0xCA) (0x6A) (0xEA) fs (0x10) (0x0A) (0x8A) (0x0A) fc (0x00) (0x8A) (0x4A) (0xCA) fc/211 fc/25 fc/22 fs fc fs/23 fs/2 fs 3 High-/Low-Frequency Selection (TBTCR) TTF CLR SET CLR SET CLR SET CLR SET CLR SET CLR SET CLR SET CLR SET (0x40) Inversion Interval 16.38ms 256s 16s(*) 1.95ms 8s(*) 15.616ms 1.95ms * In these settings, because the interrupt cycle is shorter thatn the interrupt processing time, interrupts are not generated according to the setting. 39 2000-05-22 TMP86CM29 5.2.3.10 16-bit TC5 + 6 Test [Test number: 9] The 16-bit TC5 + 6 test has the following three modes: * 16-bit Timer Mode The 16-bit timer is activated and COMMON pin outputs are inverted in TC6 interrupt processing. By monitoring the COMMON pin, the TC6 interrupt cycle can be measured to check whether the 16-bit timer mode is operating according to the setting. * 16-bit PWM Mode 16-bit PWM is output to the TC6 pin and COMMON pin outputs are inverted in TC6 interrupt processing. By monitoring the COMMON and TC6 pins, the TC6 interrupt cycle and PWM output can be measured to check whether the 16-bit PWM mode is operating according to the setting. * 16-bit PPG Mode 16bit PPG is output to the TC6 pin and COMMON pin outputs are inverted in TC6 interrupt processing. By monitoring the COMMON and TC6 pins, the TC6 interrupt and PPG output can be measured to check whether the 16-bit PPG mode is operating according to the setting. The test number of 16-bit TC5 + 6 test is 9. Table 5.2.33 shows the modes and setting items of 16-bit TC5 + 6 test. Table 5.2.33 Mode Name 16bit Timer Mode 16bit PDO Mode 16bit PPG Mode Mode No 0 1 2 Modes and Setting Items of TC6 Test Setting Item Operating mode, High-/Low-frequency selection, TTREG5, TTREG6, TC6 source clock Operating mode, High-/Low-frequency selection, PWREG5, PWREG6, TC6 source clock, TTF Operating mode, High-/Low-frequency selection, TTREG5, TTREG6, PWREG5, PWREG6, TC6 source clock, TTF Table 5.2.34 to Table 5.2.36 show the register set values for each setting pattern. Table 5.2.34 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fs (0x10) fs/23(0x08) fc (0x00) NORMAL(0xC0) (0x0C) fc/23(0x38) fc (0x00) Operating Mode (SYSCR2) Register Set Values for TC5 + 6 16-bit Timer Frequency Selection (TC5CR) fc/211(0x08) fc/27(0x18) fc/25(0x28) (TC6CR) (TTREG56) (0x0001) (0x0F42) (0x0001) (0xF424) (0x0005) (0xC350) (0x0100) (0x0014) (0x0064) (0x03E8) (0x2710) (0xC350) (0x0001) (0x1002) (0x0001) (0x1002) TC56 Interrupt Cycle 256s 1s 16s 1s 20s 200ms 1s(*) 20s 100s 1ms 10ms 50ms 244s 1s 244s(*) 1s High-/Low-Frequency Selection (TBTCR) * In these settings, because the interrupt cycle is shorter than the interrupt processing time, interrupts are not generated according to the setting. 40 2000-05-22 TMP86CM29 Table 5.2.35 Setting Item 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fs (0x10) fc (0x00) fs(0x4B) fc/2(0x5B) fc(0x6B) fs/23(0x0B) fs/23(0x0B) fs(0x4B) (0x4000) CLR(0x0E) NORMAL(0xC0) fc (0x00) fc/23(0x3B) SET(0x8E) (0x2000) (0x1000) (0x0800) (0x0400) (0x0200) Operating Mode (SYSCR2) Register Set Values for TC5 + 6 16-bit PWM Frequency Selection (TC5CR) fc/211(0x0B) fc/27(0x1B) fc/25(0x2B) CLR(0x0E) (0x4000) TTF (TC6CR) (TTREG56) Inversion Interval 4.19s 262.144ms 65.536ms 16.384ms 8.191ms 4.0955ms 2.04775ms 1.023875ms 511.9375s 499.712ms 4.096ms 2.048ms 3.997696s 3.997696s 499.712ms High-/Low-Frequency Selection (TBTCR) Table 5.2.36 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW (0xE0) fs (0x10) NORMAL (0xC0) fc (0x00) Operating Mode (SYSCR2) Register Set Values for TC5 + 6 16-bit PPG Frequency Selection (TC5CR) fc/211(0x0B) fc/27(0x1B) fc/25(0x2B) TFF (TC6CR) CLR(0x0F) SET(0x8F) CLR(0x0F) SET(0x8F) CLR(0x0F) SET(0x8F) CLR(0x0F) SET(0x8F) fc/23(0x3B) CLR(0x0F) SET(0x8F) CLR(0x0F) SET(0x8F) CLR(0x0F) fs/23(0x0B) SET(0x8F) CLR(0x0F) SET(0x8F) (0x0668) (0x019A) 100ms 400ms (0x4E20) (0x0014) (0x0005) (0x9c40) (TTREG 56) (0x0640) (0x09C4) (0x2710) (PWREG 56) (0x0190) (0x0271) (0x09C4) (0x2710) (0x1388) (0x2710) (0x000A) (0x0001) Inversion Interval 100ms 10ms 10ms 10ms 5ms 10ms 10s 1s Interrupt Cycle 400ms 40ms 40ms 40ms 40ms 20ms 20s 5s High-/LowFrequency Selection (TBTCR) fc (0x00) * Because the inversion interval is short, inversion waveforms may not be ourput properly. Also, interrupts may not be generated according to the setting. 41 2000-05-22 TMP86CM29 5.2.3.11 UART Test [Test number: 10] The UART test has the following two modes: * UART Tx (UART Transmit Test ) Mode Data is transmitted from the TXD pin and COMMON pin outputs are inverted in UART Tx interrupt processing. By monitoring the COMMON pin as well as the UART transmit data output from the TXD pin, whether UART Tx is operating according to the setting can be checked. UART Rx (UART Receive Test) Mode Data is received from the RXD pin and COMMON pin outputs are inverted in UART Rx interrupt processing. By monitoring the COMMON pin as well as displaying on LCD the UART receive data input from the RXD pin, whether UART Rx is operating according to the setting can be checked. * The test number of UART test is 10. Table 5.2.37 shows the mode numbers and setting items of UART test. Table 5.2.37 Mode Name UART Tx Mode UART Rx Mode Mode No 0 1 Modes and Setting Items of UART Test Setting Item Operating mode, Transmit stop bit length, Parity, Transfer clock, TTREG5, TC5 source clock, Transfer data Operating mode, Receive stop bit length, Parity, Transfer clock, TTREG5, TC5 source clock (In the UART test, noise cancellation is set to "none".) The test completed state is entered after data transfer in the UART Tx mode and after data receive in the UART Rx mode. In the test competed state, transmitted or received data is displayed on LCD. This display is made divided into three times. When the display number is 1, the 1st to 3rd words of data are displayed. When the display number is 2, the 4th to 6th words are displayed When the display number is 3, the 7th and 8th words are displayed. The 9th and 8th digits on LCD display the display number. The 7th and 6th digits display the 3rd or 6th word of transmit/receive data. The 4th and 3rd digits display the 2nd, 5th, or 8th word . The 2nd and 1st digits display the 1st, 4th, or 7th word. The display number (1 to 3) is selected with "F4 Key" input. If an error occurs during transfer, the cause of error is displayed on the 8th to 6th digits of Display Number 3. This display is made in the following manne: Table 5.2.38 Display digit 8th digit 7th digit 6th digit Error Display in UART Transfer Display Cause Overrun error Flaming error Parity error O F P If these errors occur, change the set value and transmit data again. By pressing "INT0 Interrupt Key" in the study completed state, the state returns to the test item setting state. 42 2000-05-22 TMP86CM29 LED1 LED2 LED3 LED4 9th digit 8th digit 7th digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit Display Number 3rd/6th word 2nd/5th/8th word 1st/4th/7th word Figure 5.2.4 UART Test Completed Note: In UART transmit, after data without parity and with 1-bit stop bit is output, if data is sent with parity and 2-bit stop bit, it has been observed that the TxD pin remains at "L" level and does not return to "H" level. Threfore, after a test to transmit data without parity and with 1-bit stop bit, do not perform a test to transmit data with parity and 2-bit stop bit. If tests are performed in this sequence, forciblly perform a reset with "Reset Key". The same transmit data is used for the UART transmit test and for the SIO transmit and SIO receive tests that are described in the following chapter. Table 5.2.39 shows the transmit data numbers and transmit data contents. Table 5.2.39 Transmit Data for UART Tx, SIO Tx and SIO TxRx Tests Transmit Data No (DataNo.) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Transmit Data Contents 0x10, 0x32, 0x54, 0x76, 0x98, 0xBA, 0xDC, 0xFE 0x21, 0x43, 0x65, 0x87, 0xA9, 0xCB, 0xED, 0x0F 0x32, 0x54, 0x76, 0x98, 0xBA, 0xDC, 0xFE, 0x10 0x43, 0x65, 0x87, 0xA9, 0xCB, 0xED, 0x0F, 0x21 0x54, 0x76, 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32 0x65, 0x87, 0xA9, 0xCB, 0xED, 0x0F, 0x21, 0x43 0x76, 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54 0x87, 0xA9, 0xCB, 0xED, 0x0F, 0x21, 0x43, 0x65 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76 0xA9, 0xCB, 0xED, 0x0F, 0x21, 0x43, 0x65, 0x87 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76, 0x98 0xCB, 0xED, 0x0F, 0x21, 0x43, 0x65, 0x87, 0xA9 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76, 0x98, 0xBA 0xED, 0x0F, 0x21, 0x43, 0x65, 0x87, 0xA9, 0xCB 0xFE, 0x10, 0x32, 0x54, 0x76, 0x98, 0xBA, 0xDC 0x0F, 0x21, 0x43, 0x65, 0x87, 0xA9, 0xCB, 0xED 43 2000-05-22 TMP86CM29 Table 5.2.40 and Table 5.2.41 show the register set values for each setting pattern. Table 5.2.40 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fs (0x10) fc (0x00) (0xA0) (0x88) (0x98) (0xA8) (0xB8) (0x81) (0x82) (0x83) (0x84) (0x85) (0x86) fc/26 fc/52 fc/104 fc/208 fc/416 19200 9600 4800 2400 1200 None 1bit fc/13 38400 Odd Even Odd Even 2bit 1bit (0x80) 1bit High-/Low-Frequency Selection (TBTCR) Register Set Items for UART Tx (UARTCR1) DataNo (TC5CR) (TTREG5) Frequency Baud Rate Parity StopBit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (0x28) (0x08) (0x01) (0x01) None 2bit TC5(250KHz) TC5(4KHz) Table 5.2.41 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fs (0x10) fc (0x00) (0x48) (0x58) (0x48) (0x58) (0x41) (0x42) (0x43) (0x44) (0x45) (0x46) (0x40) High-/Low-Frequency Selection (TBTCR) Register Set Items for UART Rx (UARTCR1) Frequency Baud Rate Parity StopBit (UARTCR2) (TC5CR) (TTREG5) None 1 bit (0x00) fc/13 38400 Odd Even Odd Even 2bit (0x01) 1bit (0x00) 2bit (0x01) fc/26 fc/52 fc/104 fc/208 fc/416 19200 9600 4800 2400 1200 (0x28) (0x08) (0x01) (0x01) None 1bit (0x00) TC5(250KHz) TC5(4KHz) 44 2000-05-22 TMP86CM29 5.2.3.12 SIO Test [Test number: 11] The SIO test has the following three modes: * SIO Tx (SIO Transmit) Mode SIO data is transmitted from the TxD pin and COMMON pin outputs are inverted in SIO interrupt processing. By monitoring the COMMON pin as well as the SCK and SO pins, transmit data can be measured to check whether the SIO Tx mode is operating according to the setting. SIO Rx (SIO Receive) Mode SIO data is received from the RxD pin and COMMON pin outputs are inverted in SIO interrupt processing. By monitoring the COMMON pin to measure the interrupt cycle as well as receiving data sent in synchronization with the serial clock and displaying it on LCD, whether the SIO Rx mode is operating properly can be checked. SIO TxRx (SIO Transmit/Receive) Mode SIO data is transmitted from the TxD pin and data is received from the RxD pin at the same time. COMMON pin outputs are inverted in SIO interrupt processing. By monitoring the COMMON pin to measure the interrupt cycle as well as displaying on LCD the transmit data output from the SO pin in synchronization with the serial clock and the receive data input from the SI pin, whether the SIO TxRx mode is operating according to the setting can be checked. * * The test number of SIO test is 11. Table 5.2.42 shows the mode numbers and setting items of SIO test. Table 5.2.42 Mode Name SIO Tx Mode SIO Rx Mode SIO TxRx Mode Mode No 0 1 2 Modes and Setting Items of SIO Test Setting Item Operating mode, High-/Low-frequency selection, Transmit mode, Serial clock, Transfer word number, Transmit data Operating mode, High-/Low-frequency selection, Receive mode, Serial clock, Transfer word number Operating mode, High-/Low-frequency selection, Serial clock, Transfer word number, Transmit data, WAIT control In the SIO test, 8-byte data is transferred. When transfer is made by 1 word, transfer is started again in SIO interrupt and SIO transfer is repeated until all 8-word data is transferred. For data to be transmitted, see Table 5.2.39. After 8-word data is transmitted/received, the SIO test enters the test completed state. In the test completed state, transmitted/received data is displayed on LCD. In the SIO Tx and SIO Rx modes, transmitted/received 8-word data is displayed divided into three times (display number:1 to 3). In the SIO TxRx mode, transmitted data is displayed when the display number is 1 to 3, and received data is displayed when the display number is 4 to 6. When the display number is 1 or 4, 1st to 3rd words are displayed. When the display number is 2 or 5, the 4th to 6th words are displayed. When the display number is 3 or 6, the 7th and 8th words are displayed. The display number (1 to 3, 1 to 6 in the TxRx mode) is displayed on the 9th and 8th digits on LCD. It is selected with "K4 Key" input. By pressing "INT0 Interrupt Key" in the test completed state, the state returns to the test item setting state. 45 2000-05-22 TMP86CM29 LED1 LED2 LED3 LED4 9th digit 8th digit 7th digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit Display Number 3rd/6th word 2nd/5th/8th word 1st/4th/7th word Figure 5.2.5 SIO Test Completed Table 5.2.43 to Table 5.2.45 show the register set values for each setting pattern. Table 5.2.43 Setting No Operating Mode (SYSCR2) High-/Low-Frequency Selection (TBTCR) (0x97) (0x87) (0x97) (0x87) NORMAL (0xC0) fc (0x00) (0x90) (0x80) (0x92) (0x82) (0x95) (0x85) fs (0x10) (0x90) (0x80) (0x90) SLOW(0xE0) fc (0x00) (0x80) (0x90) (0x80) Register Set Values for SIO Tx (SIOCR1) Transfer bit (SIOM) 4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8 fs/2 5 Transfer clock (SCK) Transfer word number BUF (SIOCR2) DataNo. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 External sck pin 1word(0x00) 8word(0x07) 1word(0x00) 8word(0x07) 1word(0x00) 8word(0x07) 1word(0x00) 8word(0x07) 1word(0x00) 8word(0x07) 1word(0x00) 8word(0x07) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fc/213 fc/27 fc/24 (*) 46 2000-05-22 TMP86CM29 Table 5.2.44 Setting No Operating Mode (SYSCR2) High-/Low-Frequency Selection (TBTCR) (0xB7) (0xAF) (0xB7) (0xAF) NORMAL (0xC0) fc (0x00) (0xB0) (0xA8) (0xB2) (0xAA) (0xB5) (0xAD) fs (0x10) (0xB0) (0xA8) (0xB0) SLOW(0xE0) fc (0x00) (0xA8) (0xB0) (0xA8) Register Set Values for SIO Rx (SIOCR1) Transfer bit (SIOM) 4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8 fs/25 fc/213 fc/27 fc/24 (*) External sck pin 8word(0x07) 1word(0x00) 8word(0x07) 1word(0x00) 8word(0x07) 1word(0x00) 8word(0x07) 1word(0x00) 8word(0x07) 1word(0x00) 8word(0x07) Transfer clock (SCK) Transfer word number BUF(SIOCR2) 1word(0x00) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table 5.2.45 Setting No Operating Mode (SYSCR2) High-/Low-Frequency Selection (TBTCR) Register Set Values for SIO TxRx (SIOCR1) Transfer clock (SCK) (0xA7) (0xA7) (0xA7) (0xA7) (0xA0) (0xA0) (0xA0) (0xA0) (0xA2) (0xA2) (0xA5) (0xA5) (0xA0) (0xA0) (0xA0) (0xA0) fs/25 fc/2 7 (SIOCR2) Transfer Word No BUF (0x00) (0x18) (0x07) (0x1F) (0x00) (0x18) (0x07) (0x1F) (0x00) (0x07) (0x00) (0x07) (0x00) (0x18) (0x07) (0x1F) 1word 8word 1word 8word 1word 8word 1word 8word 1word 8word 1word 8word TD Data No. WAIT TD 8TD TD 8TD TD 8TD TD 8TD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOW(0xE0) fs (0x10) fc (0x00) NORMAL (0xC0) fc (0x00) External sck pin fc/213 fc/24 * In SIO transfer, when fc/24 is selected as a serial clock, data may not be transferred properly depending on the connecting line of the SCK pin. In SIO transmit/receive (SIO TxRx), a part of receive data may not be transferred properly. 47 2000-05-22 TMP86CM29 5.2.3.13 ADC Test [Test number: 12] The ADC test has the following two modes: * Single Mode COMMON pin outputs are inverted in AD converter interrupt processing. By measuring each of analog inputs from the AIN0 pin three times and displaying results on LCD, whether the single mode is operating according to the setting can be checked. Repeat Mode COMMON pin outputs are inverted in AD converter interrupt processing. By monitoring the COMMON pin as well as measuring each of analog inputs from the AIN0 pin three times and displaying results on LCD, whether the repeat mode is operating according to the setting can be checked. * The test number of AD converter test is 12. Table 5.2.46 shows the mode numbers and setting items of AD converter test. Table 5.2.46 Mode Name Single Mode Repeat Mode Mode No 0 1 Modes and Setting Items of AD converter Test Setting Item Operating mode, Ladder resistor ON/OFF, AD conversion time Operating mode, Ladder resistor ON/OFF, AD conversion time After measurements are performed a fixed number of times, the AD converter test enters the test completed state. In the test completed state, 10-bit data after AD conversion is displayed on LCD. When the display number is 1, 2, and 3, the 1st, 2nd, and 3rd AD conversion data is displayed, respectively. The display number (1 to 3) is selected with "F4 Key" input. By pressing "INT0 Interrupt Key" in the test completed state, the state returns to the test item setting state. LED1 LED2 LED3 LED4 9th digit 8th digit 7th digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit Display 10th to 8th bits 7th to 0 bit Figure 5.2.6 ADC Test Completed 48 2000-05-22 TMP86CM29 Table 5.2.47 and Table 5.2.48 show the register set values for each setting pattern. Table 5.2.47 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (0xA0) (0x1A) (For continuous test) Register Set Values for Single Mode (ADCCR2) (ADCCR1) ACK (0x16) (0x36) (0x18) (0x38) (0x1A) (0x3A) 19.5s 39.0s 78.0s IREFON 0 1 0 1 0 1 78.0s 0 Table 5.2.48 Setting No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Register Set Values for Repeat Mode (ADCCR2) (ADCCR1) ACK (0x16) (0x36) (0x18) (0x38) (0x1A) (0x3A) 19.5s 39.0s 78.0s IREFON 0 1 0 1 0 1 (0xE0) (0x1A) (For continuous test) 78.0s 0 49 2000-05-22 TMP86CM29 5.2.3.14 LCD Test [Test number: 13] The LCD test checks the operation of LCD by lighting segments of LCD one by one. When the LCD test is started, one segment in the 1st digit lights up. Each time "F4 Key" is pressed, the lighted segment changes. By this operation, LCD lights can be checked. To end the LCD test, press "INT0 Interrupt Key". F4 Key input F4 Key input Figure 5.2.7 LCD Display Test [13-0-0] 5.2.3.15 Continuous Test [Test number: 14] In the continuous test, tests can be performed one after another continuously. "INT0 Interrupt Key" ends each test and starts the next test. The setting number that is set at the start is applied to all tests. In other words, when the setting number 0 is selected, all tests (TBT test, watchdog timer test, etc) are performed with the setting number 0. For details of each test, see the test items for each test. In the continuous test, the 9th digit on LCD displays "A", the 6th and 7th digits display the test number, the 4th digit displays the test mode, and the 1st and 2nd digits display the setting number. Figure 5.2.8 shows an example of LCD display when a test of test number 3, mode 0, setting number 1 (TC1 timer test) is executed. 50 2000-05-22 TMP86CM29 LED1 LED2 LED3 LED4 9th digit 8th digit 7th digit 6th digit 5th digit 4th digit 3rd digit 2nd digit 1st digit Figure 5.2.8 In the continuous test, the following tests are performed: Table 5.2.49 Test No 0 1 2 Mode No 0 0 0 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 0 1 2 3 0 1 2 0 1 0 1 2 0 1 TBT test WDT test DVO test Description of Continuous Test Description of Test Time Base Timer Interrupt request DVO 18-bit timer 18-bit event counter Pulse width measurement Frequency measurement 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter 16-bit PWM 16-bit PPG 8-bit timer 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit PWM 16-bit PPG Tx Rx SIO Tx SIO Rx SIO TxRx Single mode Repeat mode 3 TC1 test 4 TC3 test 5 TC4 test 6 TC3 + 4 test 7 TC5 test 8 TC6 test 9 TC5 + 6 test 10 UART test 11 SIO test 12 ADC test 51 2000-05-22 TMP86CM29 5.3 ROM/RAM Check Mode In ROM/RAM Check mode, tests on internal ROM and RAM in the microcontroller are performed. All LEDs are "OFF" in this mode. When ROM/RAM Check mode is entered, the 9th to 6th digits on LCD display the check sum of internal ROM. The 4th to 1st digits display the most recent address where Read/Write are not performed properly. In internal RAM check, if there is no address where Read/Write are not performed properly, the 4th to 1st digits are all lit. Key operation is not valid except for "Reset Key". After the check sum is displayed, press "Reset Key" to reset. LED1 LED2 LED3 LED4 Internal ROM Check Sum Internal RAM Abnormal Adddress Figure 5.3.1 ROM/RAM Check Mode 52 2000-05-22 TMP86CM29 6. Circuit Diagram LCD 4.7k variable resistance 47k 47k 47k open x5 open 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 24 57 23 58 22 59 21 60 20 61 19 62 18 63 17 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1S1588 x4 TMP86CM29 47k TC74HC125AP TC74HC125AP 4HC125 10 Clock Oscillator 4.7k x TLN105A TC74AC04 47 x11 30pF x4 8 MHz 32.768 kHz LED ST/RE 100k POWER 330 LED5 100k RESET F2 0.1 F SW1 20k variable resistance 100k INT0 F1 4.7k 1.5k 3.3k SW2 20k 10k variable resistance F3 F4 AIN5 VSS DVO TC4 ECIN RxD/SI SCK VDD COMMON TC3 TC6 ECNT TxD/SO AIN0 Figure 6.1 Circuit Diagram 53 2000-05-22 Buzzer 330 x5 47k x5 TMP86CM29 SEG15 SEG15 SEG14 SEG14 SEG13 SEG13 SEG12 SEG12 SEG11 SEG10 SEG11 SEG10 SEG9 SEG8 SEG9 SEG SEG8 SEG SEG7 SEG6 SEG SEG SEG5 SEG7 SEG4 SEG6 SEG3 SEG5 SEG2 SEG4 SEG1 SEG0 SEG3 COM3 SEG2 COM2 SEG1 COM1 SEG0 COM0 COM0 COM1 COM2 COM3 Figure 6.2 LCD Wiring 54 2000-05-22 TMP86CM29 Postscript This document describes the specifications of the demonstration set for the 8-bit microcontroller TMP86Cx29. The information contained herein is subject to change without prior notice as a result of future technical advancement. All examples employed herein are used as reference for the purpose of explanation. Toshiba No part of corporation disclaims all responsibilities for problems that may result from usnig any of these examples. this publication may be reproduced or distributed without the prior written permission of Toshiba Corporation. If you have any questions regarding TOSHIBA microcomputers, please contact Toshiba branch offices, area offices or sales offices. 2000.05 2000-05-22 |
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