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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91PW10
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts (NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP91PW10
Low-Voltage CMOS 16-Bit Microcontroller
TMP91PW10F 1. Outline and Device Characteristics
The TMP91PW10 is an OTP-type MCU which includes a 128-K one-time programmable ROM. Data for TMP91PW10 can be written and verified using the adapter socket. The TMP91PW10 has the same pin-assignment as the TMP91CU10 (mask ROM-type). A program can be written to the TMP91PW10's built-in PROM in the same way as on the TMP91CU10.
000000H Internal I/O 000080H Internal RAM
001C80H
External Area
FE0000H
Internal ROM (128 KB)
FFFF00H Reserved FFFFFFH
Figure 2.1.1 Memory map of TMP91PW1
MCU TMP91PW10F ROM 128-Kbyte OTP RAM 4 Kbytes Package QFP100 Adapter Socket BM11129
000707EBP1
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice.
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TMP91PW10
AN0 to AN7 (P50 to P57) AVcc AVss VREFL VREFH 10-BIT 8-CH A/D CONVERTER
DVCC [3] CPU (TLCS-900/H) DVSS [3] OSC1 Clock Gear OSC2 XT1 (P96) XT2 (P97) CLK ALE EA
RESET
X1 X2
TXD0 (P90) RXD0 (P91) SCLK0/ CTS0 (P92) TXD1 (P93) RXD1 (P94) SCLK1 (P95) TXD2 (P60) RXD2 (P61) SCLK2/ CTS2 (P62) TI0/INT1 (P70) TO1 (P71) 8-BIT TIMER (TIMER 0) 8-BIT TIMER (TIMER 1) 8-BIT TIMER (TIMER 2) TO3/INT2 (P72) TI4/INT3 (P73) TO5 (P74) 8-BIT TIMER (TIMER 3) 8-BIT TIMER (TIMER 4) 8-BIT TIMER (TIMER 5) 8-BIT TIMER (TIMER 6) TO7/INT4 (P75) 8-BIT TIMER (TIMER 7) SERIAL I/O (CH.2) SERIAL I/O (CH.1) SERIAL I/O (CH.0)
XWA XBC XDE XHL XIX XIY XSP
W B D H
A C E L
IX IY IZ SP 32 bits SR F PC
RD (P30)
WATCHDOG TIMER
WR (P31) HWR (P32) BUSRQ (P34) BUSAK (P35) R/ W (P36) AM8/ 16 P37 (P00 to P07) AD0 to AD7 (P10 to P17) AD8/A8 to AD15/A15 (P20 to P27) A0/A16 to A7/A23 *PA0 to PA7 P63, P65 to P67
PORT 0
4 KB RAM
PORT 1 PORT 2
PORT A PORT 6
128 KB RAM
CS/WAIT CONTROLLER (3-BLOCK)
CS0 (P40) CS1 (P41) CS2 (P42) WAIT (P33) NMI INTO (P64)
INTERRUPT CONTROLLER
16-BIT TIMER (TIMER 8)
TI8/INT5 (P80) TI9/INT6 (P81) TO8 (P82) TO9 (P83) TIA/INT7 (P84)
16-BIT TIMER (TIMER 9)
TIB/INT8 (P85) TOA/TOB (P86)
( ) : Default function after reset Figure 2.1.2 TMP91PW10 Block Diagram
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2.
Pin Assignment and Functions
The assignment of input and output pins for the TMP91PW10, their names and functions are described as follows:
2.1
Pin Assignment
Figure 2.1.1 shows the pin assignment of the TMP91PW10.
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P65 P64/INT0 P63 P62/SCLK2/CTS2 P61/RXD2 P60/TXD2 P42/CS2 P41/CS1 P40/CS0 P37 P36/R/W P35/BUSAK P34/BUSRQ P33/WAIT P32/HWR P31/WR P30/RD P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 P21/A1/A17 P20/A0/A16 DVCC DVSS NMI P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 P10/AD8/A8 P07/AD7 P06/AD6
P66 P67 DVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC P70/TI0/INT1 P71/TO1 P72/TO3/INT2 P73/TI4/INT3 P74/TO5 P75/TO7/INT4 P80/TI8/INT5 P81/TI9/INT6 P82/TO8 P83/TO9 P84/TIA/INT7 P85/TIB/INT8 P86/TOA/TOB P90/TXD0 P91/RXD0 P92/SCLK0/CTS0 P93/TXD1 P94/RXD1 P95/SCLK1 AM8/16 CLK DVCC
89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
DVSS X1 X2 EA RESET P96/XT1 P97/XT2 TEST1 TEST2 PA0 PA1 PA2
26 27 28 29 30 31 32 33 34 35 36 37
50 49 48 47 46 45 44 43 42 41 40 39 38
P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 DVCC ALE PA7 PA6 PA5 PA4 PA3
Figure 2.1.1 Pin Assignment diagram
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2.2
Pin Names and Functions
The names of the input/output pins and their functions are described in Table 2.2.1. Table 2.2.1 Pin names and Functions (1/3)
Pin name
P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30
RD
Number of pins
8 8
I/O
I/O I/O I/O I/O Output I/O Output Output Output Output Output Output I/O Output I/O Input I/O Input
Functions
Port 0: I/O port that allows I/O to be selected at the bit level Address (lower): Bits 0 to 7 for address and data bus Port 1: I/O port that allows I/O to be selected at the bit level Address and data (upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 for address bus Port 2: I/O port that allows I/O to be selected at the bit level (with pull-up resistor) Address: Bits 0 to 7 for address bus Address: Bits 16 to 23 for address bus Port 30: Output port Read: Strobe signal for reading external memory When P3 = 0 and P3FC = 1, RD is output and internal memory is read. Port 31: Output port Write: Strobe signal for writing data to pins D0 to 7 Port 32: I/O port (with pull-up resistor) High Write: Strobe signal for writing data to pins D8 to 15 Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU Bus Wait Port 34: I/O port (with pull-up resistor) Bus Request: Signal used to request high impedance on pins D0 to 15, A0 to 23, RD ,
WR , HWR , CS0 , CS1 and CS2 .
8
1
P31
WR
1 1 1 1
P32 HWR P33 WAIT P34
BUSRQ
P35
BUSAK
1
I/O Output I/O Output I/O I/O Output I/O Output I/O Output Input Input I/O Output I/O Input I/O I/O Input I/O I/O Input I/O
Port 35: I/O port (with pull-up resistor) Bus Acknowledge: Signal used to acknowledge high impedance on pins D0 to 15, A0 to 23, RD , WR , HWR , CS0 , CS1 and CS2 by receiving BUSRQ . Port 36: I/O port (with pull-up resistor) Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle. Port 37: I/O port Port 40: I/O port (with pull-up resistor) Chip Select 0: Outputs 0 when address is within specified address area. Port 41: I/O port (with pull-up resistor) Chip Select 1: Outputs 0 when address is within specified address area. Port 42: I/O port (with pull-down resistor) Chip Select 2: Outputs 0 when address is within specified address area. Port 5: Input port Analog input: Pin used to input to AD converter Port 60: I/O port (level shift pin) Serial Send Data 2 Port 61: I/O port (level shift pin) Serial Receive Data 2 Port 62: I/O port (level shift pin) Serial Clock I/O 2 Serial Data Send Enable 2 (Clear to Send) Port 63: I/O port Port 64: I/O port Interrupt Request pin 0: Interrupt triggered on either level or rising edge (programmable) Port 65 to 67: I/O ports
P36 R/ W P37 P40
CS0
1 1 1 1 1 8 1 1 1
P41
CS1
P42
CS2
P50 to P57 AN0 to AN7 P60 TXD2 P61 RXD2 P62 SCLK2
CTS2
P63 P64 INT0 P65 to P67
1 1 3
Note:
A DMAC controller's internal memory or I/O devices cannot be accessed using BUSRQ and BUSAK .
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Table 2.2.1 Pin names and Functions (2/3) Pin name
P70 TI0 INT1 P71 TO1 P72 TO3 INT2 P73 TI4 INT3 P74 TO5 P75 TO7 INT4 P80 TI8 INT5 P81 TI9 INT6 P82 TO8 P83 TO9 P84 TIA INT7 P85 TIB INT8 P86 TOA TOB P90 TXD0 P91 RXD0 P92 SCLK0
CTS0
Number of pins
1
I/O
I/O Input Input I/O Output I/O Output Input I/O Input Input I/O Output I/O Output Input I/O Input Input I/O Input Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output Output I/O Output I/O Input I/O I/O Input I/O Output I/O Input I/O I/O I/O Input I/O Output
Functions
Port 70: I/O port Timer Input 0: Timer 0 input pin Interrupt Request pin 1: Interrupt request on rising edge Port 71: I/O port Timer Output 1: Timer 0 or 1 output Port 72: I/O port Timer Output 3: Timer 2 or 3 output Interrupt Request pin 2: Interrupt request on rising edge Port 74: I/O port Timer Input 4: Timer 4 input Interrupt Request pin 3: Interrupt request on rising edge Port 75: I/O port Timer Output 5: Timer 4 or 5 output Port 76: I/O port Timer Output 7: Timer 6 or 7 output Interrupt Request pin 4: Interrupt request on rising edge Port 80: I/O port Timer Input 8: Timer 8 count or capture trigger signal input Interrupt Request pin 5: Interrupt request on programmable rising / falling edge Port 81: I/O port Timer Input 9: Timer 8 count or capture trigger signal input Interrupt Request pin 6: Interrupt request on rising edge Port 82: I/O port Timer Output 8: Timer 8 output pin Port 83: I/O port Timer Output 9: Timer 9 output pin Port 84: I/O port Timer Input A: Timer 9 count or capture trigger signal input Interrupt Request pin 7: Interrupt request on programmable rising / falling edge Port 85: I/O port Timer Input B: Timer 9 count or capture trigger signal input Interrupt Request pin 8: Interrupt request on rising edge Port 86: I/O port Timer Output A: Timer A output pin Timer Output B: Timer B output pin Port 90: I/O port Serial Send Data 0 Port 91: I/O port Serial Receive Data 0 Port 92: I/O port Serial Clock I/O 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 Port 94: I/O port Serial Receive Data 1 Port 95: I/O port Serial Clock I/O 1 Port 96: I/O port (open drain output) Low-frequency oscillator connecting pin Port 97: I/O port (open drain output) Low-frequency oscillator connecting pin
1 1
1
1 1
1
1
1 1 1
1
1
1 1 1
P93 TXD1 P94 RXD1 P95 SCLK1 P96 XT1 P97 XT2
1 1 1 1 1
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Table 2.2.1 Pin names and Functions (3/3) Pin name
PA0 to PA7 ALE
NMI
Number of pins
3 1 1 1 1 1
I/O
I/O Output Input Output Input Input
Functions
Port A0 to A7: I/O ports (Level Shift port) Address Latch Enable (can be disabled for reducing noise.) Non-Maskable Interrupt Request pin: Interrupt request pin with programmable falling edge or both edges. Clock Output: Outputs (external input clock / 4) clock. Pulled up during reset The Vcc pin should be connected. Address Mode: Selects external data bus width. The Vcc pin should be connected. The data bus width for external access is set by the Chip Select / WAIT Control register and the Port 1 Control register.
CLK
EA
AM8/ 16
RESET
1 1 1 1 1 2 2 3 3
Input Input Input
Reset: Initializes LSI. (With pull-up resistor) Reference power supply input pin for AD converter (H) Reference power supply input pin for AD converter (L) Power supply pin for AD converter GND power supply pin for AD converter (0 V)
VREFH VREFL AVCC AVSS X1/X2 TEST1/TEST2 DVCC DVSS
I/O Output /Input
Oscillator connecting pin TEST1 should be connected with TEST2 pin. Power supply pin GND pin (0 V)
Note:
All pins that have built-in pull-up/pull-down resistors (other than the RESET pin) can be disconnected from their built-in pull-up/pull-down resistors by software.
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TMP91PW10
(1) PROM mode
Pin Function
A7 to A0 A15 to A8 A16 D7 to D0 CE OE
PGM
Pin Number
8 8 1 8 1 1 1 1 4 4
Input/Output
Input Input Input I/O Input Input Input Power supply Power supply Power supply
Function
Pin Name (MCU mode)
P27 to P20 P17 to P10 P33 P07 to P00 P32 P30 P31
EA
Memory address of program Memory data of program Chip enable Output control Program control 12.75 V/5 V (Power supply used for programming) 6.25 V/5 V 0V
VPP VCC VSS
VCC, AVCC VSS, AVSS
Pin Function
P34
RESET
Pin Number
1 1 1 1 1 1 7 2
Input/Output
Input Input Input Output Input Output Input Input/Output Open Crystal
Pin setting
Fix to Low level (security pin) Fix to Low level (PROM mode)
CLK ALE X1 X2 P42 to P40 P37 to P35 AM8/16 TEST1/TEST2 P57 to P50 P67 to P60 P73 to P70 P87 to P80 P97 to P90 PA7 to PA0 VREFH VREFL
NMI
Fix to High level Short
48
I/O
Open
WDTOUT
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TMP91PW10
3.
Operation
This section describes the functions and basic operations of the TMP91PW10. The TMP91PW10 has a PROM instead of the mask ROM which of the TMP91CU10. All other configuration details and functions are the same as for the TMP91CU10. For information of functions of the TMP91PW10 which are not described here, see the TMP91CU10. The TMP91PW10 has two operational modes: MCU mode and PROM mode.
3.1
MCU mode
(1) Mode setting and functions Setting the CLK pin to open selects MCU Mode. In MCU mode, operation is same as for the TMP91CU10.
3.2
Memory Map
Figure 3.2.1, Figure 3.2.1 are memory maps of theTMP91PW10. 2
000000H 000080H Internal I/O Internal RAM 001080H Internal ROM (128 KB) 00000H
External
FE0000H
Internal ROM
1FFFFH
FFFF00H FFFFFFH
Reserved
Figure 3.2.1 Memory map for MCU mode
Figure 3.2.2 Memory map for PROM mode,
3.3
PROM Mode
(1) Mode setting and functions PROM mode is set by setting the RESET and CLK pins to L. Programming and verification of the internal PROM is carried out using a general PROM programmer with an adapter socket. (1) OTP adaptor BM11129: TMP93PS40DF, TMP93PW40DF, TMP91PW10F adapters (2) Setting OTP adapter Set the switch (SW1) to N side.
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TMP91PW10
4.
4.1
Electrical Characteristics
Absolute Maximum Ratings
X used in an expression shows a frequency for the clock (fFPH) as selected by SYSCR1. The value of X changes according to whether a clock gear or a low-speed oscillator is selected. An example value of fc, is calculated with gear = 1/fc (SYSCR1 = 0000). Symbol
VCC VIN
IOL IOH
Parameter
Power Supply Voltage Input Voltage Output Current (total) Output Current (total) Power Dissipation (Ta = 8 C) Soldering Temperature (10 s) Storage Temperature Operating Temperature
Rating
0.5 to 6.5 0.5 to VCC + 0.5 120 80 600 260 65 to 150 40 to 85
Unit
V V mA mA mW C C C
PD TSOLDER TSTG TOPR
Note:
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
4.2
DC Characteristics
Parameter Symbol
VCC
Condition
fc = 4 to 13.5 MHz fs = 30 to 34 kHz (Ta = 40 to 85 C) VCC 2.7 V
Min
Typ.
(Note 1)
Max
Unit
Power Supply Voltage AVCC = VCC AVSS = VSS = 0 V AD0 to AD15 Port 2 to A (except P87, P5) Input High Voltage
RESET , NMI , INT0
2.7
3.6 0.8 0.3 VCC
V
VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL IDAR (Note2) ILI ILO
EA, AM8/ 16 X1, Port 5 AD0 to AD15 Port 2 to A (except P87)
VCC = 2.7 to 3.6 V
0.3
0.25 VCC 0.3 0.2 VCC
VCC
2.7 V
2.2 0.7 VCC 0.75 VCC VCC + 0.3
V
Input High Voltage
RESET , NMI , INT0
EA, AM8/ 16 X1
VCC = 2.7 to 3.6 V
VCC
0.3 0.45 1.0 3.5 V mA
0.8 VCC IOL = 1.6 mA (VCC = 2.7 to 3.6 V) VEXT = 1.5 V REXT = 1.1 k (VCC = 3 V 10%) 0.0 0.2 VIN VIN VCC VCC 0.2
Output Low Voltage Darlington Drive Current (8 output pins max) Input Leakage Current Output Leakage Current
0.02 0.05
5 10
mA
Note 1: Typical values are for Ta = 25 C and VCC = 5 V unless otherwise noted. Note 2: I-DAR is guranteed for total of up to 8 ports.
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Parameter
Power-down Voltage (@STOP, RAM backup) RESET Pull-up Resistor Pin Capacitance Schmitt Width
RESET , NMI , INT0
Symbol
VSTOP RRST CIO VTH PKL PKH
Condition
VIL2 = 0.2 VCC, VIH2 = 0.8 VCC VCC = 3 V 10% fc = 1 MHz
Min
2.0 30 0.4
Typ.
(Note 1)
Max
6.0 250 10
Unit
V k pF V
1.0 200 300 13 8.6 5.5 0.95 40 32 18 6 0.2 20 14 9.5 2.5 55 45 35 20 10 20 50
Programmable Pull-down Resistor Programmable Pull-up Resistor NORMAL (Note2) RUN IDLE2 IDLE1 SLOW (Note2) RUN IDLE2 IDLE1
VCC = 3 V 10% VCC = 3 V 10% Vcc = 3 V 10% fc = 12.5 MHz (Typ.: VCC = 3.0 V)
30 80
k
mA
ICC
VCC =3 V 10% fs = 32.768 kHz (Typ.: v = 3.0 V) Ta 50 C 70 C 85 C VCC = 2.0 to 3.6 V
mA
mA
STOP
Ta Ta
Note 1: Typical values are for Ta = 25 C and VCC = 3 V unless otherwise noted. Note 2: ICC measurement condition (NORMAL): All functions are operational: Output pins are open and input pins are fixed.
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4.3
AC Characteristics
(1) VCC = 3.0 V 10% V Symbol
tOSC tCLK CLK Hold ALE Fall tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW tAPH tAPH2 tAP 2.5x + 50 3.5 +100 x 2.0x 2.0x 0.5x 2.0x 0 20 40 80 32 3.5x 3.0x 2.0x + 0 2.5x 120 235 359 60 60 148 65 40 ALE Rise
RD / WR Fall RD / WR Fall
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Osc. Period (=x) CLK Width A0 to A23 Valid CLK Valid ALE Fall ALE Fall A0 to A15 Valid ALE High Width
Parameter
Value Min
72 2x 0.5x 1.5x 0.5x 0.5x x 0.5x 0.5x x 1.5x 0.5x 40 30 85 34 30 50 27 30 40 50 37 3.0x 3.5x 2.0x 55 65 45
13.5 MHz Max
31250
Min
74 108 7 26 30 7 24 10 7 34 61 0
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
A0 to A23 Hold A0 to A15 Hold
RD / WR Fall
RD / WR Rise
A0 to A15 Valid A0 to A23 Valid
RD / WR Rise
A0 to A23 Hold D0 to D15 Input D0 to D15 Input
A0 to A15 Valid A0 to A23 Valid
RD Fall
130 215 100 108 0 54 108 68 5 199 162
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
D0 to D15 Input D0 to D15 Hold A0 to A15 Output
WR Rise
RD -Low Pulse Width RD Rise RD Rise
WR -Low Pulse Width
D0 to D15 Valid
WR Rise
D0 to D15 Hold
WAIT Input WAIT Input WAIT Hold
A0 to A23 Valid A0 to A15 Valid
RD / WR Fall
(1 WAIT + n mode) (1 WAIT + n mode) (1 WAIT + n mode) A0 to A23 Valid A0 to A23 Valid A0 to A23 Valid Port Input Port Hold Port Valid
AC Measuring Conditions Output Level: High 2.2 V/Low 0.8 V, CL = 50 pF (However, CL = 100 pF for AD0 to AD15, A0 to A23, ALE RD , WR , HWR , R/ W , CLK ) Input Level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8Vcc/Low 0.2Vcc (except for AD0 to AD15)
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(2) Read Cycle
tOSC
X1 tCLK CLK tAK A0 to A23 tKA
CS0 to CS2
R/ W
tAWH tAWL tCW
WAIT
tAPH tAPH2 Port Input tADH
RD
tCA tRR
tACH tACL tLC A0 to A15 tAL tLL tLA
tRAE tHR
tRD tADL D0 to D15
AD0 to AD15
tCL
ALE
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(3) Write Cycle
X1
CLK
A0 to A23
CS0 to CS2
R/ W
WAIT
Port Output
WR , HWR
tWW
tDW AD0 to AD15 A0 to A15 D0 to D15
tWD
ALE
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4.4
AD Conversion Characteristics
AVCC = VCC, AVSS = VSS Parameter Symbol
VrefH VrefL Vain Iref (VrefL = 0 V)
Min
VCC 0.2 V VSS VrefL
Typ.
VCC VSS
Max
VCC VSS + 0.2 V VrefH
Unit
V
Analog Reference Voltage (+) Analog Reference Voltage ( ) Analog Input Voltage Range Analog Current for Analog Reference Voltage VCC = 3 V 10% = 1 VCC = 3 V 10% = 0 Error (except for quantizing errors)
0.5 0.02 1
1.5 5.0 3
mA A LSB
Note 1: LSB = (VrefH
VrefL)/2
10
V
Note 2: The operation of the AD converter is guaranteed only when fc (the high frequency oscillator) is used (it is not guaranteed when fs is used). It is guaranteed when fFPH 4 MHz Note 3: The value Icc includes the current which flows through the AVCC pin.
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4.5
Serial Channel Timing
(1) I/O Interface Mode SCLK Input Mode Parameter Symbol
tSCY Rising Edge or Falling Edge2 of SCLK tOSS
Value Min
16x tSCY/2 5 x 50 5x 100 0 tSCY 5x 100
32.768 kHz Min
488 91.5
1
13.5 MHz Min
1.18 172
Max
Max
Max
Unit
ms ns
SCLK Cycle Output Data
SCLK Rising Edge or Falling Edge SCLK Rising Edge or Falling Edge2 SCLK Rising Edge or Falling Edge2
Output Data Hold Input Data Hold Effective Data input
tOHS tHSR tSRD
152 0 336
270 0 714
ns ns ns
Note 1: System clock is fs or input clock to prescaler is divisor clock of fs. Note 2: The rising edge is used in SCLK Rising mode. The falling edge is used SCLK Falling mode. SCLK Output Mode Parameter
SCLK Cycle (Programmable) Output Data SCLK Rising Edge Output Data Hold Input Data Hold Effective Data Input
Symbol
tSCY tOSS tOHS tHSR tSRD
Variable Frequency Min
16x tSCY 2x 150 2x 80 0 tSCY 2x 150
32.768 kHz Min
488 427 60 0
1
13.5 MHz Min
1.18 886 68 0
Unit
s ns ns ns
Max
8192x
Max
250
Max
606.2
SCLK Rising Edge SCLK Rising Edge SCLK Rising Edge
428
886
ns
Note 1: System clock is fs, or input clock to prescaler is divisor clock of fs.
tSCY
SCLK SCLK Output mode (only rising edge is used) SCLK (SCLK Falling Edge mode) OUTPUT DATA
tOSS 0
tOHS 1 tSRD tHSR 1 VALID 2 VALID 3 VALID 2 3
INPUT DATA RxD
0 VALID
91PW10-19
2003-03-31
TMP91PW10
4.6
Event Counter (TI0, TI4, TI8, TI9, TIA, TIB)
Variable Frequency Min Max 13.5 MHz Unit Min
692 336 336
Parameter
Clock Cycle Low Level Clock Pulse Width High Level Clock Pulse Width
Symbol
tVCK tVCKL tVCKH
Max
ns ns ns
8X + 100 4X + 40 4X + 40
4.7
Interrupt and Capture
(1) NMI, INT0 interrupts Variable Frequency Min Max 13.5 MHz Unit Min
296 296
Parameter
NMI , INT0 to INT 4 Low Level Pulse Width NMI , INT0 High Level Pulse Width
Symbol
tINTAL tINTAH
Max
ns ns
4X 4X
(2) INT5 to INT8 interrupts, capture The INT5 to INT8 input pulse width depends on the CPU operation clock and the timer (9-bit prescaler). The following shows the pulse width for each clock. tINTBL System clock selected Prescaler clock selected
(INT5 to INT8 low level pulse width)
tINTBH
(INT5 to INT8 high level pulse width)
Unit
Variable Frequency Min
13.5 MHz Min
692 244.3 9.572
Variable Frequency Min
8X + 100 8XT + 0.1 128X + 0.1
13.5 MHz Min
692 244.3 9.572 ns
00 (fFPH) 0 (fc) 01 (fs) 10 (fc/16) 00 (fFPH) 01 (fs)
8X + 100 8XT + 0.1 128X + 0.1
s
1 (fs)
Note
8XT + 0.1
244.3
8XT + 0.1
244.3
Note1: XT shows cycle of low clock (fs). A calculation value is (fs) = 32.768 [kHz] Note2: When fs is used as the system clock, fc/16 cannot be selected as the prescaler clock.
tSCH SCOUT tSCL
91PW10-20
2003-03-31
TMP91PW10
4.8
Timing Chart for Bus Request / Bus Acknowledge
(Note 1) CLK
tBRC
BUSRQ
tBRC tCBAH
tCBAL
BUSAK
tBAA AD0 to AD15, A0 to A23, CS0 to CS2 , R/ W tABA (Note 2)
RD , WR , HWR
(Note 2)
ALE
Parameter
BUSRQ Set-up Time to CLK
Symbol
tBRC tCBAL tCBAH tABA tBAA
Value Min
120 1.5x + 120 0.5x + 40 0 0 80 80 0 0
13.5 MHz Max Min
120 231 80 77 80
Max
Unit
ns ns ns ns ns
CLK CLK
BUSAK Falling Edge BUSAK Rising Edge
Output Buffer off to BUSAK
BUSAK to Output Buffer on
Note 1: Even if the BUSRQ signal goes Low, the bus will not be released while the WAIT signal is Low. The bus will only be released when BUSRQ goes Low while WAIT is High. Note 2: This line shows only that the output buffer is in the OFF state. Just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. Therefore, to fix the signal level using an external resistor during bus release, careful design is necessary, as fixing of the level is delayed. The internal programmable pull-up/pull-down resistor is switched between the active and non-active states by the internal signal.
91PW10-21
2003-03-31
TMP91PW10
4.9
Read operation in PROM mode
DC/AC characteristics Ta = 25 Parameter Symbol
Vpp VIH1 VIL1 TACC CL = 50 pF
5 C VCC = 5 V Max Unit
V V V ns
10%
Condition
Min
4.5 2.2 0.3 -
Vpp Read Voltage Input High Voltage (A0 to A16, CE , OE and PGM ) Input High Voltage (A0 to A16, CE , OE and PGM ) Address to Output Delay
5.5 VCC + 0.3 0.8 2.25TCYC +
TCYC = 400 ns (10 MHz Clock)
= 200 ns
4.10 Program operation in PROM mode
DC/AC characteristics Ta = 25 Parameter
Programming Supply Voltage Maximum Input Voltage (D0 to D7, A0 to A16, CE , OE and PGM ) Minimum Input Voltage (D0 to D7, A0 to A16, CE , OE and PGM ) VCC Supply Current VCC Supply Current PGM Program Pulse Width
5 C VCC = 6.25 V Typ
12.75
0.25 V Unit
V V V mA mA ns
Symbol
Vpp VIH VIL ICC IPP tPW
Condition
Min
12.5 2.6 0.3
Max
13.00 VCC + 0.3 8 50 50
fc = 10 MHz VPP = 13.00 V CL = 50 pF 0.095 0.1
0.105
4.11 Timing chart of Read operation in PROM mode
A0 to A16
CE
OE
PGM
tACC D0 to D7
Data output
91PW10-22
2003-03-31
TMP91PW10
4.12 Timing chart of Program operation in PROM mode
A0 to A16
CE
OE
D0 to D7
UNKNOWN
Data-in stable
Data output
PGM
tPW
Vpp
Note 1. The power supply Vpp (12.75 V) must be turned on at the same time as or later than the power supply VCC and must be turned off at the same time as or early than the power supply VCC. Note 2. If Vpp =12.75 V, do not remove or insert the device, as this may damage it. If Vpp = 5 V the device can be removed and replaced without risk. Note 3. The maximum rating for the Vpp pin is 14.0 V. Ensure that this rating is never exceeded.
91PW10-23
2003-03-31

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