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| EASE63180 In-Circuit Emulator User's Manual MSM63180 Family Program Development Support System Second Edition, Sep 24, 1998 This manual contains important information pertaining to the safe use of the above product. Before using the product, read these safety notes thoroughly and then keep this manual handy for immediate reference. Oki Electric Industry Co., Ltd. This manual describes the setup and operation of the EASE63180 in-circuit emulator, the hardware portion of the EASE63180 development support system for developing user application programs for Oki Electric's MSM63180 family of 4-bit CMOS microcontrollers. NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit and assembly designs. 3. When developing and evaluating your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. OKI assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended only for use in development and evaluation of control programs for equipment and systems. These products are not authorized for other use (as an embedded device and a peripheral device). 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright(c) 1998 Oki Electric Industry Co., Ltd. Table of Contents Table of contents Preface --------------------------------------------------------------------------------------------------0-1 1. Product Inquiries ---------------------------------------------------------------------------------------------------- 0-2 2. Using this Product Safely and Properly--------------------------------------------------------------------- 0-3 2.1 Icons------------------------------------------------------------------------------------------------------------ 0-3 2.2 Important Safety Notes----------------------------------------------------------------------------------- 0-4 3. Notation ---------------------------------------------------------------------------------------------------------------- 0-7 4. Manual Organization----------------------------------------------------------------------------------------------- 0-8 5. Package Contents -------------------------------------------------------------------------------------------------- 0-9 5.1 Verify Shipping Contents -------------------------------------------------------------------------------- 0-9 Chapter 1. Overview ------------------------------------------------------------------------------1-1 1. 2. 3. 4. Overview -------------------------------------------------------------------------------------------------------------- 1-2 Package Components --------------------------------------------------------------------------------------------- 1-3 Configurations-------------------------------------------------------------------------------------------------------- 1-4 Names of Parts ----------------------------------------------------------------------------------------------------- 1-5 Chapter 2. Functions -----------------------------------------------------------------------------2-1 1. Emulator Specifications ------------------------------------------------------------------------------------------- 2-2 2. Functions -------------------------------------------------------------------------------------------------------------- 2-4 2.1 Configuring for Target Device ------------------------------------------------------------------------- 2-4 2.2 Evaluation Operation -------------------------------------------------------------------------------------- 2-5 2.2.1 Overview ----------------------------------------------------------------------------------------------- 2-5 2.2.2 Operation ---------------------------------------------------------------------------------------------- 2-5 2.3 Emulation Operation--------------------------------------------------------------------------------------- 2-7 2.3.1 Single-Step Emulation ------------------------------------------------------------------------------- 2-7 2.3.2 Real-time Emulation --------------------------------------------------------------------------------- 2-8 2.3.2.1 Breaks with Parameters ................................................................................. 2-10 2.3.2.2 Breaks on Specific Conditions ....................................................................... 2-15 2.3.2.3 Forced Breaks................................................................................................ 2-20 2.3.3 Other Options ----------------------------------------------------------------------------------------2-21 2.4 Code Memory Operations ----------------------------------------------------------------------------- 2-22 2.4.1 Data Operations between Code Memory and Disk Files ---------------------------------------2-22 2.4.2 Data Operations between Code Memory and EPROMs ----------------------------------------2-22 2.4.3 Displaying/Changing/Moving Code Memory ---------------------------------------------------2-23 2.4.4 Code Memory Backup-------------------------------------------------------------------------------2-23 2.4.5 Expanding Code Memory --------------------------------------------------------------------------2-24 2.5 External Memory Operations ------------------------------------------------------------------------- 2-25 2.6 Real-time Tracing ---------------------------------------------------------------------------------------- 2-26 2.6.1 Trace Entries -----------------------------------------------------------------------------------------2-27 2.6.2 Real-time Trace Control ----------------------------------------------------------------------------2-27 2.6.3 Displaying/Searching Trace Entries --------------------------------------------------------------2-30 II Table of contents 2.7 Profiling-------------------------------------------------------------------------------------------------------2-31 2.7.1 Instruction Executed (IE) Bits --------------------------------------------------------------------- 2-31 2.7.2 Cycle Counter ---------------------------------------------------------------------------------------- 2-32 2.8 Probe Cable ------------------------------------------------------------------------------------------------2-34 2.8.1 Break Signal Input ---------------------------------------------------------------------------------- 2-34 2.8.2 Sync Out Signal-------------------------------------------------------------------------------------- 2-35 2.8.3 Trace Inputs ------------------------------------------------------------------------------------------ 2-36 2.9 Clock Switching--------------------------------------------------------------------------------------------2-37 2.10 Reset Input Switching----------------------------------------------------------------------------------2-40 2.11 Internal Signal Monitoring-----------------------------------------------------------------------------2-41 2.12 Port Interface Power Supply Switching ----------------------------------------------------------2-42 2.13 LCD Bias Switching ------------------------------------------------------------------------------------2-43 2.14 DIP Switches----------------------------------------------------------------------------------------------2-45 2.14.1 BAUD Switches ------------------------------------------------------------------------------------ 2-45 2.14.2 SETICE Switch------------------------------------------------------------------------------------- 2-46 2.15 LED Indicator ---------------------------------------------------------------------------------------------2-47 2.16 Power Supplies-------------------------------------------------------------------------------------------2-48 Chapter 3. Setting Up and Starting Up --------------------------------------------------- 3-1 1. Device Configuration ---------------------------------------------------------------------------------------------- 3-2 2. Evaluation------------------------------------------------------------------------------------------------------------- 3-4 2.1 Switch and Jumper Settings---------------------------------------------------------------------------- 3-4 2.2 Emulator Connections------------------------------------------------------------------------------------- 3-9 2.3 Powering Up ------------------------------------------------------------------------------------------------3-13 3. Emulation-------------------------------------------------------------------------------------------------------------3-14 3.1 Switch and Jumper Settings---------------------------------------------------------------------------3-14 3.2 Emulator Connections------------------------------------------------------------------------------------3-20 3.3 Powering Up ------------------------------------------------------------------------------------------------3-21 Chapter 4. Additional Usage Notes--------------------------------------------------------- 4-1 1. Debugging Notes --------------------------------------------------------------------------------------------------- 4-2 2. Initialization ----------------------------------------------------------------------------------------------------------- 4-3 3. Operation Timing --------------------------------------------------------------------------------------------------- 4-4 Appendices --------------------------------------------------------------------------------------------A-1 A.1 A.2 A.3 A.4 A.5 A.6 A.7 User Cable Connectors-----------------------------------------------------------------------------------------A-2 User Cable Pin Layouts----------------------------------------------------------------------------------------A-4 Probe Cable Connectors and Pin Layout ----------------------------------------------------------------A-9 RS-232C Cable Wiring Diagrams------------------------------------------------------------------------- A-11 RS-232C Interface Circuit ----------------------------------------------------------------------------------- A-13 Installing EPROMs --------------------------------------------------------------------------------------------- A-14 If Emulator Doesn't Start ------------------------------------------------------------------------------------ A-16 III Table of contents A.8 Pin Configurations ---------------------------------------------------------------------------------------------- A-17 IV Preface Preface 1. Product Inquiries Thank you for purchasing the EASE63180 Development Support System. Please direct any comments or questions that you may have about this product to your nearest Oki Electric Industry representative. 0-2 Preface 2. Using this Product Safely and Properly 2.1 Icons This User's Guide uses various labels and icons that serve as your guides to operating this product safely and properly so as to prevent death, personal injury, and property damage. The following table lists these labels and their definitions. Labels Warning This label indicates precautions that, if ignored or otherwise not completely followed, could lead to death or serious personal injury. This label indicates precautions that, if ignored or otherwise not completely followed, could lead to personal injury or property damage. Caution Icons A triangular icon draws your attention to the presence of a hazard. The illustration inside the triangular frame indicates the nature of the hazard--in this example, an electrical shock hazard. A circular icon with a solid background illustrates an action to be performed. The illustration inside this circle indicates this action--in this example, unplugging the power cord. A circular icon with a crossbar indicates a prohibition. The illustration inside this circle indicates the prohibited action--in this example, disassembly. 0-3 Preface 2.2 Important Safety Notes Please read this page before using the product. Warning Use only the specified voltage. Using the wrong voltage risks fire and electrical shock. At the first signs of smoke, an unusual smell, or other problems, unplug the emulator and disconnect all external power cords. Continued use risks fire and electrical shock. Do not use the product in an environment exposing it to moisture or high humidity. Such exposure risks fire and electrical shock. Do not pile objects on top of the product. Such pressure risks fire and electrical shock. At the first signs of breakdown, immediately stop using the product, unplug the emulator, and disconnect all external power cords. Continued use risks fire and electrical shock. 0-4 Preface Please read this page before using the product. Caution Do not use this product on an unstable or inclined base as it can fall or overturn, producing injury. Do not use this product in an environment exposing it to excessive vibration, strong magnetic fields, or corrosive gases. Such factors can loosen or even disconnect cable connectors, producing a breakdown. Do not use this product in an environment exposing it to temperatures outside the specified range, direct sunlight, or excessive dust. Such factors risk fire and breakdown. Use only the cables and other accessories provided. Using non-compatible parts risks fire and breakdown. Do not use the cables and other accessories provided with other systems. Such improper usage risks fire. 0-5 Preface Please read this page before using the product. Caution Do not exceed the rated input voltage for the user cable VDD and VDDI pins. Doing so risks fire and breakdown. Always observe the specified order for turning equipment on and off. Using the incorrect order risks fire and breakdown. Always cut the power to the emulator before altering connections. Connection or disconnection with the power on risks fire and breakdown. Always cut the power to the emulator and the user application system before altering connections between the two. Connection or disconnection with the power on risks fire and breakdown. 0-6 Preface 3. Notation This User's Guide uses the following notational conventions. Type Numerals Units Notation xxh, xxH xxb W (word) B (byte) N (nibble) M (mega-) K (kilo-) k (kilo-) m (milli-) (micro-) n (nano-) s Meaning Hexadecimal number Binary number 1 word = 2 bytes = 4 nibbles = 16 bits 1 byte = 2 nibbles = 8 bits 1 nibble = 4 bits 106 1024 -- only in KB (kilobytes) and KW (kilowords) 3 10 = 1000 10-3 10-6 10-9 second(s) High signal level -- that is, the VDD voltage level. Low signal level -- that is, the VSS voltage level. This notation gives a cross-reference to related material elsewhere in this manual. This notation refers the reader to a numbered note providing supplementary information later in the same Section. This notation introduces a numbered note providing supplementary information. Terms Cross References "H" level "L" level n Reference n (See Note n) n Note n n 0-7 Preface 4. Manual Organization This manual consists of the following four chapters. Chapter 1. Overview This chapter introduces the emulator and its parts. Chapter 2. Functions This chapter describes the functions of the emulator. Chapter 3. Setting and Starting Up This chapter describes configuring the emulator and powering it up. Chapter 4. Additional Usage Notes This chapter contains important usage notes. Be sure to read it before using the emulator. Appendices 0-8 Preface 5. Package Contents 5.1 Verify Shipping Contents When you receive your EASE63180 development support system, check the package contents against the EASE63180 packing list. Oki Electric has every confidence that the contents are both complete and undamaged. Should a component be damaged or missing, however, please contact your nearest Oki Electric representative. 0-9 Chapter 1. Overview Chapter 1. Overview 1. Overview The EASE63180 in-circuit emulator supports the development of user application programs for the Oki MSM63180 family of 4-bit microcontrollers. 1-2 Chapter 1. Overview 2. Package Components The package contains the components listed below. Hardware EASE63180 This is the emulator unit. Manual EASE63180 User's Manual This, the document that you are now reading, is the manual for the package. Accessories AC power supply cable TCP-2 DC power supply cable TCP-63180DC RS-232C cable TCS-DRIBM Probe cable TCX-63180 User cables TCU-63180-1 TCU-63180-2 This cable plugs into the AC power supply input connector at the rear of the emulator. This cable plugs into the DC power supply input connector at the rear of the emulator. This cable connects the host computer to the emulator. This cable plugs into the probe cable connector on top of the emulator. These two cables connect the user cable connectors on top of the emulator to the user application system. USRCN1 cable: 100-pin 50-pin52 USRCN2 cable: 80-pin 40-pin52 1-3 Chapter 1. Overview 3. Configurations The emulator is used in the two configurations shown below. (1) Emulation This configuration is for high-level debugging using a dedicated debugger running on a development host. Host computer RS-232C cable User cable EASE63180 In-Circuit Emulator Probe cable User application system Dedicated debugger (2) Evaluation This configuration is for stand-alone execution of the user application program from EPROMs. EASE63180 In-Circuit Emulator User application system User cable Caution Use only the cables and other accessories provided. Using non-compatible parts risks fire and breakdown. 1-4 Chapter 1. Overview 4. Names of Parts 12 248 mm Rear view ON OFF 38400 19200 9600 4800 SETICE 3 75 mm 75 mm 186 mm POWER OFF ON DC 5V BAUD AC100~240V RS232C 45 10 Top view USR CN2 USR CN1 6 7 EVA EASE63180 MSM63E180 8 t PIN1 t PROBE t PIN32 PIN28 tt 11 9 PIN1 t PIN1 VDD VDDI VDDI SEL.1 SEL.2 IN 3V 5V MODE XT.SEL OSC.SEL EVA EMU IN EXT IN EXT PO W ER RU ER N R VC OR H EC K H AL CR T OS C EXT OKI 18 19 20 21 22 23 12 13 14 15 16 17 Front view CLOCK 83 mm 83 mm RESET 1-5 Chapter 1. Overview 1. Baud rate switches (BAUD) These switches specify the baud rate for the serial interface to the development host. 2. Device configuration switch (SETICE) This switch is used when specifying the target microcontroller with the dedicated emulator setup utility. 3. Reset switch (RESET) This switch resets the emulator and initializes its firmware. 4. AC power switch (POWER) This switch controls power to the emulator. Rapid switching on and off can prevent the main control CPU from resetting properly, leading to faulty emulator operation. 5. DC power input jack (DC5V) This connects to the DC power cable provided. 6. AC power input connector (AC IN) This connects to the AC power cable provided. 7. RS-232C connector (RS232C) This connects to the RS-232C cable provided. 8. User cable connectors (USRCN1 and USRCN2) These connect to the user cables 1 and 2 provided. 9. Probe connector (PROBE) This connects to the probe cable provided. 10. Evaluation chip socket (EVA) This accepts the MSM63E180 evaluation chip. 11. EPROM sockets (EPROM.HIGH and EPROM.LOW) These accept EPROMs containing the user application program. 12. Power supply LED (POWER) This red LED lights when power is being supplied to the emulator. 1-6 Chapter 1. 13. Execution LED (RUN) Overview This green LED lights during real-time emulation. It also may flash during emulator initialization. 14. Error LED (ERROR) This red LED lights when a problem within the emulator prevents normal operation from proceeding. It also may flash during emulator initialization. 15. Power supply check LED (VCHECK) This red LED lights when VDDI, the port interface power supply voltage, or VDD, the positive power supply voltage, falls below 0.9 V. It also may flash during emulator initialization. 16. Halt mode LED (HALT) This orange LED lights when the evaluation chip is in halt mode. 17. RC oscillation LED (CROSC) This green LED lights when RC oscillation is selected, and goes out when ceralock oscillation is selected. 18. Port/positive power supply switch 1 (VDD+VDDI.SEL1) This simultaneously switches VDDI, the port interface power supply voltage, and VDD, the positive power supply voltage, between internal and external sources. 19. Port interface power supply switch 2 (VDD.SEL2) This switches the internal power supply between 3 and 5 V. 20. Evaluation/emulation switch (MODE) This switches emulator operation between evaluation and emulation. 21. Low-speed clock switch (XT.SEL) This switches the low-speed (XT) clock between internal and external sources. 22. High-speed OSC clock switch (OSC.SEL) This switches the high-speed (OSC) clock between internal and external sources. 23. Crystal board (CLOCK) This generates the emulator's internal operating clock signals. 1-7 Chapter 2. Functions Chapter 2. Functions 1. Emulator Specifications Function Interface serial interface 4800/9600/19200/38400 bps, 8 bits, no parity, 1 stop bit, XON/XOFF flow control Program size Code memory size: up to 64 KW, depending on the microcontroller Memory backup: approx. 4 days Data storage Emulation Breaks Depending on the microcontroller Real-time emulation (evaluation and emulation configurations) Single-step emulation (emulation configuration only) Specification Breaks with parameters: Address break Address pass count break RAM data match break RAM address match break Internal ROM table data match break Internal ROM table address match break External memory data match break External memory address match break Breaks on specific conditions: Breakpoint break Trace memory full break Cycle counter overflow break External break HALT break Call stack overflow break Register stack overflow break Forced breaks: N area access break User break Real-time tracing Trace memory size: Trace conditions: Trace data: 8192 entries Free-running trace Trigger trace PC, A, FLAG, CBR, EBR, HL, XY, SP, RSP, MI, MD, XP, RAM address, RAM data 2-2 Chapter 2. Functions Cycle counter Counter: Count conditions: One 24-bit counter Free-running count Trigger count Program memory address space Instruction fetch Address access information Coverage functions Monitored space: Monitored condition: Coverage information: Probe cable I/O * Break (EXT.BRK) input * Synchronous (SYNC.OUT) output * Trace (PROBE0 to PROBE3) inputs LEDs Voltage switching (User cable 1) POWER, RUN, ERROR, VCHECK, HALT, CROSC * Choice of internal or external power with VDD+VDDI.SEL1 switch * Choice of 3 or 5 V for internal power supply voltage with VDDI.SEL2 switch * External power supply voltage range: 0.9 to 5.0 V * Choice of internal or external low-speed clock with XT.SEL switch * Choice of internal or external high-speed clock with OSC.SEL switch Clock switching User interface cables Power supplies Flat cables with 50 and 40 pins (pitch = 2.54 mm) Input voltage: 100 to 240 V AC, 50/60 Hz and 5 V DC (2A) Power consumption: 24 W Operating conditions External dimensions and weight Temperature: Humidity: Dimensions: Weight: 5 to 50C 30 to 80% 248 (W)5186 (D)575 (H) mm 1.8 kg 2-3 Chapter 2. Functions 2. Functions 2.1 Configuring for Target Device The emulator is used to develop user application programs for all devices in the Oki MSM63180 family of 4-bit microcontrollers even though the individual devices have different ROM sizes and onboard peripherals. A dedicated emulator setup utility running on the development host configures the emulator to cover these differences by downloading the contents of the device information file (.TCD file) for the target microcontroller to an EEPROM inside the emulator. These settings take effect the next time that the power is applied or the reset switch is pressed. * Specify the highest code memory address in the target microcontroller's ROM and thus the number of breakpoint bits, trace enable bits, instruction executed (IE) bits, and sync out bits * Enable and disable RAM and SFR addresses * Specify the sizes of the call and register stacks * Specify the external memory size Changing these settings requires setting the emulator's SETICE switch to its ON position. Always set this switch to its OFF position for debugging. Operation Device configuration Debugging SETICE switch ON OFF ON ON OFF n Reference n ___________________________________________________________________________________________________________ Refer to the setup utility's manual for the detailed operating procedure. ________________________________________________________________________________________________________________________________ 2-4 38400 19200 9600 4800 SETICE OFF Chapter 2. Functions 2.2 Evaluation Operation 2.2.1 Overview The emulation configuration is for high-level debugging using a dedicated debugger running on a development host; the evaluation configuration, for stand-alone execution of the user application program from EPROMs. The MODE switch switches between the two, taking effect the next time that the power is applied or the reset switch is pressed. MODE switch EMU EVA Configuration Emulation Evaluation 2.2.2 Operation The evaluation configuration produces real-time emulation of the user application program from EPROMs. The two EPROM sockets, labeled EPROM.HIGH and EPROM.LOW, accept the following types. * MSM27512 and compatibles * MSM27101 and compatibles The emulator cannot program EPROMs. Use a commercial EPROM writer to write the two object files generated by the dedicated assembler to separate EPROMs. 0000H 1FFFH MSM27512 Write xxx.HXH 0000H 1FFFH MSM27512 Write xxx.HXL 0FFFFH HIGH Figure 2-1 0FFFFH LOW Address Ranges for MSM27512 2-5 Chapter 2. Functions 0000H 1FFFH MSM27101 Write xxx.HXH 0000H 1FFFH MSM27101 Write xxx.HXL 01FFFFH HIGH 1FFFFH LOW Figure 2-2 Address Ranges for MSM27101 Figures 2-1 and 2-2 show the address ranges for a microcontroller with a ROM size of 8 KW for these two types. The extension .HXH indicates the upper 8-bit object file from the assembler; .HXL, lower 8-bit object file. In the stand-alone evaluation configuration, turning on the emulator or pressing the reset switch resets the evaluation chip and starts real-time emulation from address 0. The RUN LED then lights. If the program counter (PC) strays into the nonexistent code memory area (N area), emulation aborts, the RUN LED goes out. Evaluation supports the use of user cable reset (USER.RESET) input to reset the evaluation chip. 2-6 Chapter 2. Functions 2.3 Emulation Operation Emulation involves running a user application program, under the control of software on a development host, in real time at the same speed and with electrical characteristics approaching those of the volume production masked ROM version. These last two characteristics distinguish it from simulation, the replacement of hardware with software running on a development host. Two types of emulation are available: real-time and single-step. The former runs nonstop up until a break. The latter pauses after each instruction to permit such debugging operations as examining and modifying register contents. Control from the host is possible because the evaluation chip inside the emulator has no masked ROM. Instead there are data and address buses to RAM and other external devices plus related control circuits. These modifications permit the microcontroller to execute the user application program in real time while still allowing the emulator (as thus the control software) debugging access to the device's memory, registers, and flags. The microcontroller uses this additional hardware to read instructions; the emulator, to control user application program execution and access these internal device components. The pins that the evaluation chip shares with the volume production masked ROM version are connected to the user application system through the user cables. n Note 1 n _______________________________________________________________________________________________________________ The interface circuitry provides resistors that protect the evaluation chip, but at the price of slightly altering pin electrical characteristics. We therefore recommend that testing with the next stage, a one-time programmable (OTP) version, include a full review of such characteristics. _______________________________________________________________________________________________________________________________ 2.3.1 Single-Step Emulation Single-step emulation pauses after each instruction to permit such debugging operations as examining and modifying register contents. Chapter 2. Functions The LCD drivers, however, continue to receive a clock signal, so are fully functional. n Note 1 n ________________________________________________________________________________________________________________ Do not press the emulator's reset switch during single-step emulation. Doing so invalidates code memory contents. ________________________________________________________________________________________________________________________________ 2.3.2 Real-time Emulation Real-time emulation runs nonstop or until there is a break from the following list. * Address break * Address pass count break * RAM data match break * RAM address match break * Internal ROM table data match break * Internal ROM table address match break * External memory data match break * External memory address match break * Breakpoint break * Trace memory full break * Cycle counter overflow break * External break * HALT break * Call stack overflow break * Register stack overflow break * N area access break * User break n Note 1 n ________________________________________________________________________________________________________________ Evaluation, in contrast, only offers N area access breaks. ________________________________________________________________________________________________________________________________ These break conditions generate a break request. Acceptance terminates the real-time emulation. 2-8 Chapter 2. Functions n Note 2 n _______________________________________________________________________________________________________________ The second group uses parameters that the user must set in advance. _______________________________________________________________________________________________________________________________ Figure 2-3 shows the interaction between these break conditions and the break condition register. Address break Address pass count break RAM data match break RAM address match break Internal ROM table data match break Internal ROM table address match break External memory data match break External memory address match break N-area access break User break Breakpoint break Trace memory full break Cycle counter overflow break External break HALT break Call stack overflow break Register stack overflow break BP TF CC XP PD PC RG Break request Break condition register Figure 2-3 From Break Condition to Break Request 2-9 Chapter 2. Functions 2.3.2.1 Breaks with Parameters (1) Address break Execution breaks after the instruction at the specified break address has executed. 100H 101H 102H 103H 303H 304H Break address Break address Break address (2) Address pass count break Execution breaks after the instruction at the specified address has executed the specified number of times. Break address 100H 101H 102H 103H 104H 105H 106H MOV A,#0FH MOV H,#0H MOV L,#0H MOV [HL] ,A NOP INCB HL BNG 103H Specifying a break address of 103H and a count of 5 produces a break after the fifth execution of the MOV [HL],A instruction at address 103H. Loop (3) RAM data match break Execution breaks one instruction after instructions have written the specified data the specified number of times to either any data memory address or the specified data memory address. 2-10 Chapter 2. Functions RAM write instruction 1FFH 200H 201H 202H 203H 204H 205H MOV MOV MOV MOV MOV INCB NOP CBR,#3H A,#3H H,#0FH L,#0FH [HL],A HL Specifying an address of any, a comparison value of 3, and a count of 1 produces a break one instruction after the once execution of the MOV [HL],A instruction at address 203H, that is, after the INCB HL instruction at address 204H. The break timing is not immediately after the instruction satisfying the break condition, but an additional instruction later. There is a bit mask parameter for extending data checking to multiple (or even all) comparison values. Specifying a code memory address produces a break only if the instruction at that address writes to a data memory address. n Note 1 n _______________________________________________________________________________________________________________ RAM data match breaks are available over the entire data memory address space--even SFR addresses with reserved bits (bits that ignore writes and always return "1") and addresses with read-only bits. _______________________________________________________________________________________________________________________________ n Note 2 n _______________________________________________________________________________________________________________ RAM data match breaks check only writes by instructions. RAM modifications by timers and other circuits are ignored. _______________________________________________________________________________________________________________________________ n Note 3 n _______________________________________________________________________________________________________________ A RAM data match break request remains in effect until the next write instruction. To resume emulation under the same break conditions, write somewhere in RAM using data that does not produce another break. _______________________________________________________________________________________________________________________________ (4) RAM address match break Execution breaks one instruction after instructions have written the specified number of times to the specified data memory address. 2-11 Chapter 2. Functions RAM write instruction RAM read instruction 300H 301H 302H 303H 304H 305H 306H MOV MOV MOV MOV NOP MOV NOP CBR,#3H H,#0H L,#0H [HL],A [HL],A Specifying an address of 300H and a count of 2 produces a break one instruction after the MOV [HL],A instructions at addresses 303H and 305H, that is, after the NOP instruction at address 306H. The break timing is not immediately after the instruction satisfying the break condition, but an additional instruction later. There is a bit mask parameter for extending address checking to multiple data memory addresses. n Note 4 n ________________________________________________________________________________________________________________ RAM address match breaks are available over the entire data memory address space--even SFR addresses. ________________________________________________________________________________________________________________________________ (5) Internal ROM table data match break Execution breaks when a ROM table reference instruction (MOVHB or MOVLB) reads either any data or the specified data from the specified code memory address. There is a bit mask parameter for extending data checking to multiple (or even all) comparison values. This type of break provides no count parameter. 100H 101H 102H 300H 301H 302H NOP MOVLB [HL], 300H NOP 33H 50H 38H LOW 28H 60H 24H HIGH ROM table Specifying a ROM table address of 300H and a comparison value of 33H produces a break one instruction after the MOVLB [HL],300H instruction at address 101H, that is, after the NOP instruction at address 102H. The break timing is not immediately after the instruction satisfying the break condition, but an additional instruction later. Specifying a code memory address produces a break only if the instruction at that address is a ROM table reference instruction. 2-12 Chapter 2. Functions (6) Internal ROM table address match break Execution breaks when a ROM table reference instruction (MOVHB or MOVLB) reads from the specified code memory address. 400H 401H 403H 404H 800H 801H 802H NOP MOVHB [HL+], 800H NOP NOP 22H 53H 68H 28H 57H 33H Specifying a ROM table address of 800H produces a break one instruction after the MOVHB [HL+],800H instruction at address 401H, that is, after the NOP instruction at address 403H. ROM table The break timing is not immediately after the instruction satisfying the break condition, but an additional instruction later. There is a bit mask parameter for extending address checking to multiple ROM table addresses. This type of break provides no count parameter. (7) External memory data match break Execution breaks one instruction after instructions have accessed the specified data at either any external memory address or the specified external memory address. A parameter provides three choices for access: read, write, or both. This type of break provides no count parameter. 500H 501H 503H 505H 506H NOP MOVXB [HL+], 323H MOVXB [HL+], 324H NOP NOP If external memory address 324H contains 55H, specifying an external memory address of 324H, a comparison value of 55H, and an access parameter of read only produces a break one instruction after the MOVXB [HL+],324H instruction at address 503H, that is, after the NOP instruction at address 505H. The break timing is not immediately after the instruction satisfying the break condition, but an additional instruction later. Specifying a code memory address produces a break only if the instruction at that address is a read or write instruction accessing the external memory. 2-13 Chapter 2. Functions (8) External memory address match break Execution breaks one instruction after an instructions has accessed the specified external memory address. This type of break provides no count parameter. 600H 601H 603H 605H 606H NOP MOVXB [HL+], 800H MOVXB [HL+], 801H NOP NOP Specifying an external memory address of 801H produces a break one instruction after the MOVXB [HL+],801H instruction at address 603H, that is, after the NOP instruction at address 605H. n Note 5 n ________________________________________________________________________________________________________________ Address settings at the following addresses never produce address breaks or address pass count breaks--unless there is something seriously wrong with the user application program. (a) ROM table locations 100H 101H 102H NOP MOVLB [HL], 323H The address 323H never produces an address break. Table data Break address 323H 2-14 Chapter 2. Functions (b) The second word of a 2-word instruction Break address 100H 101H 102H 103H NOP NOP LJMP 4324H The address 103H never produces an address break. _______________________________________________________________________________________________________________________________ n Note 6 n _______________________________________________________________________________________________________________ Some break types support bit masks for extending data or address matches. (a) Data match: Specifying a data memory address of 200H, a comparison value of 4H, and a mask of 0111B produces a match whenever 4H, 0CH, is written to data address 200H. (b) Address match: Specifying a external memory address of 120H and a mask of 0FFF0H produces a match for all addresses from 120H to 12FH (among others). _______________________________________________________________________________________________________________________________ n Note 7 n _______________________________________________________________________________________________________________ Specifying a code memory address produces data matching for the instruction at that address. In the following example, only the first three specifications produce data matches. (1) (2) (3) (4) MOV [HL], A MOV [XY], A MOV [XY], #5 MOV [XY+], #5 Address for data match Address for data match Address for data match Address not for data match _______________________________________________________________________________________________________________________________ 2.3.2.2 Breaks on Specific Conditions These breaks are the result of specific conditions involving flag bits and counters. 2-15 Chapter 2. Functions (1) Breakpoint break For each code memory address, the emulator provides a breakpoint bit for enabling these breaks. Setting a breakpoint at a code memory address sets the corresponding breakpoint bit to "1." Code memory 0000H 0001H 0002H 0003H 0004H Address specified by program counter (PC). Breakpoint bit memory 0FFFDH 0FFFEH 0FFFFH Breakpoint break request If these breaks are enabled, execution of the instruction at that address produces a break request of this type. n Note 1 n ________________________________________________________________________________________________________________ There are no limits on the number of breakpoints or their locations in the code memory space. Breakpoint settings at the following addresses, however, never produce breaks. (a) ROM table locations Breakpoint bit memory Code memory 100H 101H NOP MOVLB [HL],323H 0 0 0 The breakpoint bit for address 323H is never accessed. Breakpoint break specification 323H Table data 1 0 2-16 Chapter 2. Functions (b) The second word of a 2-word instruction Breakpoint bit memory The breakpoint bit for address 101H is never accessed. 100H 101H MOVLB [HL], 300H 0 1 Breakpoint break specification Code memory _______________________________________________________________________________________________________________________________ (2) Trace memory full break If these breaks are enabled, overflow during real-time emulation of the trace pointer, a 13-bit counter giving the location of the next entry to be written within its 8192-entry trace table produces a break request of this type. The emulator has room for 8192 trace entries. Trace information 0 1 2 3 4 8190 8191 Trace memory Trace signal Trace pointer (13-bit counter) (Overflow signal) Trace memory full break request If trace memory full breaks are enabled, overflow during real-time emulation of the trace pointer, a 13bit counter, produces a break request of this type. n Note 2 n _______________________________________________________________________________________________________________ Resuming real-time emulation after this break automatically cancels this request. The next 2-17 Chapter 2. Functions break of this type is not until the next overflow. ________________________________________________________________________________________________________________________________ (3) Cycle counter overflow break If these breaks are enabled, overflow during real-time emulation of the cycle counter, a 24-bit counter summing the machine cycles for instructions executed produces a break request of this type. Cycle count signal Cycle counter (24-bit counter) Cycle counter overflow break request n Note 3 n ________________________________________________________________________________________________________________ Resuming real-time emulation after this break automatically cancels this request. The next break of this type is not until the next overflow. ________________________________________________________________________________________________________________________________ n Note 4 n ________________________________________________________________________________________________________________ The cycle counter value after the break varies between one and the execution time of the instruction producing the overflow. It is always 1 for a single-cycle instruction, but could be 1, 2, or 3 for a 3-cycle one. ________________________________________________________________________________________________________________________________ (4) External break If these breaks are enabled, a rising edge in the probe cable break (EXT.BRK) input during real-time emulation produces a break request of this type. The signal uses VDDI, the port interface power supply voltage, for its "H" level. Voltage conversion circuit 51K Rising edge detection circuit External break request EXT.BRK (Probe cable) n Note 5 n ________________________________________________________________________________________________________________ The external break request and acceptance coincide with the beginning and end of an instruction S2 cycle. 2-18 Chapter 2. Functions M1 S1 System clock M1S1 EXT.BRK External break request External break occurs _______________________________________________________________________________________________________________________________ M1 S2 S1 S2 S1 M2 S2 S1 M1 S2 M1 S1 (5) Power down (HALT) break If these breaks are enabled, a HALT instruction produces a break request of this type. n Note 6 n _______________________________________________________________________________________________________________ The HALT instruction produces a temporary transition to halt mode followed by an immediate return. Restarting real-time emulation without specifying a starting address causes execution to resume from the instruction after the HALT instruction. _______________________________________________________________________________________________________________________________ (6) Call stack overflow break If these breaks are enabled, stack over- or underflow in the call stack pointer (SP) as the result of pushing onto or popping from that stack during real-time emulation produces a break request of this type. n Note 7 n _______________________________________________________________________________________________________________ When a call stack push/pop is performed, if the emulator detects a stack pointer overflow or underflow, then it will output a call stack overflow break request. _______________________________________________________________________________________________________________________________ n Reference n ___________________________________________________________________________________________________________ The stack size appears in the user's manual for the target microcontroller. _______________________________________________________________________________________________________________________________ (7) Register stack overflow break If these breaks are enabled, stack over- or underflow in the register stack pointer (RSP) as the result of pushing onto or popping from that stack during real-time emulation produces a break request of this type. n Note 8 n _______________________________________________________________________________________________________________ 2-19 Chapter 2. Functions When a register stack push/pop is performed, if the emulator detects a stack pointer overflow or underflow, then it will output a register stack overflow break request. ________________________________________________________________________________________________________________________________ n Reference n ___________________________________________________________________________________________________________ The stack size appears in the user's manual for the target microcontroller. ________________________________________________________________________________________________________________________________ 2.3.2.3 Forced Breaks Forced breaks are breaks that do not depend on parameters or specific conditions. They force immediate termination of real-time emulation. (1) N area access break An attempt to read an instruction or ROM table data from a code memory address not physically present produces a break request of this type. 0FFFFH N area 6000H 5FDFH Test data area Code memory area 8K words 0000H Code memory n Note 1 n ________________________________________________________________________________________________________________ The former is especially problematical because the break occurs after the microcontroller attempts to execute the indeterminate data from the invalid address. Real-time emulation immediately terminates. ________________________________________________________________________________________________________________________________ n Note 2 n ________________________________________________________________________________________________________________ The emulator considers the microcontroller's test data area part of the N area. ________________________________________________________________________________________________________________________________ n Note 3 n ________________________________________________________________________________________________________________ The EXPAND ON command expands the available code memory area to the full address space (64 KW), eliminating the N area and thus these breaks. 2-20 Chapter 2. Functions _______________________________________________________________________________________________________________________________ (2) User break User break input from the keyboard produces a break request of this type. Real-time emulation immediately terminates. n Note 4 n _______________________________________________________________________________________________________________ This break also terminates halt mode if it is in effect. Restarting real-time emulation without specifying a starting address causes execution to resume from the instruction after the HALT instruction. _______________________________________________________________________________________________________________________________ 2.3.3 Other Options The following options are available with both real-time and single-step emulation. * Suspend the time-base counter (TBC). This option stops TBC, disabling all peripheral devices using the latter's clock output. * Suspend the watchdog timer (WDT). This option disables the WDT clock input, thus disabling watchdog timer interrupts. 2-21 Chapter 2. Functions 2.4 Code Memory Operations Code memory is a 16-bit address space that corresponds to the masked ROM of the volume production device. The emulator starts with a code memory area the size of the ROM in the microcontroller specified with the dedicated emulator setup utility. 2.4.1 Data Operations between Code Memory and Disk Files These operations include copying data in either direction between code memory and disk files. They always involve simultaneous use of a pair of object files: one for the upper 8 bits and another for the lower 8 bits. Disk Files Load Code Memory Save Verify xxx.HXH (higher 8 bits) xxx.HXL (lower 8 bits) 16 bits Figure 2-4 Data Operations between Code Memory and Disk Files 2.4.2 Data Operations between Code Memory and EPROMs These operations limit copying data to one direction: from EPROMs in the two sockets on top of the emulator to code memory. The socket labeled EPROM.HIGH is for the upper 8-bit object file (.HXH) from the assembler; EPROM.LOW, the lower 8-bit object file (.HXL). The emulator cannot program EPROMs. Use a commercial EPROM writer to write the two object files generated by the dedicated assembler to separate EPROMs. 2-22 Chapter 2. Functions Load Code Memory Verify HIGH side (higher 8 bits) 16 bits LOW side (lower 8 bits) Figure 2-5 Data Operations between Code Memory and EPROMs n Note 1 n _______________________________________________________________________________________________________________ Stand-alone, evaluation operation does not use code memory. The user application program executes directly from the EPROMs in the EPROM sockets. _______________________________________________________________________________________________________________________________ 2.4.3 Displaying/Changing/Moving Code Memory Displaying/changing code memory can be performed at the instruction code level or instruction mnemonic level. Moving code memory can be performed at the instruction code level. 2.4.4 Code Memory Backup A large capacitor inside the emulator maintains code memory contents for up to 96 hours (four days). n Note 1 n _______________________________________________________________________________________________________________ The backup interval depends on how long the capacitor has been charged--that is, how long the emulator power has been on--and varies with ambient conditions. _______________________________________________________________________________________________________________________________ 2-23 Chapter 2. Functions 2.4.5 Expanding Code Memory The EXPAND command temporarily expands the code memory to the full address space (64 KW) for debugging a user application program that is too large for the user application program memory. Figure 2-6 shows such expansion for a microcontroller with 8 KW of ROM. 0FFFFH Expanded mode Normal mode 1FDFH Expansion on 8K words 64K words Expansion off 0000H 0000H Figure 2-6 Code Memory Expansion n Note 1 n ________________________________________________________________________________________________________________ Be sure to disable code memory expansion before starting final verification of user application program operation. ________________________________________________________________________________________________________________________________ n Note 2 n ________________________________________________________________________________________________________________ Changing the code memory expansion setting resets the evaluation chip. ________________________________________________________________________________________________________________________________ 2-24 Chapter 2. Functions 2.5 External Memory Operations MSM63180 microcontrollers offer an external memory interface as a secondary function for their I/O ports. The emulator can display and modify this external memory. Load External memory Save Disk files xxx.H00 xxx.HFF 8 bits Figure 2-7 Data Operations between External Memory and Disk Files The hexadecimal digits in the file extensions .H00 to .HFF correspond to the segment specified in the source file with the XDATA directive. n Note 1 n _______________________________________________________________________________________________________________ The assembler supports up to 256 banks in the external memory address space. MSM63180 microcontrollers, however, do not select banks, relying instead on the I/O ports or the user application system to do so. A command accessing external memory simply uses the bank last specified by the user application program. _______________________________________________________________________________________________________________________________ 2-25 Chapter 2. Functions 2.6 Real-time Tracing Real-time tracing stores the current instruction address, the contents of ACC and other registers, flag states, etc. for post mortem analysis of real-time emulation. The emulator uses the 13-bit trace pointer to keep track of the location of the next entry to be written within its 8192-entry trace table. When the trace pointer reaches that number, it recycles, overwriting the oldest entry first. Trace data Trace enable bits 0 1 2 3 4 Program counter output 8190 8191 Trace memory Trace signal Trace control circuit Trace pointer (13-bit counter) (Overflow signal) Trace memory full break request Figure 2-8 Real-Time Tracing For each code memory address, the emulator provides a trace enable bit for use in limiting tracing to specific addresses. 2-26 Chapter 2. Functions Code memory 0000H 0001H 0002H 0003H 0004H Address specified by program counter (PC) Trace enable bits 0FFFDH 0FFFEH 0FFFFH To trace control circuit Figure 2-9 Trace Enable Bits 2.6.1 Trace Entries Trace entries track the following data items. Label ADRS A RADR RD CGZ MI MD CB EB HL XY SP RS XP Description Execution address Accumulator RAM address RAM data Flag register Master interrupt enable flag Melody request flag Current bank register Extra bank register HL register XY register Stack pointer Register stack pointer External probe data 16 4 12 4 3 1 1 4 4 8 8 5 4 4 Bits In addition to the above, the emulator also traces interrupt requests for post mortem analysis of interrupts during real-time emulation. 2-27 Chapter 2. Functions 2.6.2 Real-time Trace Control Real-time tracing offers three operating modes and an option for limiting tracing to code memory addresses with "1" in their trace enable bits. Trace disabled Free-running trace Trigger trace With t race enable bits Without trace enable bits With trace enable bits Without trace enable bits (1) Trace disabled No instructions are traced. (2) Free-running trace Instructions are traced for all code memory addresses--unless limited with the trace enable bit option. a. With trace enable bits Tracing depends on the trace enable bit contents. Only addresses with a trace enable bit of 1 are traced. Code memory Trace enable bits 100H 101H 102H 103H 104H 105H 106H 107H MOV A,#3H MOV H,#8H MOV L,#2H MOV [HL],A MOV A,#4H INCB HL MOV [HL],A NOP 0 1 1 1 1 1 0 0 Trace enable bits specify tracing for addresses 101H to 105H. b. Without trace enable bits Tracing ignores the contents of the trace enable bits. (3) Trigger trace All instructions between start and stop triggers based on code memory addresses are traced--unless limited with the trace enable bit option. There are three possible trigger combinations: 2-28 Chapter 2. Functions a. Specifying both a start and stop address Tracing starts when real-time emulation visits the former and stops when the program counter (PC) hits the latter. b. Specifying a start address only Tracing starts when real-time emulation visits the former and continues until there is a break. c. Specifying a stop address only Tracing starts simultaneously with real-time emulation and stops when the program counter (PC) hits the latter. This example shows such tracing together with the trace enable bit option. a. With trace enable bits Tracing depends on the trace enable bit contents. Only addresses with a trace enable bit of 1 are traced. Code memory Trace enable bits Trace start address Trace stop address 100H 101H 102H 103H 104H 105H 106H 107H 108H 109H MOV A, #3H MOV H, #8H MOV L, #2H MOV [HL], A MOV A, #4H INCB HL MOV [HL], A NOP NOP NOP 0 1 1 1 1 1 0 0 1 1 Tracing starts at code memory address 100H, but trace enable bits limit it to addresses 102H through 105H. b. Without trace enable bits Tracing ignores the contents of the trace enable bits. n Note 1 n _______________________________________________________________________________________________________________ Real-time tracing is enabled during real-time emulation and disabled during single-step emulation. _______________________________________________________________________________________________________________________________ n Note 2 n _______________________________________________________________________________________________________________ The trigger fires just before execution of the instruction at the corresponding address, so the instruction at the start address is traced, but not the one at the stop address. 2-29 Chapter 2. Functions Trace start address Trace stop address MOV A,#3H MOV H,#0FH MOV L,#0 MOV CBR,#4H MOV [HL],A INCB HL Tracing covers from the MOV A,#3H instruction at the start address through to the MOV [HL],A instruction preceding the stop address. ________________________________________________________________________________________________________________________________ n Note 3 n ________________________________________________________________________________________________________________ Only start and stop address specifications corresponding to the first word of an instruction produce results. One specifying the second word of a two-word instruction or an entry in the ROM table yield a trigger that never fires. ________________________________________________________________________________________________________________________________ n Note 4 n ________________________________________________________________________________________________________________ Only the trace enable bits corresponding to the first word of an instruction produce results. One specifying the second word of a two-word instruction or an entry in the ROM table is ignored. Disabling the option produces tracing regardless of the enable bit contents. ________________________________________________________________________________________________________________________________ n Note 5 n ________________________________________________________________________________________________________________ The RAM address and RAM data fields contain indeterminate data until an instruction writes to a data memory address. They also repeat between such instructions. ________________________________________________________________________________________________________________________________ n Note 6 n ________________________________________________________________________________________________________________ Flag (C, Z, G, MIEF) changes appear in the entry for the instruction preceding the one where the flag actually changes. ________________________________________________________________________________________________________________________________ n Note 7 n ________________________________________________________________________________________________________________ The external memory access and ROM table reference instructions (MOVXB, MOVHB, and MOVLB) consume two trace entries each. ________________________________________________________________________________________________________________________________ 2.6.3 Displaying/Searching Trace Entries The emulator can display the real-time trace entries as a group or individually. 2-30 Chapter 2. Functions 2.7 Profiling The emulator supports two types of profiling: * Checking code memory addresses accessed with instruction executed (IE) bits * Measuring execution times with the cycle counter 2.7.1 Instruction Executed (IE) Bits For each code memory address, the emulator provides an instruction executed (IE) bit for use in tracking instruction access during execution. Each access to a code memory address during real-time emulation sets the corresponding IE bit to "1." Examining these bits then reveals which instructions were executed during the emulation. Instruction executed memory Code memory 0000H 0001H 0002H 0003H 0004H Execution sets the IE bit at the address specified by the program counter (PC) to "1." 0FFFDH 0FFFEH 0FFFFH Figure 2-10 IE Bits n Note 1 n _______________________________________________________________________________________________________________ Single-step emulation does not set IE bits. _______________________________________________________________________________________________________________________________ 2-31 Chapter 2. Functions 2.7.2 Cycle Counter The 24-bit cycle counter tracks the machine cycles of each instruction executed as a yardstick to user application program execution times. Cycle count signal Cycle counter overflow break request Machine cycle signal Program counter output Cycle counter control circuit Cycle counter Figure 2-11 Cycle Counter This counter offers three modes of operation. * Count disabled * Free-running count * Trigger count (1) Count disabled No instructions are counted. (2) Free-running count Instructions are counted for all code memory addresses. (3) Trigger count All instructions between start and stop triggers based on code memory addresses are counted. There are three possible trigger combinations: a. Specifying both a start and stop address Counting starts when real-time emulation visits the former and stops when the program counter (PC) hits the latter. b. Specifying a start address only Counting starts when real-time emulation visits the former and continues until there is a break. c. Specifying a stop address only Counting starts simultaneously with real-time emulation and stops when the program counter (PC) hits the latter. n Note 1 n ________________________________________________________________________________________________________________ Counting is enabled during real-time emulation and disabled during single-step emulation. ________________________________________________________________________________________________________________________________ 2-32 Chapter 2. Functions n Note 2 n _______________________________________________________________________________________________________________ The trigger fires just before execution of the instruction at the corresponding address, so the instruction at the start address is counted, but not the one at the stop address. Count start address MOV A, #3H MOV H, #0FH MOV L, #0H Counting covers from the MOV A,#3H instruction at the start address through to the INCB HL instruction preceding the stop address. Count stop address INCB HL MOV [HL], A _______________________________________________________________________________________________________________________________ n Note 3 n _______________________________________________________________________________________________________________ Only start and stop address specifications corresponding to the first word of an instruction produce results. One specifying the second word of a two-word instruction or an entry in the ROM table yield a trigger that never fires. _______________________________________________________________________________________________________________________________ 2-33 Chapter 2. Functions 2.8 Probe Cable The emulator's probe cable carries the following six signals. * Break (EXT.BRK) input * Sync out (SYNC.OUT) output * Trace (PROBE0 to PROBE3) inputs 2.8.1 Break Signal Input If external breaks are enabled, a rising edge in this signal produces a break request. EXT.BRK (Probe cable) 51K + 1/2 VDDI Rising edge detection circuit External break request Figure 2-12 Break Signal Input A built-in voltage conversion circuit converts the break (EXT.BRK) input level of VDDI, the port interface power supply voltage (0.9 to 5 V), to the internal "H" level. The break request coincides with the beginning of an instruction S2 cycle. M1 S1 System clock M1S00 EXT.BRK External break request External break occurs Figure 2-13 External Break Input Timing S2 S1 M1 S2 S1 M2 S2 S1 M1 S2 M1 S1 2-34 Chapter 2. Functions 2.8.2 Sync Out Signal For each code memory address, the emulator provides a sync out bit that controls this output. If a bit is "1," execution of the instruction at the corresponding address pulls the probe cable sync out (SYNC.OUT) output to "L" level for the first half of an instruction S1 cycle. Code memory 0000H 0001H 0002H 0003H 0004H Addresses specified by the program counter (PC). Sync out bits 0FFFDH 0FFFEH 0FFFFH Latch VDDI Level conversion SYNC.OUT (Probe cable) Figure 2-14 Sync Out Bits A built-in voltage conversion circuit converts the sync out (SYNC.OUT) signal "H" level to VDDI, the port interface power supply voltage (0.9 to 5 V), for output. n Note 1 n _______________________________________________________________________________________________________________ Only the sync out bit specifications corresponding to the first word of an instruction produce results. One specifying the second word of a two-word instruction or an entry in the ROM table is ignored. _______________________________________________________________________________________________________________________________ 2-35 Chapter 2. Functions 2.8.3 Trace Inputs These inputs are for tracing external signals during real-time emulation. PROBE0 51K PROBE1 51K PROBE2 51K PROBE3 (Probe cable) 51K + + + + 1/2 VDDI To trace circuit Figure 2-15 Trace Inputs Built-in voltage conversion circuits convert the trace (PROBE0 to PROBE3) inputs to the internal "H" level from VDDI, the port interface power supply voltage (0.9 to 5 V). Input is latched at the beginning of an instruction S1 cycle. M1 S1 System clock Trace write signal Data capture signal Trace probe input Trace memory probe information S2 S1 M1 S2 S1 M2 S2 S1 M1 S2 M1 S1 Figure 2-16 Trace Input Timing 2-36 Chapter 2. Functions 2.9 Clock Switching The emulator offers the choice of internal or external clock signals to the XT (low-speed) and OSC (high-speed) pins on the evaluation chip. It bases the internal versions on the clock signal from the crystal board's MSM63P180. The external ones come from the user cable USER.XT and USER.OSC pins. Low-speed (XT) High-speed (OSC) Internal External (user cable USER.XT pin) Internal External (user cable USER.OSC pin) The microcontroller's time-base counter always uses the XT input to generate clock signals for the onboard peripherals. Its CPU, however, offers a choice of clock speeds: XT or OSC. Using the faster (OSC) clock signal, however, introduces the risk of losing synchronization with the lower (XT) during single-step emulation or in the course of repeated breaks during real-time emulation. Results from timers and other onboard peripherals can therefore differ from those obtained during continuous execution with real-time emulation. Crystal board MSM63P180 OSC0 Internal high-speed clock OSC.SEL IN EXT High-speed OSC clock 2MHz OSC1 XT0 XT1 to OSC pin on evaluation chip Internal low-speed clock XT.SEL IN EXT Low-speed XT clock 32.768kHz Internal 5V power supply 100K HC541 high-speed to XT pin on evaluation chip External clock HC541 USER.OSC (User cable) 100K OSC.OUT (User cable) USER.XT (User cable) HC541 low-speed External clock HC541 XT.OUT (User cable) Figure 2-17 Clock Circuits 2-37 Chapter 2. Functions The XT.SEL and OSC.SEL switches control clock signal selection. High-speed (OSC) clock OSC.SEL IN EXT Low-speed (XT) clock XT.SEL IN EXT Selected clock Internal high-speed clock External high-speed clock Selected clock Internal low-speed clock External low-speed clock The internal clock signals are generated by the MSM63P180, a one-time programmable (OTP) version. This device allows the user to supply clock signals with frequencies similar to those from the actual oscillator--especially for the RC oscillation high-speed clock. Although MSM63180 microcontrollers normally switch between ceralock and RC oscillation with Frequency Control Register (FCON) bit 2 (OSCSEL), the emulator uses a jumper on the crystal board. External high-speed (USER.OSC) and low-speed (USER.XT) clock signals must have the following waveform. e a c b Duty ratio: Voltage: Frequency: a:b = 1:1 e = 5.0 V USER.XT c = 10 kHz to 150 kHz USER.OSC c= 500 kHz to 2 MHz The emulator ships with the XT.SEL and OSC.SEL switches in their IN positions. The crystal board has the following circuit configuration. MSM63P180 XT0 Internal low-speed clock 32.768kHz ROS XT1 OSC0 OSC1 Internal high-speed clock 5V JP Test pin Figure 2-18 Crystal Board Circuits 2-38 Chapter 2. Functions Connecting the jumper (JP) to 5 V switches to ceralock oscillation. The emulator ships with the jumper open, selecting RC oscillation with the resistor ROS. n Note 1 n _______________________________________________________________________________________________________________ The emulator ships with a 32.768-kHz crystal oscillator across the MSM63P180 XT pins. If you replace this, be sure to check the output at the monitor pin XT.OUT. Depending on the crystal manufacturer and type, the circuit might not oscillate properly. _______________________________________________________________________________________________________________________________ n Note 2 n _______________________________________________________________________________________________________________ The emulator ships with the jumper (JP) open, selecting RC oscillation with the crystal board's built-in resistor ROS across the MSM63P180 OSC pins. If you change this resistor or switch to ceralock oscillation, be sure to check the output at the monitor pin OSC.OUT. Depending on the resistor type or ceralock oscillator used, the circuit might not oscillate properly. _______________________________________________________________________________________________________________________________ n Note 3 n _______________________________________________________________________________________________________________ MSM63180 microcontrollers start the high-speed clock oscillation by setting Frequency Control Register (FCON) bit 1 (ENOSC) to "1." Although ceralock oscillation then normally requires on the order of 10 ms to start, here the clock signal is immediately available because the emulator starts the oscillation soon after the power is applied. _______________________________________________________________________________________________________________________________ 2-39 Chapter 2. Functions 2.10 Reset Input Switching The reset signal to the evaluation chip in the emulator normally comes from the emulator's main control CPU. There is, however, a setting for adding user cable reset (USER.RESET) input. Reset signal from main CPU USER.RESET (User cable) 51K Reset input to evaluation chip + 1/2 VDD Reset switch signal Figure 2-19 Reset Input A built-in voltage conversion circuit converts the user cable reset (USER.RESET) input to the internal "H" level from VDD, the positive power supply voltage (0.9 to 5 V). n Note 1 n ________________________________________________________________________________________________________________ User cable reset (USER.RESET) input is only relevant during evaluation and real-time emulation. It is always prohibited during single-step emulation. ________________________________________________________________________________________________________________________________ 2-40 Chapter 2. Functions 2.11 Internal Signal Monitoring The user cables provide pins for monitoring the following internal signals. * Halt mode (HALT.OUT) signal * Low-speed clock (XT.OUT) signal * High-speed clock (OSC.OUT) signal (1) Halt mode (HALT.OUT) signal "H" level output indicates that the evaluation chip is in halt mode. (2) Low-speed clock (XT.OUT) signal This pin monitors the low-speed (XT) clock signal to the evaluation chip. (3) High-speed clock (OSC.OUT) signal This pin monitors the high-speed (OSC) clock signal to the evaluation chip. n Note 1 n _______________________________________________________________________________________________________________ These three signals use the emulator's internal operating voltage (5 V) for their "H" level. _______________________________________________________________________________________________________________________________ 2-41 Chapter 2. Functions 2.12 Port Interface Power Supply Switching The emulator offers the following choices for VDDI, the port interface power supply voltage, and VDD, the positive power supply voltage. Port interface power supply (VDDI) Positive power supply (VDD) Internal 5-V power supply Internal 3-V power supply External power supply from user cable VDDI pin Internal 5-V power supply External power supply from user cable VDD pin User cable reset (USER.RESET) input uses VDD as its "H" level; ports and the probe signals, VDDI. VDDI (User cable) Protection circuit VDD,VDDI.SEL1 EXT IN Voltage monitor circuit Port interface power supply VDD (User cable) Protection circuit EXT IN Internal 5V power supply Internal 3V power supply 5V 3V VDDI.SEL2 Voltage monitor circuit Positive power supply Port/positive power supply switch 1 (VDD+VDDI.SEL1) simultaneously switches VDDI and VDD between internal and external sources. Port interface power supply switch 2 (VDDI.SEL2) switches the internal VDDI source between 5 and 3 V. The protection circuits on the user cable VDDI and VDD pins protect the emulator from damage due to voltages applied to those pins before power is applied to the emulator. The voltage monitor circuits constantly monitor the VDDI and VDD levels, lighting the VCHECK LED if either falls below approximately 0.9 V. Caution 2-42 The VDDI or VDD input voltage must be between 0.9 and 5 V. Using a voltage outside this range risks damaging the evaluation chip. Chapter 2. Functions 2.13 LCD Bias Switching The built-in LCD driver offers a choice of bias (1/4 or 1/5) and the option of using an external expansion LCD driver. (1) LCD bias power supply The external (EXT) position of jumper 1 (J1) disables the evaluation chip's built-in LCD bias voltage generator. Use with an expansion LCD driver requires an external bias power supply. Evaluation chip MSM63E180 J1 EXT C IN 0.1F C1 C2 Figure 2-20 Jumper 1 Circuit LCD bias power supply External Internal J1 setting C shorted with EXT C shorted with IN The emulator ships with J1 in its IN position. n Note 1 n _______________________________________________________________________________________________________________ This setting also affects the LCD drive signal (COMxx and SEGxx) output levels. _______________________________________________________________________________________________________________________________ (2) Bias switch Jumper 2 (J2) specifies the LCD driver bias: 1/4 or 1/5. Evaluation chip MSM63E180 J2 1/5 C 1/4 0.1F VDD2 VDD3 0.1F Figure 2-21 Jumper 2 Circuit 2-43 Chapter 2. Functions Bias 1/4 J2 setting C shorted with 1/4 1/5 C shorted with 1/5 The emulator ships with J2 in its 1/5 position. 2-44 Chapter 2. Functions 2.14 DIP Switches 2.14.1 BAUD Switches The BAUD switches at the rear of the emulator offer a choice of eight baud rates from 4800 to 115200 bps. BAUD ON BAUD RESET ON Figure 2-22 BAUD Switch The baud rate settings are as follow. BAUD switch baud rate 4,800bps 9,600bps 19,200bps 38,400bps 51,200bps 57,600bps 76,800bps 115,200bps 38400 19200 9600 OFF OFF OFF ON ON ON ON OFF OFF OFF ON OFF ON ON OFF ON OFF ON OFF OFF ON OFF ON ON All other serial interface parameters are fixed: 8 bits, no parity, 1 stop bit, XON/XOFF flow control. n Note 1 n _______________________________________________________________________________________________________________ The IBM PC/AT and compatibles do not support the 51,200bps and 76,800bps speeds. If turning on or resetting the EASE63180 fails to produce an initialization message on the dedicated debugger's screen, lower both the EASE63180 baud rate setting and the dedicated debugger's speed parameter. _______________________________________________________________________________________________________________________________ 38400 19200 9600 4800 SETICE OFF OFF 4800 ON OFF OFF OFF OFF ON ON ON 2-45 Chapter 2. Functions 2.14.2 SETICE Switch Set the SETICE switch to its ON position before running the dedicated emulator setup utility on the development host to configure the emulator for the target microcontroller. SETICE switch ON OFF Operating mode Device configuration mode Debugging (evaluation or emulation) 2-46 Chapter 2. Functions 2.15 LED Indicator The emulator has six LEDs. Label POWER RUN ERROR VCHECK HALT CROSC Color Red Green Red Red Orange Green Meaning Power supply Execution Error Voltage check Halt mode RC oscillation (1) POWER This LED lights when power is being supplied to the emulator. (2) RUN This LED lights during real-time emulation. It goes out if the program counter (PC) strays into the nonexistent code memory area (N area), producing an N area access break. (3) ERROR This LED lights when an error within the emulator prevents correct operation. (4) VCHECK This LED lights if VDDI, the port interface power supply voltage, or VDD, the positive power supply voltage, falls below 0.9 V. (5) HALT This LED lights when the evaluation chip is in halt mode. (6) CROSC This LED lights when Frequency Control Register (FCON) bit 2 (OSCSEL) is "1," specifying ceralock oscillation. Note that the user application program must set this bit. n Note 1 n _______________________________________________________________________________________________________________ If the ERROR LED lights, or if all LEDs other than HALT light, try the appropriate troubleshooting procedure from Appendix 7, "If Emulator Doesn't Start." _______________________________________________________________________________________________________________________________ 2-47 Chapter 2. Functions 2.16 Power Supplies The emulator runs off either AC or DC power. (1) AC power supply The emulator uses a built-in switching regulator. 100 to 240 V AC 47 to 63 Hz, single-phase AC power connector 100 to 240 V AC Caution (2) DC power supply NEVER USE A POWER SUPPLY VOLTAGE OUTSIDE THE SPECIFIED RANGE. DOING SO RISKS FIRE AND BREAKDOWN. The emulator operates on a nominal 5 V DC (4.75 to 5.25 V) from the DC power supply cable. Connecting this cable automatically isolates the built-in switching regulator. 5 V DC - + DC power jack 2-48 Chapter 2. Functions Caution NEVER REVERSE THE POLARITY OF THE DC POWER SUPPLY INPUT. DOING SO DAMAGES THE EMULATOR. 2-49 Chapter 3. Setting Up and Starting Up Chapter 3. Setting Up and Starting Up 1. Device Configuration Before using the emulator for debugging, use the dedicated emulator setup utility to configure it for the target microcontroller. This utility runs on the development host, transferring device information to the emulator over a serial cable. The BAUD switches at the rear of the emulator specify the transfer speed. The emulator stores this configuration data in a built-in EEPROM, so reconfiguration is only necessary when the target microcontroller changes. Before using the utility, set the SETICE switch at the rear of the emulator to its ON position, the one for updating this EEPROM. SETICE switch ON OFF Operating mode Device configuration Debugging (evaluation or emulation) The ICE setup utility runs on the host computer, transferring device information to the EASE63180 InCircuit Emulator through the RS-232C interface. The communication baud rate of the RS-232C interface is set by the dipswitches (BAUD) on the rear panel of the EASE63180 In-Circuit Emulator unit. BAUD switch baud rate 4,800bps 9,600bps 19,200bps 38,400bps 51,200bps 57,600bps 76,800bps 115,200bps 38400 19200 9600 4800 OFF OFF OFF ON ON ON ON OFF OFF OFF ON OFF ON ON OFF ON OFF ON OFF OFF ON OFF ON ON ON OFF OFF OFF OFF ON ON ON The emulator is now ready for the update. n Note 1 n ________________________________________________________________________________________________________________ After the update, always return the SETICE switch to its OFF position for debugging. ________________________________________________________________________________________________________________________________ 3-2 Chapter 3. Setting Up and Starting Up n Note 2 n _______________________________________________________________________________________________________________ Set the emulator switches to the settings in the following table. Switch label MODE VDD + VDDI.SEL1 VDDI.SEL2 OSC.SEL XT.SEL Setting EMU IN 5V IN IN _______________________________________________________________________________________________________________________________ n Note 3 n _______________________________________________________________________________________________________________ The IBM PC/AT and compatibles do not support the 51,200bps and 76,800bps speeds. If turning on or resetting the EASE63180 fails to produce an initialization message on the dedicated debugger's screen, lower both the EASE63180 baud rate setting and the dedicated debugger's speed parameter. _______________________________________________________________________________________________________________________________ 3-3 Chapter 3. Setting Up and Starting Up 2. Evaluation This configuration is for stand-alone execution of the user application program from EPROMs. 2.1 Switch and Jumper Settings This section describes the switch and jumper settings needed before starting the emulator. (1) MODE switch Set this switch to its EVA position to select evaluation. (2) DIP switches Set the SETICE switch to its OFF position. Leave the BAUD switches (4800BPS to 38400BPS) as is. (3) VDD+VDDI.SEL1 and VDDI.SEL2 switches Select the power supply configurations for VDDI, the port interface power supply voltage, and VDD, the positive power supply voltage. Power supply Port interface power supply (VDDI) Internal 5 V power supply Internal 3 V power supply External (from user cable VDDI pin) External (from user cable VDD pin) VDD (VDD) VDDI.SEL1 IN VDDI.SEL 2 5V 3V Positive power supply Internal 5 V power supply EXT Don't care (4) OSC.SEL switch Select the high-speed (OSC) clock source. Clock source Internal External (from user cable USER.OSC pin) OSC.SEL IN EXT (5) XT.SEL switch Select the low-speed (XT) clock source. 3-4 Chapter 3. Setting Up and Starting Up Clock source Internal External (from user cable USER.XT pin) XT.SEL IN EXT n Note 1 n _______________________________________________________________________________________________________________ The emulator ships with a 32.768-kHz crystal oscillator for its internal XT source on the crystal board. To change the frequency, replace this crystal. If you do, however, be sure to check the output at the monitor pin XT.OUT. _______________________________________________________________________________________________________________________________ (6) Crystal board jumper (JP) The emulator ships with these jumper pins open, selecting RC oscillation with the ROS resistor provided for the high-speed clock. To switch to ceralock oscillation, short-circuit the pins and install a ceralock oscillator and oscillation capacitors on the crystal board. Oscillation mode Ceralock oscillation RC oscillation Jumper pins Shorted Open To use ceralock oscillation, install a ceralock oscillator and oscillation capacitors on the crystal board. Ceralock Capacitors for ceralock oscillation Crystal for internal low-speed clock (32.768 kHz crystal mounted when shipped) JP Ceralock/RC jumper 3-5 Chapter 3. Setting Up and Starting Up To use RC oscillation, install an ROS resistor with the value given in the user's manual for the microcontroller. ROS resistor for RC oscillation Crystal for internal low-speed clock (32.768 kHz crystal mounted when shipped) JP n Note 2 n ________________________________________________________________________________________________________________ If you replace the crystal for the internal high-speed clock, or switch between ceralock oscillation and RC oscillation, be sure to check the output at the monitor pins XT.OUT and OSC.OUT. ________________________________________________________________________________________________________________________________ (7) LCD bias jumper Specify the LCD bias power supply with jumper 1 (J1). Using an expansion LCD driver requires an external power supply. LCD bias power supply External Internal J1 EXT C IN External power supply The emulator ships with J1 in its IN position. EXT C J1 setting C shorted with EXT C shorted with IN J1 Jumper IN Internal power supply 3-6 Chapter 3. Setting Up and Starting Up Jumper 2 (J2) specifies the LCD driver bias: 1/4 or 1/5. Bias 1/4 1/5 J2 1/5 C 1/4 1/5 bias The emulator ships with J2 in its 1/5 position. 1/5 C 1/4 J2 setting C shorted with 1/4 C shorted with 1/5 J2 Jumper 1/4 bias These jumpers are located on the topmost printed circuit board in the emulator. Remove the top cover to access them. EVA J1 Low EPROM socket High EPROM socket J2 (8) Backup circuit jumpers Jumpers J4 and J5 switch backup on and off. Backup Backup ON VDD = 0.9V to 2.7V Backup OFF VDD = 1.8V to 5.0V J4 and J5 settings J4 Short pins 4 and 5 J5 Short pins 6 and 7 J4 Short pins 1 and 2 J5 Short pins 9 and 10 3-7 Chapter 3. Setting Up and Starting Up Jumper 5 1 Jumper J4 J5 6 10 5 1 J4 J5 Backup OFF 6 10 Backup ON The emulator ships with backup off. These jumpers are located on the topmost printed circuit board in the emulator. Remove the top cover to access them. EVA J1 Low EPROM socket High EPROM socket J4 J5 J2 Caution If VDD exceeds 2.7 V, turn the backup circuit off. Otherwise, the circuit generates high voltages that could damage the emulator. 3-8 Chapter 3. Setting Up and Starting Up 2.2 Emulator Connections EASE63180 High EPROM PROBE USRCN1 User cable 1 User application system Low EPROM Emulator power supply (4.75 to 5.25 V) 50 pins USRCN1-1 50 pins USRCN1-2 + - DC power cable USRCN2 DC5V User cable 2 40 pins USRCN2-1 40 pins USRCN2-2 User application system VDD VSS ACIN Power cable User application system power supply + Grounded AC outlet (100 to 240 V AC) 0.9 to 5V Positive power supply + + - 0.9 to 5V VDD VSS Port interface power supply 0.9 to 5V VDDI VSS Figure 3-1 Connections for Evaluation n Note 1 n _______________________________________________________________________________________________________________ (1) (2) Install the two EPROMs containing the user application program in the EPROM.HIGH and EPROM.LOW sockets. The VDDI and VDD power supplies shown are not necessary when the user application program draws upon the emulator's internal power supplies. The third is always required because the user cables do not supply this power to the user application system. (3) Connecting the DC power supply cable automatically isolates the built-in switching regulator. _______________________________________________________________________________________________________________________________ 3-9 Chapter 3. Setting Up and Starting Up EASE63180 emulator VDD5 VDD4 VDD3 VDD2 VDD1 VDD,VDDI.SEL1 EXT VDDI VDD IN EXT IN 5V 3V Input port Output port RESET XT OSC VSS 5V power supply User cable User application system VDDI VDD + + VDD Port interface power supply (5V) VDD, VDDI.SEL2 Positive power supply (3V) Pn Pn .... (VDDI interface) (VDDI interface) Reset circuit (VDD interface) XT circuit (5V interface) OSC circuit (5V interface) User circuit USER.RESET USER.XT USER.OSC Reset circuit XT oscillation circuit OSC oscillation circuit 3V power supply VSS (GND) Figure 3-2 Power Supply Interface Example Figure 3-2 shows one possible power supply setup using external clock signals and external power supplies for VDDI, the port interface power supply voltage, and VDD, the positive power supply voltage. The user application system uses VDDI, not VDD. 3-10 Chapter 3. Setting Up and Starting Up EASE63180 emulator User cable User application system + VDD5 VDD4 VDD3 VDD2 VDD1 1/4 VDD5 VDD4 VDD3 VDD2 VDD1 Expansion LCD driver - LCD bias power supply J2 1/5 VSS C1 C2 J1 Figure 3-3 Interface Example for Expansion LCD Driver with External Bias Power Supply Figure 3-3 shows the power supply connections for an expanded LCD driver. Such a driver requires an external LCD bias power supply. 3-11 Chapter 3. Setting Up and Starting Up The following table gives the signal levels for user cable and probe cable pins. Pin Ports 0 to F BD, BD MD, MD COM1 to COM16 SEG0 to SEG63 USER.RESET USER.XT USER.OSC XT.OUT HALT.OUT SYNC.OUT EXT.BRK PROBE0 to PROBE3 VDDI VDD VDD Interface voltage VDD1 to 5 V VDD1 to 5 V VDD 5V 5V 5V 5V VDDI VDDI VDDI n Note 2 n ________________________________________________________________________________________________________________ The LCD drive signal (COMxx and SEGxx) output levels depend on the jumper 1 (J1) setting. * External: * Internal: VDD1 to VDD5 from external LCD bias power supply Central levels from 1.1 to 5.5 V ________________________________________________________________________________________________________________________________ Caution The VDDI and VDD input voltages must be between 0.9 and 5 V. Using a voltage in excess of 5 V risks damaging the evaluation chip. 3-12 Chapter 3. Setting Up and Starting Up 2.3 Powering Up First make sure that * the emulator switches and jumpers have been properly set, * the crystal board's crystal and jumpers have been set, * the EPROMs containing the user application program have been installed, and * the emulator is connected to the user application system. Follow the procedure below to start the emulator. 1. Turn on the power to the emulator. 2. Wait for the emulator's POWER LED to light. 3. Wait for the emulator's RUN LED to light. If it does not light, press the reset switch at the rear of the emulator. 4. Turn on the power to the user application system. 5. Press the reset switch on the user application system. 6. Check the user cable USER.OSC and USER.XT outputs. n Note 1 n _______________________________________________________________________________________________________________ Always power up the emulator and then the user application system. Power down in the reverse order. _______________________________________________________________________________________________________________________________ Caution Pay close attention to the sequence of applying power, or you could damage the emulator. (1) When turning power on: a. Turn on power to the emulator. b. Turn on power to the user application system. (2) When turning power off a. Turn off power to the user application system. b. Turn off power to the emulator. 3-13 Chapter 3. Setting Up and Starting Up 3. Emulation This configuration is for high-level debugging using a dedicated debugger running on a development host. 3.1 Switch and Jumper Settings This section describes the switch and jumper settings needed before starting the emulator. (1) MODE switch Set this switch to its EMU position to select emulation. (2) DIP switches Set the SETICE switch to its OFF position. Set the BAUD switches to match the development host baud rate. BAUD switch baud rate 4,800bps 9,600bps 19,200bps 38,400bps 51,200bps 57,600bps 76,800bps 115,200bps OFF OFF OFF ON ON ON ON OFF OFF OFF ON OFF ON ON OFF ON OFF ON OFF OFF ON OFF ON ON ON OFF OFF OFF OFF ON ON ON 38400 19200 9600 4800 n Note 1 n ________________________________________________________________________________________________________________ The IBM PC/AT and compatibles do not support the 51,200bps and 76,800bps speeds. If turning on or resetting the EASE63180 fails to produce an initialization message on the dedicated debugger's screen, lower both the EASE63180 baud rate setting and the dedicated debugger's speed parameter. ________________________________________________________________________________________________________________________________ 3-14 Chapter 3. Setting Up and Starting Up (3) VDD+VDDI.SEL1 and VDDI.SEL2 switches Select the power supply configurations for VDDI, the port interface power supply voltage, and VDD, the positive power supply voltage. Power supply Port interface power supply (VDDI) Internal 5 V power supply Internal 3 V power supply External (from user cable VDDI pin) External (from user cable VDD pin) VDD, VDDI.SEL1 IN VDDI.SEL2 Positive power supply (VDD) Internal 5 V power supply 5V 3V EXT Don't care (4) OSC.SEL switch Select the high-speed (OSC) clock source. Clock source Internal External (from user cable USER.OSC pin) OSC.SEL IN EXT (5) XT.SEL switch Select the low-speed (XT) clock clock source. Clock source Internal External (from user cable USER.XT pin) XT.SEL IN EXT n Note 2 n _______________________________________________________________________________________________________________ The emulator ships with a 32.768-kHz crystal oscillator for its internal XT source on the crystal board. To change the frequency, replace this crystal. If you do, however, be sure to check the output at the monitor pin XT.OUT. _______________________________________________________________________________________________________________________________ (6) Crystal board jumper (JP) The emulator ships with these jumper pins open, selecting RC oscillation with the ROS resistor provided for the high-speed clock. To switch to ceralock oscillation, short-circuit the pins and install a ceralock oscillator and oscillation capacitors on the crystal board. Oscillation mode Ceralock oscillation RC oscillation Jumper pins Shorted Open 3-15 Chapter 3. Setting Up and Starting Up To use ceralock oscillation, install a ceralock oscillator and oscillation capacitors on the crystal board. Ceralock Capacitors for ceralock oscillation Crystal for internal low-speed clock (32.768 kHz crystal mounted when shipped) JP Ceralock/RC jumper To use RC oscillation, install an ROS resistor with the value given in the user's manual for the microcontroller. ROS resistor for RC oscillation Crystal for internal low-speed clock (32.768 kHz crystal mounted when shipped) JP n Note 3 n ________________________________________________________________________________________________________________ If you replace the crystal for the internal high-speed clock, or switch between ceralock oscillation and RC oscillation, be sure to check the output at the monitor pins XT.OUT and OSC.OUT. ________________________________________________________________________________________________________________________________ 3-16 Chapter 3. Setting Up and Starting Up (7) LCD bias jumper Specify the LCD bias power supply with jumper 1 (J1). Using an expansion LCD driver requires an external power supply. LCD bias power supply External Internal J1 EXT C IN External power supply The emulator ships with J1 in its IN position. Jumper 2 (J2) specifies the LCD driver bias: 1/4 or 1/5. EXT C J1 J1 setting C shorted with EXT C shorted with IN Jumper IN Internal power supply Bias 1/4 1/5 J2 1/5 C 1/4 1/5 bias J2 setting C shorted with 1/4 C shorted with 1/5 J2 1/5 C 1/4 1/4 bias Jumper The emulator ships with J2 in its 1/5 position. These jumpers are located on the topmost printed circuit board in the emulator. Remove the top cover to access them. 3-17 Chapter 3. Setting Up and Starting Up J1 Low EPROM socket High EPROM socket EVA J2 (8) Backup circuit jumpers Jumpers J4 and J5 switch backup on and off. Backup Backup ON VDD=0.9V to 2.7V Backup OFF VDD=1.8V to 5.0V J4 and J5 settings J4 Short pins 4 and 5 J5 Short pins 6 and 7 J4 Short pins 1 and 2 J5 Short pins 9 and 10 Jumper 5 1 Jumper J4 J5 6 10 5 1 J4 J5 Backup OFF 6 10 Backup ON The emulator ships with backup off. These jumpers are located on the topmost printed circuit board in the emulator. Remove the top cover to access them. EVA J1 Low EPROM socket High EPROM socket J2 3-18 Chapter 3. Setting Up and Starting Up Caution If VDD exceeds 2.7 V, turn the backup circuit off. Otherwise, the circuit generates high voltages that could damage the emulator. 3-19 Chapter 3. Setting Up and Starting Up 3.2 Emulator Connections EASE63180 High EPROM PROBE USRCN1 User cable 1 User application system Low EPROM Emulator power supply (4.75 to 5.25 V) 50 pins USRCN1-1 50 pins USRCN1-2 + - DC power cable USRCN2 DC5V User cable 2 40 pins USRCN2-1 40 pins USRCN2-2 User application system VDD VSS ACIN Power cable User application system power supply + Grounded AC outlet (100 to 240 V AC) 0.9 to 5V Positive power supply + + - 0.9 to 5V VDD VSS Port interface power supply 0.9 to 5V VDDI VSS Figure 3-4 Connections for Emulation n Note 1 n ________________________________________________________________________________________________________________ (1) (2) Do not connect the user cables or probe cable is there is no user application system connected to the emulator. The VDDI and VDD power supplies shown are not necessary when the user application program draws upon the emulator's internal power supplies. The third is always required because the user cables do not supply this power to the user application system. (3) Connecting the DC power supply cable automatically isolates the built-in switching regulator. ________________________________________________________________________________________________________________________________ 3-20 Chapter 3. Setting Up and Starting Up 3.3 Powering Up First make sure that * the emulator switches and jumpers have been properly set, * the crystal board's crystal and jumpers have been set, * the EPROMs containing the user application program have been installed, and * the emulator is connected to the user application system. Follow the procedure below to start the emulator. 1. Load the dedicated debugger. 2. Turn on the power to the emulator. 3. Wait for the emulator's POWER LED to light. 4. Turn on the power to the user application system. 5. Press the reset switch on the user application system. 6. Check the user cable USER.OSC and USER.XT outputs. n Note 1 n _______________________________________________________________________________________________________________ Always power up the emulator and then the user application system. Power down in the reverse order. _______________________________________________________________________________________________________________________________ Caution Pay close attention to the sequence of applying power, or you could damage the emulator. (1) When turning power on: a. Turn on power to the emulator. b. Turn on power to the user application system. (2) When turning power off a. Turn off power to the user application system. b. Turn off power to the emulator. 3-21 Chapter 4. Additional Usage Notes Chapter 4. Additional Usage Notes 1. Debugging Notes (1) Power on/off sequence When a user application system is connected, always power up the emulator and then the user application system. Power down in the reverse order. (2) Flag bits and start/stop addresses Only breakpoint, trace enable, and sync out bit and start and stop address specifications corresponding to the first word of an instruction produce results. One specifying the second word of a two-word instruction or an entry in the ROM table is ignored. (3) User cable pins * The allowed input voltage range for the user cable VDDI and VDD pins is 0.9 to 5 V. * User cable reset (USER.RESET) input is only relevant during evaluation and real-time emulation. * The external clock signal (USER.OSC and USER.XT) pins have input signal levels of 5 V. * The halt mode (HALT.OUT), low-speed clock (XT.OUT), and high-speed clock (OSC.OUT) pins have output signal levels of 5 V. Note, however, that these pins are not present on the volume production versions of MSM63180 family microcontrollers. * Each I/O pin from port 0 through F includes a 22-ohm protection resistor in series. (4) LCD bias The jumper 2 (J2) setting (1/4 or 1/5 bias) must match the user application program's setting in the microcontroller's Display Control Register 0 (DSPCON0) bit 3 (BISEL). (5) Terminating halt mode A user break terminates halt mode if it is in effect. Restarting real-time emulation without specifying a starting address causes execution to resume from the instruction after the HALT instruction. Note that forcing resumption this way can produce different results from normal execution. (6) Ceralock oscillation The emulator handles ceralock oscillation a little differently from the volume production versions of MSM63180 family microcontrollers. We therefore recommend that testing with the next stage, a onetime programmable (OTP) version, include a full review of any switches to ceralock oscillation. Item Switching between ceralock and RC oscillation Time lag between setting Frequency Control Register (FCON) bit 1 (ENOSC) to "1" and start of ceralock oscillation Emulator Jumper on crystal board Microcontroller Frequency Control Register (FCON) bit 2 (OSCSEL) Approximately 10 ms Oscillation starts when emulator is turned on, so clock signal is immediately available. 4-2 Chapter 4. Additional Usage Notes 2. Initialization The following table summarizes the results of the initializations when the power is first applied and when the reset switch is pressed. Item Evaluation chip Powering up Same as for production versions of MSM63180 family microcontrollers Reset Break conditions Breakpoint break, call stack overflow break, register stack overflow break Breakpoint bits Break status Trace memory Trace condition Trace trigger Trace enable bits Trace pointer Cycle counter Cycle counter trigger User reset Sync out bits IE bits Memory expansion Timers All "0" Dummy "No break status" Blank All addresses traced Free-running trace All "0" Zero Zero Free-running trace Input disabled All "0" All "0" Expansion off TBC and WDT operative Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged 4-3 Chapter 4. Additional Usage Notes 3. Operation Timing M1 S1 CLK S2 S1 M1 S2 S1 M1 S2 S1 M2 S2 S1 M1 S2 S1 M2 S2 S1 M3 S2 M1.S1 PC Trace Latch Trace Write Figure 4-1 Trace Timing Chart M1 S1 CLK S2 S1 M1 S2 S1 M1 S2 S1 M2 S2 S1 M1 S2 S1 M2 S2 S1 M3 S2 M1.S1 PC Cycle Counter up Syncout clock Figure 4-2 Cycle Counter/Sync Out Timing Chart 4-4 Chapter 4. Additional Usage Notes RESET CYCLE M1 S1 CLK S2 S1 M1 S2 S1 M1 S2 S1 M2 S2 S1 M1 S2 S1 M2 S2 S1 M3 S2 RST RESET released 4Hz M1.S1 Figure 4-3 Reset Timing Chart HALT RTI M1 S1 CLK S2 S1 M1 S2 S1 M1 S2 S1 M1 S2 S1 M1 S2 S1 M1 S2 S1 M1 S2 HLT M1.S1 Interrupt request INT n+1 (INT) (INT)+1 (INT)+2 n+2 n+3 PC n n: HALT instruction address (INT): Entry point of interrupt service routine Figure 4-4 Halt Mode Timing Chart 4-5 Appendices Appendices A.1 User Cable Connectors (1) User Cable 1 The following figure shows this cable. The large connector plugs into the 100-pin USRCN1 connector on the emulator. 100-pin connector EASE63180 USRCN1 Pin 1 (red) Pin 1 (red) 50-pin connector USRCN1-1 USRCN1-2 50-pin connector Connector header: Hirose HIF3BA-50PA-2.54DSA A-2 Connector header: Hirose HIF3BB-50PA-2.54DSA Appendices (2) User Cable 2 The following figure shows this cable. The large connector plugs into the 80-pin USRCN2 connector on the emulator. 80-pin connector EASE63180 USRCN2 Pin 1 (red) Pin 1 (red) 40-pin connector USRCN2-1 USRCN2-2 40-pin connector Connector header: Hirose HIF3BA-40PA-2.54DSA Connector header: Hirose HIF3BA-40PA2.54DSA A-3 Appendices A.2 User Cable Pin Layouts The 100-pin USRCN1 and 80-pin USRCN2 connectors on top of the emulator are for the user cables. USRCN2 Pin 80 Pin 40 USRCN1 Pin 100 Pin 50 Pin 41 Pin 1 Pin 51 Pin 1 n Note 1 n ________________________________________________________________________________________________________________ The connectors provide access to all port, segment, and other pins that the evaluation chip shares with the volume production masked ROM version. Refer to the microcontroller's User's Manual for the meanings of the signal names in the tables below. ________________________________________________________________________________________________________________________________ n Note 2 n ________________________________________________________________________________________________________________ USRCN1-1 and USRCN1-2, the connectors at the user application end of user cable 1 have 50 pins; USRCN2-1 and USRCN2-2, 40. A triangle on the connector indicates pin 1. ________________________________________________________________________________________________________________________________ Pin 1 Pin 1 indicator n-1 n Pin 2 n=40 or 50 A-4 Appendices User Cable Pin List 1: USRCN1 to USRCN1-1 (50 pins) USRCN1 (emulator) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 USRCN1-1 (user) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal name USRCN1 (emulator) 26 USRCN1-1 Signal name (user) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P51 P52 P53 P60 P61 P62 P63 P70 P71 P72 P73 P80 P81 P82 P83 P90 P91 P92 P93 PA0 PA1 PA2 PA3 PB0 PB1 VDDI 27 28 29 P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P40 P41 P42 P43 P50 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A-5 Appendices User Cable Pin List 2: USRCN1 to USRCN1-2 (50 pins) USRCN1 (emulator) 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 USRCN1-2 (user) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal name USRCN1 (emulator) USRCN1-2 (user) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal name PB2 PB3 PC0 PC1 PC2 PC3 PD0 PD1 PD2 PD3 PE0 PE1 PE2 PE3 PF0 PF1 PF2 PF3 BD BD MD MD 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 VDD VDD5 VDD4 VDD3 VDD2 VDD1 USER.RESET VSS (GND) XT.OUT VSS (GND) OSC.OUT VSS (GND) HALT.OUT VSS (GND) USER.XT VSS (GND) USER.OSC VDD 99 100 VSS (GND) A-6 Appendices User Cable Pin List 3: USRCN2 to USRCN2-1 (40 pins) USRCN2 (emulator) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 USRCN2-1 Signal name (user) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG0 SEG1 SEG2 SEG3 USRCN2 (emulator) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 USRCN2-1 (user) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal name SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 A-7 Appendices User Cable Pin List 2: USRCN2 to USRCN2-2 (40 pins) USRCN2 (emulator) 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 USRCN2-2 Signal name (user) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 USRCN2 (emulator) 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 USRCN2-2 (user) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal name SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 A-8 Appendices A.3 Probe Cable Connectors and Pin Layout The probe connector on top of the emulator is for the probe cable. Probe Connector Pin 16 Pin 15 Pin 2 Pin 1 Probe Connector Pin List Pin number 1 2 3 4 5 6 7 8 Probe color Black Brown Red Orange - Name PROBE0 VSS PROBE1 VSS PROBE2 VSS PROBE3 VSS Pin number 9 10 11 12 13 14 15 16 Probe color Yellow Green Blue Purple - Name SYNC.OUT VSS EXT.BRK VSS VSS VSS VSS VSS n Note 1 n _______________________________________________________________________________________________________________ (1) PROBE0 to PROBE3 are for tracing external signals. (2) SYNC.OUT produces a pulse each time that the emulator executes the instruction at an address with its sync out bit set to "1." (3) EXT.BRK is an external break signal. _______________________________________________________________________________________________________________________________ A-9 Appendices black brown red orangeyellow green blue purple Polarity mark Probe cable A-10 Appendices A.4 RS-232C Cable Wiring Diagrams TCS-DRIBM (9-9 pin cable) 2m 9-pin D-SUB connector (female) 9-pin D-SUB connector (male) Emulator DCD RXD TXD DTR GND DSR RTS CTS RI 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 DCD TXD RXD DSR GND DTR CTS RTS RI A-11 Appendices TCS-DRPC (25-9 pin cable) 2m 25-pin D-SUB connector (male) 9-pin D-SUB connector (male) Emulator S*EGND TXD RXD RTS CTS DSR F*EGND DCD DTR 1 2 3 4 5 6 7 8 20 N.C. 1 2 3 4 5 6 7 8 9 DCD TXD RXD DSR GND DTR CTS RTS RI n Note 1 n ________________________________________________________________________________________________________________ All pins other than those listed above are not connected. ________________________________________________________________________________________________________________________________ A-12 Appendices A.5 RS-232C Interface Circuit EASE63180 MSM82C51 (UART) TXD RXD DSR DTR CTS RTS +5V MAX237 (Level converters) 2 3 4 6 7 8 1 5 N.C. 9 RS-232C connector A-13 Appendices A.6 Installing EPROMs There are two EPROM sockets on top of the emulator. Evaluation involves executing the user application program directly from EPROMs in them. Emulation offers commands for transferring EPROM contents to code memory. Install an EPROM in its socket with the following procedure. (1) Turn off the power to the emulator. (2) Flip the lever beside the socket to its vertical position to unlock the socket. Pin 1 (3) (4) Fit the EPROM containing half of the user application program into the socket. Flip the locking lever to the side to lock the EPROM in place. Pin 1 EPROM locking lever EPROM socket A-14 Appendices The sockets accept the following EPROM types. Note how the position of pin 1 differs for each type. * MSM27512 and compatible devices (64K 5 8 bits; 28 pins) * MSM27101 and compatible devices (128K 5 8 bits; 32 pins) (1) MSM27512 Pin 32 28 t t Install with pin 14 all the way to the right. Pin 1 Pin 14 (2) MSM27101 Pin 32 Pin 28 t t Install with pin 16 all the way to the right. Pin 1 Pin 16 n Note 1 n _______________________________________________________________________________________________________________ Always be sure that the power is off before removing or installing an EPROM. _______________________________________________________________________________________________________________________________ n Note 2 n _______________________________________________________________________________________________________________ A user application program always requires two EPROMs: one each in the EPROM.HIGH and EPROM.LOW sockets. See Chapter 2 Section 2.2.2 for such details as programming ranges. _______________________________________________________________________________________________________________________________ A-15 Appendices A.7 If Emulator Doesn't Start Symptom Possible cause The emulator is operating properly. not Procedure Restart the emulator. The ERROR LED lights. The evaluation chip is not operating properly. Check the parameters for each component on the crystal board (if changed since shipping). Then restart the emulator. The serial link to development host is operating properly. the Make sure that the baud rate and not other serial interface parameters of the development host match those of the emulator. Make sure that the cable specifications match those of the development host's serial port. Check the cable connections. All LEDs other than the HALT display LED light. The emulator's main control CPU has detected a system bus error due to noise, etc. The emulator is inoperative. Restart the emulator. The LEDs do not light. The debugger stalls after displaying its starting message. Make sure that the power supply cable is connected. Then restart the emulator. A-16 Appendices A.8 Pin Configurations (1) I/O Ports The pins for I/O ports 0 to F each have an internal 22-ohm protection resistor. Evaluation chip MSM63E180 USRCN1 5 6 7 8 22 P0.0 P0.1 P0.2 P0.3 65 66 67 68 PF.0 PF.1 PF.2 PF.3 (2) LCD Outputs The evaluation chip's LCD drive signal (COMxx and SEGxx) pins are directly connected to USRCN2. Evaluation chip MSM63E180 COM1 COM2 USRCN2 1 2 15 16 17 18 COM15 COM16 SEG0 SEG1 79 80 SEG62 SEG63 A-17 Appendices (3) USER.RESET Reset signal from main CPU Reset input to evaluation chip USER.RESET 51K 1/2 VDD Reset switch signal A built-in voltage conversion circuit converts the user cable reset (USER.RESET) input to the internal "H" level from VDD, the positive power supply voltage (0.9 to 5 V). + (4) USER.OSC Internal 5V power supply 51K USER.OSC HC541 External high-speed clock The user cable high-speed clock (USER.OSC) input uses the emulator's internal operating voltage (5V) for its "H" level. (5) USER.XT Internal 5V power supply 51K USER.XT HC541 External low-speed clock The user cable low-speed clock (USER.XT) input uses the emulator's internal operating voltage (5 V) for its "H" level. A-18 Appendices (6) OSC.OUT High-speed clock input to evaluation chip HC541 OSC.OUT The high-speed clock (OSC.OUT) signal uses the emulator's internal operating voltage (5 V) for its "H" level. (7) XT.OUT Low-speed clock input to evaluation chip HC541 XT.OUT The high-speed clock (XT.OUT) signal uses the emulator's internal operating voltage (5 V) for its "H" level. (8) PROBE0 to PROBE3 PROBE0 51K PROBE1 51K PROBE2 51K PROBE3 (Probe cable) 51K + + + + 1/2 VDDI To trace circuit Built-in voltage conversion circuits convert the trace (PROBE0 to PROBE3) inputs to the internal "H" level from VDDI, the port interface power supply voltage (0.9 to 5 V). (9) EXT.BRK EXT.BRK (Probe cable) 51K + 1/2 VDDI Rising signal detection circuit External break request A-19 Appendices A built-in voltage conversion circuit converts the break (EXT.BRK) input level of VDDI, the port interface power supply voltage (0.9 to 5 V), to the internal "H" level. (10) SYNC.OUT VDDI Sync out bit value Level conversion SYNC.OUT (Probe cable) A built-in voltage conversion circuit converts the sync out (SYNC.OUT) signal "H" level to VDDI, the port interface power supply voltage (0.9 to 5 V), for output. A-20 |
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