08/02/99
Errata: CS7620 Rev. B
(Reference CS7620 Data Sheet revision DS301PP2 dated JUL `99)
1) "data_valid" output mode The data_valid output mode is turned on by setting register 3Fh bit [6] to "1". If this mode is the chosen output mode, the user has to RESET and afterwards SET this register bit every time after coming out of "power down" mode. The reset and set is necessary in order to synchronize 2 internal state machines with each other. Please note that the registers can only be accessed 500usec after the chip comes out of power down mode. 2) Active pixel definition in "data_valid" output mode The data_valid signal is present over all the non-black (dark) rows. Some of these rows do not contain valid picture information since there is a transition from black to active rows. The user has to delete these "invalid" rows in the subsequent ASIC DSP processor. Note that the register 1Eh is unused in this data_valid mode. Also note that it is still possible to control the timing of the data_valid signal in the horizontal pixel direction by programming register 1Fh appropriately. 3) Automatic calibration after reset and power down If the pixel clock frequency is different from the incoming master clock frequency the automatic calibration is not working correctly after a reset or a power down (register 3Fh clk_divide defines the divider value). If calibration is necessary a manual calibration can be performed as follows: After reset and first power up: 1) Wait at least 500usec after power up to get the chip into a valid operating condition. 2) Write the desired divide_clk setting to register 3Fh bits [4:0]. 3) Write a "11" to register 07h bits [1:0], to turn off the auto calibration and to perform a single manual calibration. After each power up with no reset 1) Wait at least 500usec after power up to get the chip into a valid operating condition. 2) Write a "1" to register 07h bit [0], to perform a single manual calibration.
If there are any questions concerning this information, Please contact Crystal Applications Support: 512-445-7222
Cirrus Logic P.O. Box 17847, Austin, Texas 7876 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
ER301A2 AUG '99 1
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