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Semiconductor
January 1998
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CD74HC646, CD74HC648
High Speed CMOS Logic Octal Bus Transceiver/Register, Three-State
Description
The Harris CD74HC646 and CD74HC648 are octal bus transceivers/registers with three-state non-inverting outputs. The Harris CD74HC648 is an octal bus transceiver/register with three-state inverting outputs. These devices are bus transceivers with D-type flip-flops which act as internal storage registers. Data on the A bus or the B bus can be clocked into the registers on the LOW-to-HIGH transition of either CAB or CBA clock inputs. Outputs enable (OE) and direction (DIR) inputs control the transceiver functions. Data present at the high impedance output can be stored in either register or both but only one of the two buses can be enabled as outputs at any one time. The select controls (SAB and SBA) can multiplex stored and transparent (real time) data. The direction control determines which data bus will receive data when the output enable (OE) is LOW. In the high impedance mode (output enable HIGH), A data can be stored in one register and B data can be stored in the other register. The clocks are not gated with the direction (DIR) and output enable (OE) terminals; data at the A or B terminals can be clocked into the storage flip-flops at any time.
Features
* Independent Registers for A and B Buses * CD74HC646 Non-Inverting * CD74HC648 Inverting * Three-State Outputs * Drives 15 LSTTL Loads * Typical Propagation Delay = 12ns (A to B, B to A) at VCC = 5V, CL = 15pF, TA = 25oC * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
Ordering Information
PART NUMBER TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 24 Ld PDIP 24 Ld SOIC 24 Ld SOIC PKG. NO. E24.3 M24.3 M24.3
Pinout
CD74HC646, CD74HC648 (PDIP, SOIC) TOP VIEW
CD74HC648EN CD74HC646M CD74HC648M NOTES:
CAB 1 SAB 2 DIR 3 A0 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 11 GND 12 24 VCC 23 CBA 22 SBA 21 OE 20 B0 19 B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7
1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1998
File Number
1664.1
1
CD74HC646, CD74HC648 Functional Diagram
A0 A1 A2 A DATA PORT A3 A4 A5 A6 A7 4 5 6 7 8 9 10 11 21 OE DIR FLIP-FLOP CLOCKS DATA SOURCE SELECTION INPUTS CAB CLOCK CBA CLOCK SAB SOURCE SBA SOURCE 3 1 23 2 22 20 19 18 17 16 15 14 13 B0 B1 B2 B3 B4 B5 B6 B7 B DATA PORT
GND = PIN 12 VCC = PIN 24
FUNCTION TABLE INPUTS DATA I/O (NOTE 3) A0 THRU A7 Input B0 THRU B7 Not Specified Input OPERATION OR FUNCTION
OE X
DIR X
CAB X H or L X X X H or L
CBA X H or L X H or L X X
SAB X
SBA X
CD74HC646 Store A, B Unspecified
CD74HC648 Store A, B Unspecified
X
X
X
X
Not Specified Input
Store B, A Unspecified
Store B, A Unspecified
H H L L L L NOTE:
X X L L H H
X X X X L H
X X L H X X
Input
Store A and B Data Isolation, Hold Storage
Store A and B Data Isolation, Hold Storage Real-Time B Data to A Bus Stored B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus
Output
Input
Real-Time B Data to A Bus Stored B Data to A Bus
Input
Output
Real-Time A Data to B Bus Stored A Data to B Bus
3. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data inputs functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. To prevent excess currents in the High-Z modes all I/O terminals should be terminated with 10k resistors.
2
CD74HC646, CD74HC648
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA
Thermal Information
Thermal Resistance (Typical, Note 4) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 4. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Three-State Leakage Current II ICC IOZ VCC or GND VCC or GND VIL or VIH VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -6 -7.8 0.02 0.02 0.02 6 7.8 0 VO = VCC or GND 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 0.5 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 5 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 10 V V V V V V V V V V V V V V V V V V A A A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
3
CD74HC646, CD74HC648
Prerequisite for Switching Specifications
25oC PARAMETER HC TYPES Maximum Frequency fMAX 2 4.5 6 Setup Time Data to Clock tSU 2 4.5 6 Hold Time Data to Clock tH 2 4.5 6 Clock Pulse Width tW 2 4.5 6 6 30 35 60 12 10 35 7 6 80 16 14 5 25 29 75 15 13 45 9 8 100 20 17 4 20 23 90 18 15 55 11 9 120 24 20 MHz MHz MHz ns ns ns ns ns ns ns ns ns SYMBOL VCC (V) MIN TYP MAX -40oC TO 85oC MIN TYP MAX -55oC TO 125oC MIN TYP MAX UNITS
Switching Specifications
CL = 50pF, Input tr, tf = 6ns 25oC -40oC TO 85oC MAX MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay Store A Data to B Bus Store B Data to B Bus (646)
SYMBOL
TEST CONDITIONS
VCC (V)
MIN
TYP
tPHL, tPLH
CL = 50pF 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 18 20 12 220 44 37 240 48 41 135 27 23 275 55 47 300 60 51 170 34 29 330 66 56 360 72 61 205 41 35 ns ns ns ns ns ns ns ns ns ns ns ns
tPHL, tPLH Store A Data to B Bus Store B Data to B Bus (648)
CL = 50pF
A Data to B Bus B Data to A Bus (646)
tPLH, tPHL
CL = 50pF
4
CD74HC646, CD74HC648
Switching Specifications
CL = 50pF, Input tr, tf = 6ns (Continued) 25oC PARAMETER A Data to B Bus B Data to A Bus (648) SYMBOL tPLH, tPHL TEST CONDITIONS CL = 50pF VCC (V) 2 4.5 CL = 15pF CL = 50pF Select to Data (646) tPLH, tPHL CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Select to Data (648) tPLH, tPHL CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Three-State Disabling Time Bus to Output or Register to Output tPLZ, tPHZ CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Three-State Enabling Time Bus to Output or Register to Output tPZL, tPZH CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Output Transition Time tTLH, tTHL CL = 50pF 5 6 2 4.5 CL = 50pF Input Capacitance Three-State Output Capacitance Maximum Frequency Power Dissipation Capacitance (Notes 5, 6) NOTES: 5. CPD is used to determine the dynamic power consumption, per package. 6. PD = VCC2 CPD fi VCC2 CL fo where fi = Input Frequency, fo = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. CIN CO CL = 50pF 6 MIN 10 TYP 12 14 16 14 14 MAX 150 30 26 170 34 29 190 38 32 175 35 30 175 35 30 60 12 10 10 20 -40oC TO 85oC MIN MAX 190 38 33 215 43 37 240 48 39 220 44 37 220 44 37 75 15 13 10 20 -55oC TO 125oC MIN MAX 225 45 38 255 51 43 285 57 48 265 53 45 265 53 45 90 18 15 10 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF
fMAX CPD
CL = 15pF -
5 5
-
60 52
-
-
-
-
-
MHz pF
5
CD74HC646, CD74HC648 Test Circuits and Waveforms
tr = 6ns I fCL VCC 50% 10% tWL 50% 50% GND tWH INVERTING OUTPUT tPHL tPLH tTHL tTLH 90% 50% 10% INPUT 90% 50% 10% tf = 6ns VCC
trCL CLOCK 90% 10%
tfCL
tWL + tWH =
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
trCL CLOCK INPUT 90% 10% tH(H)
tfCL VCC 50% GND tH(L) VCC
DATA INPUT tSU(H) tTLH 90% OUTPUT tPLH tREM VCC SET, RESET OR PRESET tSU(L) tTHL 90% 50% 10% tPHL
50% GND
6ns OUTPUT DISABLE 90% 50%
6ns VCC 10% tPZL 50% 10% tPHZ tPZH 90% 50% OUTPUTS DISABLED OUTPUTS ENABLED GND
tPLZ OUTPUT LOW TO OFF
50% GND OUTPUT HIGH TO OFF CL 50pF OUTPUTS ENABLED
IC
FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 4. HC THREE-STATE PROPAGATION DELAY WAVEFORM
OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE
IC WITH THREESTATE OUTPUT
OUTPUT RL = 1k CL 50pF
VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1k to VCC, CL = 50pF. FIGURE 5. HC THREE-STATE PROPAGATION DELAY TEST CIRCUIT
6

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