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HV230/232
HV230/HV232
Low Charge Injection 8-Channel High Voltage Analog Switches with Bleed Resistors
Features
HVCMOS technology for high performance Very low quiescent power dissipation - 10A Output On-resistance typically 22 ohms Integrated bleed resistors on the outputs Low parasitic capacitances DC to 10MHz analog signal frequency -60dB typical output off isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies
(R)
General Description
The Supertex HV230 and HV232 are low charge injection 8-channel high-voltage analog switch integrated circuits (ICs) with bleed resistors. These devices can be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. These ICs are suitable for various combinations of high voltage supplies, e.g., VPP/VNN : +50V/-150V, or +100V/-100V.
Applications
Medical ultrasound imaging Piezoelectric transducer drivers
Block Diagram
LATCHES LEVEL SHIFTERS OUTPUT SWITCHES
D LE CL
DIN
SW0
D LE CL
CLK
SW1
D LE CL
SW2
D LE CL
8 BIT SHIFT REGISTER
SW3
D LE CL
SW4
D LE CL
SW5
DOUT
D LE CL
SW6
D LE CL
SW7
VDD
LE
CL
V NN V PP
RGND
1
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HV230/232 Absolute Maximum Ratings*
VDD Logic power supply voltage VPP - VNN Supply voltage VPP Positive high voltage supply VNN Negative high voltage supply Logic input voltages Analog Signal Range Peak analog signal current/channel Storage temperature Power dissipation: 28-lead PLCC 48-lead TQFP 26-lead TAPP 26-lead -BGA -0.5V to +15V 220V -0.5V to VNN +200V +0.5V to -200V -0.5V to VDD +0.3V VNN to VPP 3.0A -65C to +150C 1.2W 1.0W 1.0W 1.0W
* Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Operating Conditions*
Symbol VDD VPP VNN VIH VIL VSIG TA Parameter Logic power supply voltage1, 3 supply1, 3 supply1, 3 Positive high voltage Value 4.5V to 13.2V 40V to VNN+ 200V -40V to -160V VDD -1.5V to VDD 0V to 1.5V VNN +10V to VPP -10V2 0C to 70C
Negative high voltage
High-level input voltage Low-level input voltage Analog signal voltage peak to peak Operating free air-temperature
Notes: 1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2 VSIG must be VNN - VSIG - VPP or floating during power up/down transistion. 3 Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.
Ordering Information
Package Options 28-Lead plastic chip carrier HV232PJ 48-Lead TQFP HV232FG 26-lead TAPP 26-lead -BGA HV232GA Die HV232X
VPP - VNN 200V 200V
HV230TA
-
-
-
-
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Truth Table
D0 L H L H L H L H L H L H L H L H X X D1 D2 D3 D4 D5 D6 D7 LE L L L L L L L L L L L L L L L L H X CL L L L L L L L L L L L L L L L L L H SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON HOLD PREVIOUS STATE OFF OFF OFF OFF OFF OFF OFF OFF
HV230/232
X X
X X
X X
X X
X X
X X
X X
Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when data in shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs.
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HV230/232 Electrical Characteristics
DC Characteristics (over recommended operating conditions unless otherwise noted)
Characteristics Sym 0C min max 30 25 Small Signal Switch (ON) Resistance RONS 25 18 23 22 Small Signal Switch (ON) Resistance Matching Large Signal Switch (ON) Resistance Output Switch Shunt Resistance Switch Off Leakage Per Switch DC Offset Switch Off DC Offset Switch On Pos. HV Supply Current Neg. HV Supply Current Pos. HV Supply Current Neg. HV Supply Current Switch Output Peak Current Output Switch Frequency fSW 6.5 IPP Supply Current IPP 4.0 4.0 6.5 INN Supply Current INN 4.0 4.0 Logic Supply Average Current Logic Supply Quiescent Current Data Out Source Current Data Out Sink Current Logic Input Capacitance
*Typical values only for HV232
min
+25C typ* 26 22 22 18 20 16 5.0 15
max 38 27 27 24 25 25 20
+70C min max 48 32 30 27 30 27 20
Units
Test Conditions ISIG = 5mA VPP = 40V, VPP = 100V, VPP = 160V,
ISIG = 200mA VNN = -160V ISIG = 5mA ISIG = 5mA % ISIG = 200mA VNN = -100V ISIG = 200mA VNN = -40V ISW = 5mA, VPP = 100V, VNN = -100V VSIG = VPP - 10V, ISIG = 1A Output switch to RGND IRINT = 0.5mA VSIG = VPP - 10V No Load No Load ALL SWs OFF ALL SWs OFF ALL SWs ON, ISW = 5mA ALL SWs ON, ISW = 5mA VSIG duty cycle - 0.1% Duty Cycle = 50% VPP = 40V, VNN = -160V mA VPP = 100V, VNN = -100V VPP = 160V, VNN = -40V VPP = 40V, VNN = -160V mA VPP = 100V, VNN = -100V VPP = 160V, VNN = -40V mA A mA mA VOUT = VDD - 0.7V VOUT = 0.7V fCLK = 5MHz, VDD = 5.0V
RONS RONL RINT ISOL
20
20 5.0 300 500
35 1.0 100 100 10 -10 10 -10
50 10 300 500 50 -50 50 -50 2.0 50 7.0 5.0 5.0 7.0 5.0 5.0 4.0 10 8.0 5.5 5.5 8.0 5.5 5.5 4.0 10 0.40 0.40 10 10 2.0 15 300 500
K
A mV mV A A A A A KHz
IPPQ INNQ IPPQ INNQ 3.0
3.0
50KHz Output Switching Frequency with no load
IDD IDDQ ISOR ISINK CIN 0.45 0.45
4.0 10 0.45 0.45 10 0.70 0.70
pF
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HV230/232 Electrical Characteristics
AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted)
Characteristics Set Up Time Before LE Rises Time Width of LE Clock Delay Time to Data Out Time Width of CL Set Up Time Data to Clock Hold Time Data from Clock Clock Freq Clock Rise and Fall Times Turn On Time Turn Off Time Sym tSD tWLE tDO tWCL tSU th fCLK tr, tf tON tOFF 0C min 150 150 55 150 15 35 5.0 1.0 5.0 5.0 20 Maximum VSIG Slew Rate dv/dt 20 20 Off Isolation KO -30 -58 Switch Crosstalk Output Switch Isolation Diode Current Off Capacitance SW to GND On Capacitance SW to GND
*Typical values only for HV232
+25C max min 150 150 150 60 150 15 35 5.0 1.0 5.0 5.0 20 20 20 -30 -58 -60 300 -70 300 5.0 25 12 38 17 50 5.0 25 -33 -30 -58 -60 8.0 150 typ* max min 150 150 70 150 20 35
+70C max
Units ns ns
Test Conditions
150
ns ns ns ns
5.0 1.0 5.0 5.0 20 20 20
MHz s s s
50% duty cycle fDATA = fCLK/2 VSIG = VPP -10V, RL = 10K VSIG = VPP -10V, RL = 10K VPP = 160V, VNN = -40V
V/ns
VPP = 100V, VNN = -100V VPP = 40V, VNN = -160V
dB dB dB 300 17 50 mA pF pF
f = 5MHz, 1K//15pF load f = 5MHz, 50 load f = 5MHz, 50 load 300ns pulse width, 2.0% duty cycle 0V, 1MHz 0V, 1MHz
KCR IID CSG(OFF) CSG(ON)
-60
5.0 25
17 50
Electrical Characteristics
AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted)
Characteristics Sym +VSPK Output Voltage Spike -VSPK +VSPK -VSPK +VSPK -VSPK
*Typical values only for HV232
+25C min typ* max 150 150 150 150 150 150
Units
Test Conditions
mV
VPP = 40V, VNN = -160V, RL = 50 VPP = 100V, VNN = -100V, RL = 50 VPP = 160V, VNN = -40V, RL = 50
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Test Circuits
VPP -10V RL VOUT VOUT Open RGND RGND VDD GND 5V VPP VNN VPP VNN VDD GND 5V VPP VNN VPP VNN 10K ISOL
HV230/232
VPP -10V
Open
RGND
VPP VPP VNN VNN
VDD GND
5V
Switch OFF Leakage
DC Offset ON/OFF
TON /TOFF Test Circuit
VIN = 10 VP-P @5MHz VSIG VOUT RL RGND RGND VPP VNN VPP VNN KO = 20Log VDD GND VOUT VIN 5V VPP VNN VPP VNN VDD GND 5V IID VNN
VIN = 10 VP-P @5MHz 50 NC 50
RGND VDD VPP VNN VPP GND VNN KCR = 20Log VOUT VIN 5V
OFF Isolation
Isolation Diode Current
Crosstalk
VOUT VOUT 1000pF
+VSPK VOUT -VSPK 50 RGND
VSIG RGND 1K RL
VPP VNN
VPP VNN
VDD GND
5V
VPP VNN
VPP VNN
VDD GND
5V
Q = 1000pF x VOUT
Charge Injection
Output Voltage Spike
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Logic Timing Waveforms
DN-1 DATA IN
LE
50% 50%
t WLE
HV230/232
DN+1
50%
DN
50%
t
SD
CLOCK
50%
t SU t t h
50%
DD
DATA OUT
50%
t OFF t ON
VOUT OFF
(TYP)
90%
ON
10%
50%
50%
CLR
t WCL
Block Diagram
LATCHES D LE CL DIN
LEVEL SHIFTERS
OUTPUT SWITCHES
SW0
D LE CL CLK D LE CL
SW1
SW2
D LE CL 8 BIT SHIFT REGISTER D LE CL
SW3
SW4
D LE CL
SW5
DOUT
D LE CL
SW6
D LE CL
SW7
VDD
LE
CL
V NN V PP
RGND
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Pin Configurations
HV232 28-Pin J-Lead Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 N/C 10 VPP 11 RGND 12 VNN 13 GND 14 VDD
Package Outlines
HV230/232
Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4
25 26 27 28 1 2 3 4 5
24
23
22
21
20
19 18 17 16 15 14 13 12
6
7
8
9
10
11
Top View 28-Pin J-Lead Package
HV232 48-Pin TQFP Pin Function 1 SW5 2 N/C 3 SW4 4 N/C 5 SW4 6 N/C 7 N/C 8 SW3 9 N/C 10 SW3 11 N/C 12 SW2 13 N/C 14 SW2 15 N/C 16 SW1 17 N/C 18 SW1 19 N/C 20 SW0 21 N/C 22 SW0 23 N/C 24 VPP
Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Function VNN N/C RGND GND VDD N/C N/C N/C DIN CLK LE CLR DOUT N/C SW7 N/C SW7 N/C SW6 N/C SW6 N/C SW5 N/C
Pin 1
Pin 12
Top View 48-Pin TQFP
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HV230/232
HV232GA Package Outline (-BGA)
6.00 0.05 3.00 0.65
A1 CORNER INDEX DIE 4.65
9
2.675
8
765
4
3
21 A B C D E F G H
0.65 0.325
1 A B C
DIE 4.09
2
345
6
7
89
D E F G H
LOT #
AXIS "Y"
DATUM AXIS "X"
Notes: 1. 2. 3. 4. Dimensioning and tolerance per ASME Y14.5M-1994. Do not subject part to ultrasonic cleaning or intense UV. Contact ball position per JESD 95-1, SPP-010. Units are in millimeters.
0.323 0.03
0.05
0.243 0.03 0.99 0.05 Polyimide Tape Adhesive Die Elastomer Lead Elastomer Seal 4 Sides/Edges
ENLARGED VIEW
SIYYWW HV232GA AAAAAAA
5.350 0.05
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-BGA Function Table
Ball Location A4 C3 C4 C5 C6 C7 D1 D3 D4 D5 D6 D7 D9 E1 E3 E4 E5 E6 E7 E9 F3 F4 F5 F6 F7 H4 Function SW1 SW2 SW1 SW0 VPP VNN SW3 SW3 SW2 SW0 RGND GND VDD SW4 SW4 SW5 SW7 LE CLK DIN SW5 SW6 SW7 DOUT CLR SW6
HV230/232
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Pin Configuration
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 Function SW4 SW3 SW3 SW2 SW2 SW1 SW1 SW0 S W0 V PP VNN RGND GND Pin # 14 15 16 17 18 19 20 21 22 23 24 25 26 Function VDD DIN CLK LE bar CLR DOUT SW7 SW7 S W6 SW6 SW5 SW5 SW4
Pad Diagram
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3
HV230/232
2
HV230TA
(Top View)
1
Pad connections are on the backside of the package
Package Dimensions
0.925
6.00 0.10 0.400 1.050 0.100 0.05 0.725
pin 2
0.650
6.00 0.10 4.150 0.35 0.05
pin 1
0.925 0.389 4.550 1.061
0.725 0.35 0.05
Dimensions are in mm
Bottom View
0.750 0.05 0.025 0.025
Dimensions are in mm
Side View
Doc.# DSFP-HV230_HV232
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