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HY57V643220CT(P)
4 Banks x 512K x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V643220CT(P) is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V643220CT(P) is organized as 4banks of 524,288x32. HY57V643220CT(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.)
FEATURES
* * * JEDEC standard 3.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3 Internal four banks operation * * * * * Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst * - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks Burst Read Single Write operation
* *
ORDERING INFORMATION
Part No.
HY57V643220C(L)T(P)-47 HY57V643220C(L)T(P)-5 HY57V643220C(L)T(P)-55 HY57V643220C(L)T(P)-6 HY57V643220C(L)T(P)-7 HY57V643220C(L)T(P)-8 HY57V643220C(L)T(P)-P HY57V643220C(L)T(P)-S
Clock Frequency
212MHz 200MHz 183MHz 166MHz 143MHz 125MHz 100MHz 100MHz
Power
Organization
Interface
Package
Normal/ Low Power
4Banks x 512Kbits x32
LVTTL
400mil 86pin TSOP II
NOTE) Hynix supports lead free part for each speed grade with same specification.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / Feb. 2004 1
HY57V643220CT(P)
PIN CONFIGURATION
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /W E /C A S /R A S /C S NC BA0 BA1 A 1 0 /A P A0 A1 A2 DQM2 VDD NC D Q 16 VSSQ D Q 17 D Q 18 VDDQ D Q 19 D Q 20 VSSQ D Q 21 D Q 22 VDDQ D Q 23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ 15 VSSQ DQ 14 DQ 13 VDDQ DQ 12 DQ 11 VSSQ DQ 10 DQ9 VDDQ DQ8 NC VSS DQM 1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM 3 VSS NC DQ 31 VDDQ DQ 30 DQ 29 VSSQ DQ 28 DQ 27 VDDQ DQ 26 DQ 25 VSSQ DQ 24 VSS
8 6 p in T S O P II 4 0 0 m il x 8 7 5 m il 0 .5 m m p in p itc h
PIN DESCRIPTION
PIN CLK CKE CS BA0, BA1 A0 ~ A10 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE DQM0~3 DQ0 ~ DQ31 VDD/VSS VDDQ/VSSQ NC
Rev. 0.9 / Feb. 2004
2
HY57V643220CT(P)
FUNCTIONAL BLOCK DIAGRAM 512Kbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic & Timer Refresh Counter
CLK
Row Active
512Kx32 Bank 3 Row Pre Decoder 512Kx32 Bank 2 X decoder 512Kx32 Bank 1 X decoder 512Kx32 Bank 0 X decoder DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate
CKE CS RAS CAS WE DQM0 DQM1 DQM2 DQM3
State Machine
Column Active
X decoder
Memory Cell Array
Column Pre Decoder Y decoder
DQ30 DQ31
Bank Select
Column Add Counter
A0 A1 Address buffers A10 BA0 BA1
Address Register Burst Counter
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.9 / Feb. 2004
3
HY57V643220CT(P)
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Unit C C
Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time
TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER
0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 . 10
V V mA W
C Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70C)
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage Input high voltage Input low voltage
VDD, VDDQ VIH VIL
3.0 2.0 VSSQ - 0.3
3.3 3.0 0
3.6 VDDQ + 0.3 0.8
V V V
1,2 1,3 1,4
Note : 1.All voltages are referenced to VSS = 0V 2.VDD/VDDQ(min) is 3.15V for HY57V643220C(L)T-47/5/55/6 3.VIH (max) is acceptable 5.6V AC pulse width with 3ns of duration with no input clamp diodes 4.VIL (min) is acceptable -2.0V AC pulse width with 3ns of duration with no input clamp diodes
AC OPERATING CONDITION (TA=0 to 70C, 3.0V VDD 3.6V, VSS=0V - Note1)
Parameter Symbol Value Unit Note
AC input high / low level voltage Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement
VIH / VIL Vtrip tR / tF Voutref CL
2.4/0.4 1.4 1 1.4 30
V V ns V pF 2
Note : 1.3.15V VDD 3.6V is applied for HY57V643220C(L)T-47/5/55/6 2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Rev. 0.9 / Feb. 2004
4
HY57V643220CT(P)
CAPACITANCE (TA=25xC, f=1MHz, VDD=3.3V)
Parameter Pin Symbol Min Max Unit
Input capacitance
CLK A0 ~ A10, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3
CI1 CI2
2.5 2.5
3.5 3.8
pF pF
Data input / output capacitance
DQ0 ~ DQ31
CI/O
4
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
Vtt=1.4V
RT=500
RT=50
Output
Output 30pF
Z0 = 50
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (DC operating conditions unless otherwise noted)
Parameter Symbol Min. Max Unit Note
Input leakage current Output leakage current Output high voltage Output low voltage
ILI ILO VOH VOL
-1 -1 2.4 -
1 1 0.4
uA uA V V
1 2 IOH = -2mA IOL = +2mA
Note : 1.VIN = 0 to 3.6V, All other pins are not under test = 0V
2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.9 / Feb. 2004
5
HY57V643220CT(P)
DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)
Speed Parameter Symbol Test Condition -47 Burst Length=1, One bank active tRAS tRAS(min), tRP tRP(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = -5 -55 -6 -7 -8 -P -S Unit Note
Operating Current
IDD1
220
200
190
180
170
150
150
150
mA
1
Precharge Standby Current in power down mode
IDD2P IDD2PS
2 mA 2
IDD2N Precharge Standby Current in non power down mode IDD2NS
0.2V
CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or
15 mA
CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK =
10
IDD3P Active Standby Current in power down mode IDD3PS
3 mA 3
IDD3N Active Standby Current in non power down mode
CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or
40 mA
0.2V
IDD3NS
CKE VIH(min), tCK = stable
Input signals are
25
Burst Mode Operating Current
IDD4
tCK tCK(min), tRAS tRAS(min), IOL=0mA All banks active tRRC tRRC(min), 2 banks active
CL=3 CL=2
290 160 260
280 160 250
260 160 235
240 160 220 2
210 160 210
180 160 190
180 160 210
180 mA 1
Auto Refresh Current
IDD5
190
mA
2 3
Self Refresh Current
IDD6
CKE 0.2V
mA 1 4
Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V643220CT(P)-47/5/55/6/7/8/P/S 4.HY57V643220CLT(P)-47/5/55/6/7/8/P/S
Rev. 0.9 / Feb. 2004
6
HY57V643220CT(P)
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-47 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max -5 -55 -6 -7 -8 -P -S Unit Note
CAS Latency = 3 System clock cycle time CAS Latency = 2 Clock high pulse width Clock low pulse width CAS Latency = 3 Access time from clock CAS Latency = 2 Data-out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time CLK to data output in low Z-time CAS Latency = 3 CLK to data output in high Z-time CAS Latency = 2
tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2
4.7 1000 10 1.65 1.65 1.5 1.3 0.8 1.3 0.8 1.3 0.8 1.3 0.8 1 4.5 6 4 6
5 1000 10 2 2 1.5 1.5 1 1.5 1 1.5 1 1.5 1 1 4.5 6 4.5 6
5.5 1000 10 2.25 2.25 2 1.5 1 1.5 1 1.5 1 1.5 1 1 5 6 5 6
6 1000 10 2.5 2.5 2 1.5 1 1.5 1 1.5 1 1.5 1 1 5.5 6 5.5 6
7 1000 10 3 3 2 1.75 1 1.75 1 1.75 1 1.75 1 1 5.5 6 5.5 6
8 1000 -10 3 3 2 2 1 2 1 2 1 2 1 1 6 6 6 6
10 1000 10 3 3 2 2 1 2 1 2 1 2 1 1 6 6 6 6
10 1000 12 3 3 2 2 1 2 1 2 1 2 1 1 6 6 6 6
ns ns ns ns ns 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 3 1 1 1 1 1 1 1 1 1 1
Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v 3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Rev. 0.9 / Feb. 2004
7
HY57V643220CT(P)
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
-47 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max -5 -55 -6 -7 -8 -P -S Unit Note
Operation RAS cycle time Auto Refresh RAS to CAS delay
tRC tRRC tRCD
51.7 51.7 14.1
-
55 55 15
100 K 64
55 55 16.5
100 K 64
60 60 18
100 K 64
63 63 20
100 K 64
64 64 20
100 K 64
70 70 20
100 K 64
70 70 20
100 K 64
ns ns ns
RAS active time
tRAS
37.6
100K
38.7
38.7
42
42
48
50
50
ns
RAS precharge time RAS to RAS bank active delay CAS to CAS delay Write command to data-in delay Data-in to precharge command Data-in to active command DQM to data-out Hi-Z DQM to data-in mask MRS to new command
tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD
14.1 2 1 0 1 4 2 0 2 3 1 1 -
64
15 2 1 0 1 4 2 0 2 3 2 1 1 -
16.5 2 1 0 1 4 2 0 2 3 2 1 1 -
18 2 1 0 1 4 2 0 2 3 2 1 1 -
20 2 1 0 1 4 2 0 2 3 2 1 1 -
20 2 1 0 1 4 2 0 2 3 2 1 1 -
20 2 1 0 1 4 2 0 2 3 2 1 1 -
20 2 1 0 1 4 2 0 2 3 2 1 1 -
ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 1
CAS Latency = 3 tPROZ3 Precharge to data output Hi-Z CAS Latency = 2 tPROZ2 Power down exit time Self refresh exit time Refresh Time tPDE tSRE tREF
Note : 1. A new command can be given tRRC after self refresh exit
Rev. 0.9 / Feb. 2004
8
HY57V643220CT(P)
DEVICE OPERATING OPTION TABLE
HY57V643220C(L)T(P)-47
CAS Latency 212MHz(4.7ns) 200MHz(5ns) 183MHz(5.5ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 3CLKs 3CLKs
3CLKs 3CLKs 3CLKs
37.6ns 38.5ns 38.5ns
12CLKs 11CLKs 10CLKs
3CLKs 3CLKs 3CLKs
4ns 4.5ns 5ns
1.5ns 1.5ns 2ns
HY57V643220C(L)T(P)-5
CAS Latency 200MHz(5ns) 183MHz(5.5ns) 166MHz(6ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 3CLKs 3CLKs
3CLKs 3CLKs 3CLKs
38.5ns 38.5ns 7CLKs
11CLKs 10CLKs 10CLKs
3CLKs 3CLKs 3CLKs
4.5ns 5ns 5.5ns
1.5ns 2ns 2ns
HY57V643220C(L)T(P)-55
CAS Latency 183MHz(5.5ns) 166MHz(6ns) 143MHz(7ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 3CLKs 3CLKs
3CLKs 3CLKs 3CLKs
7CLKs 7CLKs 6CLKs
10CLKs 10CLKs 9CLKs
3CLKs 3CLKs 3CLKs
5ns 5.5ns 5.5ns
2ns 2ns 2ns
HY57V643220C(L)T(P)-6
CAS Latency 166MHz(6ns) 143MHz(7ns) 125MHz(8ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 3CLKs 3CLKs
3CLKs 3CLKs 3CLKs
7CLKs 6CLKs 6CLKs
10CLKs 9CLKs 9CLKs
3CLKs 3CLKs 3CLKs
5.5ns 5.5ns 6ns
2ns 2ns 2.5ns
HY57V643220C(L)T(P)-7
CAS Latency 143MHz(7ns) 125MHz(8ns) 100MHz(10ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 3CLKs 2CLKs
3CLKs 3CLKs 2CLKs
6CLKs 6CLKs 5CLKs
9CLKs 9CLKs 7CLKs
3CLKs 3CLKs 2CLKs
5.5ns 6ns 6ns
2ns 2ns 2ns
HY57V64322C(L)T(P)-8
CAS Latency 125MHz(8ns) 100MHz(10ns) 83MHz(12ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 2CLKs 2CLKs
3CLKs 2CLKs 2CLKs
6CLKs 5CLKs 4CLKs
9CLKs 7CLKs 6CLKs
3CLKs 2CLKs 2CLKs
6ns 6ns 6ns
2ns 2ns 2.5ns
Rev. 0.9 / Feb. 2004
9
HY57V643220CT(P)
HY57V643220C(L)T(P)- P
CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) tRCD tRAS tRC tRP tAC tOH
2CLKs 2CLKs 2CLKs
2CLKs 2CLKs 2CLKs
5CLKs 5CLKs 4CLKs
7CLKs 7CLKs 6CLKs
2CLKs 2CLKs 2CLKs
6ns 6ns 6ns
2ns 2.5ns 2.5ns
HY57V643220C(L)T(P)-S
CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 2CLKs 2CLKs
2CLKs 2CLKs 2CLKs
5CLKs 5CLKs 4CLKs
7CLKs 7CLKs 6CLKs
2CLKs 2CLKs 2CLKs
6ns 6ns 6ns
2ns 2.5ns 2.5ns
Rev. 0.9 / Feb. 2004
10
HY57V643220CT(P)
COMMAND TRUTH TABLE
Command CKEn-1 CKEn CS RAS CAS WE DQM
ADDR
A10/ AP
BA
Note
Mode Register Set No Operation Bank Active Read
H H H H
X X
L H L
L X H L H
L X H H L
L X
X X
OP code X RA L CA H L V V
H H H X X
X X
L L
Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Burst-READ-Single-WRITE Entry Self Refresh1 Exit L H L H Entry Precharge power down Exit L H L H Clock Suspend Entry Exit H L L L H V X V V X H X H X H X X H L L H H X H X H X X H X H X H X X H H H H H H X L L L L H X L H X L L L X L L L X H L H X X H L X V X X X X L L H L X X X L H L L X CA
V H H L X X X X V
A9 Pin High (Other Pins OP code)
X
X
X
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don't care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 0.9 / Feb. 2004
11
HY57V643220CT(P)
PACKAGE INFORMATION
400mil 86pin Thin Small Outline Package
Unit : mm(inch)
22.327(0.8790) 22.149(0.8720)
11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960)
0.150(0.0059) 0.050(0.0020)
1.194(0.0470) 0.991(0.0390)
0.50(0.0197)
0.21(0.008) 0.18(0.007)
5deg 0deg
0.597(0.0235) 0.406(0.0160)
0.210(0.0083) 0.120(0.0047)
Rev. 0.9 / Feb. 2004
12

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