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Integrated Circuit Systems, Inc.
ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FEATURES
* 18 LVCMOS/LVTTL outputs, 7 typical output impedance * Selectable LVCMOS_Clock or CLK0, nCLK0 input pair * LVCMOS_CLK supports the following input types: LVCMOS or LVTTL * CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 200MHz * Output skew: 120ps (maximum) * Part-to-part skew: 850ps (maximum) * Output supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Pin compatible with the MPC940L in single supply applications
GENERAL DESCRIPTION
The ICS83940-02 is a low skew, 1-to-18 Fanout Buffer and a member of the HiPerClock TM S HiPerClockSTM family of High Performance Clock Solutions from ICS. The 83940-02 has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended clock input accepts LVCMOS or LVTTL input levels.The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 18 to 36 by utilizing the ability of the outputs to drive two series terminated lines.
ICS
The ICS83940-02 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83940 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_SEL CLK0 nCLK0 LVCMOS_CLK
PIN ASSIGNMENT
GND VDDO
32 31 30 29 28 27 26 25
0
Q0
Q1
Q2
Q3
Q4
Q5
GND Q0:Q17 GND LVCMOS_CLK CLK_SEL CLK nCLK VDD VDDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q17 Q16 Q15 GND Q14 Q13 Q12 VDDO
24 23 22
Q6 Q7 Q8 VDDO Q9 Q10 Q11 GND
1
ICS83940-02
21 20 19 18 17
32-Lead LQFP Y Pacakge 7mm x 7mm x 1.4mm package body Top View
83940AY-02
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REV. A AUGUST 20, 2004
Integrated Circuit Systems, Inc.
ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Name GND Type Power Input Input Input Input Power Description Output supply ground.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 12, 17, 25 3 4 5 6 7
LVCMOS_CLK CLK_SEL CLK0 nCLK0 VDD
Pulldown Clock input. LVCMOS/LVTTL interface levels. Clock select input. Selects LVCMOS clock input Pulldown when HIGH. Selects CLK0, nCLK0 inputs when LOW. LVCMOS/LVTTL itnerface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input Core supply pin.
Power Output supply pins. 8, 16, 21, 29 VDDO 9, 10, 11, 13, 14, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Clock outputs. 7 typical output impedance. 15, 18, 19, 20, 22, Output Q7, Q6, Q5, Q4, Q3, LVCMOS/LVTTL interface levels. 23, 24, 26, 27, 28, Q2, Q1, Q0 30, 31, 32 NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 5 VDD, VDDO = 3.465V VDD = 3.465V, VDDO = 2.625V VDD, VDDO = 2.625V Test Conditions Minimum Typical 4 12 18 18 51 51 7 12 Maximum Units pF pF pF pF K K
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input CLK_SEL 0 1 CLK0, nCLK0 Selected De-selected Clock LVCMOS_CLK De-selected Selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK_SEL 0 0 0 0 0 0 1 1 LVCMOS_CLK -- -- -- -- -- -- 0 1 CLK0 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 -- -- nCLK0 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 -- -- Outputs Q0:Q17 LOW HIGH LOW HIGH HIGH LOW LOW HIGH Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting Non Inver ting Non Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5% OR 2.5V5%, VDDO = 3V5% OR 2.5V5%, TA = 0 TO 70
Symbol Parameter VDD VDDO IDD IDDO Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 2.375 3.135 2.375 Typical 3.3 2.5 3.3 2.5 Maximum 3.465 2.625 3.465 2.625 25 25 Units V V V V mA mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = 3.3V5% OR 2.5V5%, VDDO = 3V5% OR 2.5V5%, TA = 0 TO 70
Symbol Parameter VIH VIL Input High Voltage Input Low Voltage LVCMOS_CLK CLK_SEL LVCMOS_CLK CLK_SEL IIH IIL VOH VOL Input High Current Input Low Current LVCMOS_CLK, CLK_SEL LVCMOS_CLK, CLK_SEL VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDDO = 3.465V VDDO = 2.625V VDDO = 3.465V or 2.625V Test Conditions Minimum 2 -0.3 -0.3 Typical Maximum VDD + 0.3 1. 3 0.8 150 -5 2.4 1.8 0.5 Units V V V A A V V V
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to VDDO/2. See 3.3V Output Load Test Circuit Diagram.
83940AY-02
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REV. A AUGUST 20, 2004
Integrated Circuit Systems, Inc.
ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Test Conditions CLK0 nCLK0 CLK0 VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.465V or 2.625V, VIN = 0V -5 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5% OR 2.5V5%, VDDO = 3V5% OR 2.5V5%, TA = 0 TO 70
Symbol Parameter IIH Input High Current
IIL VPP
Input Low Current nCLK0
Peak-to-Peak Input Voltage 0.15 Input Common Mode Voltage; GND + 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0 TO 70
Symbol fMAX tpLH tpHL Parameter Output Frequency Propagation Delay; NOTE 1 Propagation Delay; NOTE 1 Test Conditions Minimum Typical 2 2 Maximum 200 3.5 3.5 Units MHz ns ns ps ps ns ns %
tsk(o) Output Skew; NOTE 2, 4 120 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 850 tR Output Rise Time 20% to 80% 350 1050 tF Output Fall Time 20% to 80% 350 1050 odc Output Duty Cycle f 133MHz 45 55 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY-02
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REV. A AUGUST 20, 2004
Integrated Circuit Systems, Inc.
ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Test Conditions Minimum Typical 2 2 Maximum 200 3.5 3.5 Units MHz ns ns ps ps ns ns %
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%; VDDO = 2.5V5%, TA = 0 TO 70
Symbol fMAX tpLH tpHL Parameter Output Frequency Propagation Delay; NOTE 1 Propagation Delay; NOTE 1
tsk(o) Output Skew; NOTE 2, 4 120 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 850 tR Output Rise Time 20% to 80% 350 1050 tF Output Fall Time 20% to 80% 350 1050 odc Output Duty Cycle f 133MHz 45 55 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0 TO 70
Symbol fMAX tpLH tpHL Parameter Output Frequency Propagation Delay; NOTE 1 Propagation Delay; NOTE 1 Test Conditions Minimum Typical 2 2 Maximum 200 3.5 3.5 Units MHz ns ns ps ps ns ns %
tsk(o) Output Skew; NOTE 2, 4 120 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 850 tR Output Rise Time 20% to 80% 350 1050 tF Output Fall Time 20% to 80% 350 1050 odc Output Duty Cycle f 133MHz 40 60 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY-02
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REV. A AUGUST 20, 2004
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ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDO
SCOPE
Qx
VDD, VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V5%
1.25V5%
V DD
V DD VDDO
SCOPE
Qx
nCLK0
V
PP
Cross Points
V
CMR
LVCMOS
GND
CLK0
GND
-1.25V5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
V
PART 1
2
DDx
V
DDx
Qx
Qx
2
V
PART 2
2 tsk(o)
DDx
V
DDx
Qy
Qy
2 tsk(pp)
OUTPUT SKEW
83940AY-02
PART-TO-PART SKEW
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REV. A AUGUST 20, 2004
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ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
LVCMOS_CLK nCLK0
80% 20% tR tF 80%
VDD 2
CLK0
Clock Outputs 20%
Q0:Q17
VDDO 2 t
PD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
V
DDO
Q0:Q17
Pulse Width t
2
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
83940AY-02
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REV. A AUGUST 20, 2004
Integrated Circuit Systems, Inc.
ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
83940AY-02
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REV. A AUGUST 20, 2004
Integrated Circuit Systems, Inc.
ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
83940AY-02
BY
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REV. A AUGUST 20, 2004
Integrated Circuit Systems, Inc.
ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
input signals. In this example, this input is driven by a 3.3V LVPECL driver. For the LVCMOS output, a termination example is shown in this schematic. For more termination approaches, please refer to the LVCMOS Termination Application Note.
APPLICATION SCHEMATIC EXAMPLE
Figure 3 shows an example of ICS83940-02 application schematic. In this example, the device is operated at VCC=3.3V. The decoupling capacitor should be located as close as possible to the power pin. The differential input can accept different type of
VDDO R1 VCC Q3 R3 43 Zo = 50 Ohm 43 Zo = 50
LVCMOS
U1
VCC Zo = 50 Ohm
Zo = 50 Ohm 3.3V LVPECL R4 50 R5 50 C5 0.1u C8 (Option) 0.1u R6 50 VDD
1 2 3 4 5 6 7 8
Q0 Q1 Q2 VDDO Q3 Q4 Q5 GND
32 31 30 29 28 27 26 25
GND GND LVCMOS_CLK CLK_SEL CLK nCLK VDD VDDO Q17 Q16 Q15 GND Q14 Q13 Q12 VDDO
Q6 Q7 Q8 VDDO Q9 Q10 Q11 GND
24 23 22 21 20 19 18 17
VDDO R2 43 Zo = 50
(U1-8)
C1 0.1u
(U1-16)
(U1-21)
(U1-29)
VDD=3.3V VDDO=3.3V
C2 0.1u
C3 0.1u
C4 0.1u
FIGURE 3. APPLICATION
SCHEMATIC EXAMPLE
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9 10 11 12 13 14 15 16
ICS83940-02
REV. A AUGUST 20, 2004
Integrated Circuit Systems, Inc.
ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute) 0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940-02 is: 4270
83940AY-02
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REV. A AUGUST 20, 2004
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ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc
83940AY-02
MINIMUM
NOMINAL 32
MAXIMUM
-0.05 1.35 0.30 0.09
--1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC
1.60 0.15 1.45 0.45 0.20
0.45 0 --
0.60 ---
0.75 7 0.10
REV. A AUGUST 20, 2004
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-026 www.icst.com/products/hiperclocks.html 12
Integrated Circuit Systems, Inc.
ICS83940-02
LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Marking ICS83940AY-02 ICS83940AY-02 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS83940AY-02 ICS83940AY-02T
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83940AY-02
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