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Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
FEATURES
* Twelve, 2-to-1 multiplexers with LVPECL outputs * Selectable differential CLKx, nCLKx input pairs * CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 700MHz * Individual select control for each multiplexer * Select inputs accept LVCMOS / LVTTL levels * Propagation delay: 1.8ns (maximum) * Full 3.3V or mixed 3.3V core/2.5V output supply * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85352I is a 12 bit, 2-to-1 LVPECL Multiplexer and is a member of the HiPerClockS TM HiPerClockSTM family of High Performance Clock Solutions from ICS. Individual input select controls support independent multiplexer operation from a common clock input source. Clock inputs accept most standard differential levels.
ICS
The 85352I is characterized at full 3.3V or mixed 3.3V core/ 2.5V output operating supply modes.
BLOCK DIAGRAM
SEL0:SEL11 CLK0 nCLK0 CLK1 nCLK1
12
PIN ASSIGNMENT
VCCO CLK1 nCLK1 SEL8 SEL7 SEL6 SEL0 SEL1 SEL2 CLK0 nCLK0 VCCO
0
Q0 nQ0
1
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS85352I
Q6 nQ6 Q7 nQ7 Q8 nQ8 Q9 nQ9 Q10 nQ10 Q11 nQ11
VCCO VEE VCC SEL11 SEL10 SEL9 SEL3 SEL4 SEL5 VCC VEE VCCO
0
Q11 nQ11
1
48-Lead TQFP, E-PAD 7mm x 7mm x 1.0mm package body Y Package Top View
85352AYI
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 25, 26 27, 28 29, 30 31, 32 33, 34 35, 36 13, 24, 37, 48 14, 23 15, 22 16, 17, 18, 19, 20, 21, 40, 41, 42, 43, 44, 45 38 39 46 47 NOTE: Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 Q5, nQ5 nQ11, Q11 nQ10, Q10 nQ9, Q9 nQ8, Q8 nQ7, Q7 nQ6, Q6 VCCO VEE VCC SEL5, SEL4, SEL3, SEL9, SEL10, SEL11, SEL8, SEL7, SEL6, SEL0, SEL1, SEL2 CLK1
Output
Differential output pairs. LVPECL interface levels.
Power Power Power
Output supply pins. Negative supply pins. Core supply pins.
Input
Pulldown
Clock select inputs. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VCC/2 default when left floating. nCLK1 Input Pulldown CLK0 Input Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VCC/2 default when left floating. nCLK0 Input Pulldown Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Input
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
TABLE 3. CONTROL INPUT FUNCTION TABLE
SELx 0 1 Selected Clock Inputs CLK0, nCLK0 CLK1, nCLK1
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 27.6C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5%, VCCO = 2.5V TO 3.3V 5%, TA = -40C TO 85C
Symbol VCC VCCO IEE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.475 2.375 Typical 3.3 3.3 Maximum 3.465 3.465 170 Units V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5%, VCCO = 2.5V TO 3.3V 5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current SEL0:SEL11 SEL0:SEL11 SEL0, SEL11 SEL0, SEL11 VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V 5%, VCCO = 2.5V TO 3.3V 5%, TA = -40C TO 85C
Symbol IIH IIL V PP VCMR Parameter Input High Current Input Low Current CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 VEE + 0.5 1.0 VCC - 0.85 Minimum Typical Maximum 150 150 Units A A A A V V
Peak-to-Peak Voltage Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5%, VCCO = 2.5V TO 3.3V 5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO-2V.
TABLE 5A. AC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol fMAX t PD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time 20% to 80% 150 1.0 1.5 Test Conditions Minimum Typical Maximum 700 2.0 180 750 700 Units MHz ns ps ps ps
tsk(o) tsk(pp)
tR / tF
odc Output Duty Cycle f 622MHz 45 55 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VCC = 3.3V5%, VCCO = 2.5V5%, TA = -40C TO 85C
Symbol fMAX t PD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time 20% to 80% 150 1.0 1.5 Test Conditions Minimum Typical Maximum 700 2.0 180 750 700 Units MHz ns ps ps ps
tsk(o) tsk(pp)
tR / tF
odc Output Duty Cycle f 622MHz 45 55 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V 2.8V 0.04V 2V
Qx
V CC, VCCO
SCOPE
V CC VCCO
Qx
SCOPE
LVPECL
nQx
LVPECL
VEE
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
VCC
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx PART 1 Qx
nCLKx
nQy
V
CLKx
PP
Cross Points
V
CMR
PART 2 Qy
tsk(pp)
V EE
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
PART-TO-PART SKEW
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
tsk(o)
OUTPUT SKEW
nCLKx CLKx nQx Qx
tPD
OUTPUT RISE/FALL TIME
nQx Qx
Pulse Width t
PERIOD
odc =
t PW t PERIOD
PROPAGATION DELAY
85352AYI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
3.3V LVPECL OUTPUTS
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50
125 125
FOUT
FIN
Zo = 50
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
F FIN IN
Zo = 50 84 84
FIGURE 2A. LVPECL OUTPUT TERMINATION
85352AYI
FIGURE 2B. LVPECL OUTPUT TERMINATION
REV. A SEPTEMBER 24, 2004
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Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
VCCO=2.5V
2.5V
VCCO=2.5V
R1 250
R3 250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
Zo = 50 Ohm
Zo = 50 Ohm
-
2,5V LVPECL Driv er
2,5V LVPECL Driv er
R2 62.5
R4 62.5
R1 50
R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
85352AYI
BY
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
tions examples are shown in this schematic. Additional termination approaches can be found in the LVPECL Termination Application Note.
APPLICATION SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS85352I application schematic. In this example, the device is operated at VCC=3.3V. The decoupling capacitor should be located as close as possible to the power pin. For the LVPECL output drivers, only two terminaCLK1 nCLK1 SEL8 SEL7 SEL6 SEL0 SEL1 SEL2 CLK0 nCLK0
Zo = 50
+
Zo = 50 Vcc = Vcco = 3.3V
-
R2 50 48 47 46 45 44 43 42 41 40 39 38 37 U1 85352 Vcco nCLK0 CLK0 SEL2 SEL1 SEL0 SEL6 SEL7 SEL8 nCLK1 CLK1 Vcco R3 50
R1 50
1 2 3 4 5 6 7 8 9 10 11 12
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Vcco Vee Vcc SEL5 SEL4 SEL3 SEL9 SEL10 SEL11 Vcc Vee Vcco
Q6 nQ6 Q7 nQ7 Q8 nQ8 Q9 nQ9 Q10 nQ10 Q11 nQ11
36 35 34 33 32 31 30 29 28 27 26 25
Vcco = 3.3V
R4 133 Zo = 50
R6 133
13 14 15 16 17 18 19 20 21 22 23 24
+
SEL5 SEL4 SEL3 SEL9 SEL10 SEL11
Zo = 50
-
VCC
(U1-15)
(U1-22)
VCC0
(U1-13)
(U1-24)
(U1-37)
(U1-48)
R5 82.5 C7 .1uF
R7 82.5
C1 10uf
C3 .1uF
C4 .1uF
C1 10uf
C2 0.1uF
C5 .1uF
C6 .1uF
Optional Termination
FIGURE 5. ICS85352I APPLICATION SCHEMATIC
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85352I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85352I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 170mA = 589.1mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 12 * 30mW = 360mW
Total Power_MAX (3.465V, with all outputs switching) = 589.1mW + 360mW = 949.1mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 22.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.949W * 22.6C/W = 106.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
48-PIN TQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 27.6C/W
200
22.6C/W
500
20.7C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A SEPTEMBER 24, 2004
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3. Calculations and Equations.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 48 LEAD TQFP, E-PAD
JA by Velocity (Linear Feet per Minute)
0 200
22.6C/W
500
20.7C/W
Multi-Layer PCB, JEDEC Standard Test Boards
27.6C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85352I is: 2252
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
48L TQFP, E-PAD
EXPOSED PAD
PACKAGE OUTLINE - Y SUFFIX
O1.5
FOR
X 0.1 DEPTH
D2
E2
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b D D1 D2 E E1 E2 e L ccc 0.45 --0.05 0.95 0.17 BBC MINIMUM NOMINAL 48 --1.00 0.22 9.00 BASIC 7.00 BASIC 4.00 BASIC 9.00 BASIC 7.00 BASIC 4.00 BASIC 0.5 BASIC 0.60 -0.75 0.08 1.20 0.15 1.05 0.27 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026 REV. A
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS85352I
12 BIT, 2-TO-1, 3.3V/2.5V LVPECL CLOCK MULTIPLEXER
Package 48 Lead TQFP, E-PAD 48 Lead TQFP, E-PAD on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85352AYI ICS85352AYIT Marking ICS85352AYI ICS85352AYI
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85352AYI
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REV. A SEPTEMBER 24, 2004

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