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Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
FEATURES
* 16 LVCMOS/LVTTL outputs (4 banks of 4 outputs) * Selectable differential CLK1, nCLK1 or LVCMOS clock input * CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * CLK0 supports the following input types: LVCMOS, LVTTL * Maximum output frequency: 250MHz * Independent bank control for /1 or /2 operation * Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation * Asynchronous clock enable/disable * Output skew: 170ps (maximum) * Bank skew: 30ps (maximum) * Part-to-part skew: 750ps (maximum) * 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply * 0C to 85C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS87016 is a low skew, 1:16 LVCMOS/ LVTTL Clock Generator and is a member of the HiPerClockSTM HiPerClockS family of High Performance Clock Solutions. The device has 4 banks of 4 outputs and each bank can be independently selected for /1 or /2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines.
ICS
The divide select inputs, DIV_SELA:DIV_SELD, control the output frequency of each bank. The output banks can be independently selected for /1 or /2 operation. The bank enable inputs, CLK_ENA:CLK_END, support enabling and disabling each bank of outputs individually. The CLK_ENA:CLK_END circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. The master reset input, nMR/OE, resets the /1//2 flip flops and also controls the active and high impedance states of all outputs. This pin has an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. The ICS87016 is characterized to operate with the core at 3.3V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and part-to-part skew characteristics make the 87016 ideal for those clock applications demanding well-defined performance and repeatability.
BLOCK DIAGRAM
nMR/OE
D
PIN ASSIGNMENT
1 0
D 4
LE
QA3 VDDOA QA2 GND QA1 VDDOA QA0 GND CLK_SEL nCLK1 CLK1 VDD
CLK0 CLK1 nCLK1 CLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD
0 1
/1 /2
4
QA0:QA3 VDD CLK0 DIV_SELA QB0:QB3 DIV_SELB DIV_SELC DIV_SELD CLK_ENA QC0:QC3 CLK_ENB CLK_ENC CLK_END nMR/OE QD0:QD3 GND
1 0
LE
D
1 0
LE
4
D 1
LE
4
CLK_ENA CLK_ENB CLK_ENC CLK_END
0
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS87016
GND QB0 VDDOB QB1 GND QB2 VDDOB QB3 GND QC0 VDDOC QC1
48-Pin LQFP 7mm x 7mm x 1.4mm body package Y Package Top View
GND QC2 VDDOC QC3 GND QD0 VDDOD QD1 GND QD2 VDDOD QD3
87016AY
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REV. A DECEMBER 10, 2004
1
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
Type Power Input Input Input Input Input Input Input Input Input Input Power Output Power Output Power Output Power Output Power Input Input Input Description Core supply pins. Pulldown LVCMOS / LVTTL clock input. Controls frequency division for Bank A outputs. Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs Pullup LVCMOS / LVTTL interface levels.. Controls frequency division for Bank C outputs. Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank D outputs. Pullup LVCMOS / LVTTL interface levels. Output enable for Bank A outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank B outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank C outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank D outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Master reset. When LOW, resets the /1//2 flip flops and sets the Pullup outputs to high impedance. LVCMOS / LVTTL interface levels. Power supply ground. Bank D outputs. LVCMOS / LVTTL interface levels. Output Bank D power supply pins. Bank C outputs. LVCMOS / LVTTL interface levels. Output Bank C power supply pins. Bank B outputs. LVCMOS / LVTTL interface levels. Output Bank B power supply pins. Bank A outputs. LVCMOS / LVTTL interface levels. Output Bank A power supply pins. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. Pulldown When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 48 2 3 4 5 6 7 8 9 10 11 12, 16, 20, 24, 28, 32, 36, 40, 44 13, 15, 17, 19 14, 18 21, 23, 25, 27 22, 26 29, 31, 33, 35 30, 34 37, 39, 41, 43 38, 42 45 46 47 Name VDD CLK0 DIV_SELA DIV_SELB DIV_SELC DIV_SELD CLK_ENA CLK_ENB CLK_ENC CLK_END nMR/OE GND QD3, QD2, QD1, QD0 VDDOD QC3, QC2, QC1, QC0 VDDOC QB3, QB2, QB1, QB0 VDDOB QA3, QA2, QA1, QA0 VDDOA CLK_SEL nCLK1 CLK1
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87016AY
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REV. A DECEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum Typical 4 51 VDD, VDDOx = 3.465V; NOTE 1 VDD = 3.465, VDDOx = 2.625V; NOTE 1 VDD = 3.465, VDDOx = 1.89V; NOTE 1 7 18 20 30 Maximum Units pF K pF pF pF
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP CPD ROUT Parameter Input Capacitance Input Pullup Resistor Power Dissipation Capacitance (per output) Output Impedance
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, and VDDOD.
TABLE 3. FUNCTION TABLE
nMR/OE 0 1 1 1 Inputs CLK_ENx X 1 1 0 DIV_SELx X 0 1 X Bank X Hi Z Active Active Low Outputs Qx Frequency N/A fIN/2 fIN N/A
87016AY
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REV. A DECEMBER 10, 2004
3
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C
Symbol Parameter Core Supply Voltage VDD VDDOx IDD IDDOx Output Supply Voltage; NOTE 1 Power Supply Current Output Supply Current; NOTE 2 Test Conditions Minimum 3.135 3.135 2.375 1.71 Typical 3.3 3.3 2.5 1.8 Maximum 3.465 3.465 2.625 1.89 100 15 Units V V V V mA mA
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, and VDDOD. NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, and IDDOD.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C
Symbol Parameter VIH Input High Voltage DIV_SELA:DIV_SELD, CLK_ENA:CLK_END, nMR/OE, CLK_SEL CLK0 DIV_SELA:DIV_SELD, CLK_ENA:CLK_END, nMR/OE, CLK_SEL CLK0 CLK_ENA:CLK_END, DIV_SELA:DIV_SELD, nMR/OE CLK0, CLK_SEL CLK_ENA:CLK_END, DIV_SELA:DIV_SELD, nMR/OE CLK0, CLK_SEL Test Conditions Minimum Typical 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDOx = 3.3V 5%; NOTE 2 VOH Output High Voltage; NOTE 1 VDDOx = 2.5V 5%; NOTE 2 VDDOx = 1.8V 5%; NOTE 2 IOH = -2mA VDDOx = 3.3V 5%; NOTE 2 VOL Output Low Voltage; NOTE 1 VDDOx = 2.5V 5%; NOTE 2 VDDOx = 1.8V 5%; NOTE 2 IOL = 2mA Output Tristate Current Low -5 -150 -5 2.6 1.8 VDD - 0.45 0.5 0.5 0.45 Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V V V V V V A A
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
IOZL
Output Tristate Current High 5 IOZH NOTE 1: Outputs terminated with 50 to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuit. NOTE 2: VDDOx denotes VDDOA, VDDOB, VDDOC and VDDOD.
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REV. A DECEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions nCLK1 CLK1 nCLK1 CLK1 VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDOX = 3.3V5%, TA = 0C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise/Fall Time; NOTE 6 Output Duty Cycle Output Enable Time; NOTE 6 20% to 80% f < 175MHz f 175MHz 200 45 40 2.8 2.9 Measured on the Rising Edge Measured on the Rising Edge 3.2 3.4 Test Conditions Minimum Typical Maximum 250 3.7 3.9 30 150 750 700 55 60 10 Units MHz ns ns ps ps ps ps % % ns ns
t sk(b) t sk(o) t sk(pp)
tR / tF odc tEN
Output Disable Time; NOTE 6 10 tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VDDOX/2. NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
87016AY
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REV. A DECEMBER 10, 2004
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Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDOX = 2.5V5%, TA = 0C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise/Fall Time; NOTE 6 Output Duty Cycle Output Enable Time; NOTE 6 20% to 80% f < 175MHz f 175MHz 200 45 40 2.9 3 Measured on the Rising Edge Measured on the Rising Edge 3.3 3.5 Test Conditions Minimum Typical Maximum 250 3.8 4 30 160 750 700 55 60 10 Units MHz ns ns ps ps ps ps % % ns ns
t sk(b) t sk(o) t sk(pp)
tR / tF odc tEN
Output Disable Time; NOTE 6 10 tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VDDOX/2. NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
87016AY
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REV. A DECEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V5%, VDDOX = 1.8V5%, TA = 0C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise/Fall Time; NOTE 6 Output Duty Cycle Output Enable Time; NOTE 6 20% to 80% f < 175MHz f 175MHz 200 45 40 3.1 3.1 Measured on the Rising Edge Measured on the Rising Edge 3.8 3.8 Test Conditions Minimum Typical Maximum 250 4.5 4.5 30 170 750 700 55 60 10 Units MHz ns ns ps ps ps ps % % ns ns
t sk(b) t sk(o) t sk(pp)
tR / tF odc tEN
Output Disable Time; NOTE 6 10 tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VDDOX/2. NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
87016AY
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REV. A DECEMBER 10, 2004
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Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDOx
SCOPE
Qx
V DD VDDOx
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.40.9V +0.9V5%
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
V DD VDDOx
SCOPE
Qx
VDD
LVCMOS
GND
nCLK1
V
CLK1
PP
Cross Points
V
CMR
-0.9V5%
GND
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1 Qx
V
DDOX
V
Qx
DDOX
2
2
PART 2 Qy
V
DDOX
V
Qy
DDOX
2 tsk(pp)
2 tsk(o)
PART-TO-PART SKEW
87016AY
OUTPUT SKEW
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REV. A DECEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
QX0:QX3
VDDOX 2
80% 20%
tR
80% 20% tF
QX0:QX3
tsk(b)
VDDOX 2
Clock Outputs
BANK SKEW (where X denotes outputs in the same bank)
OUTPUT RISE/FALL TIME
V
DDOX
QAx, QBx, QCx, QDx
2
CLK0
VDD 2
Pulse Width t
PERIOD
nCLK1 CLK1
odc =
t PW t PERIOD
QAx,QBx, QCx, QDx
VDDOX 2
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
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tPD
REV. A DECEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD VCC R1 1K CLK + V_REF V_REF C1 C1 0.1u 0.1uF R2 1K nCLK
Single Ended Clock Input CLK_IN
R1 1K
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87016AY
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REV. A DECEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 2B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 2D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
87016AY
BY
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REV. A DECEMBER 10, 2004
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Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
are shown in the application section of this data sheet. The single ended input CLK0 is driven by a 7 LVMCOS driver through series termination. The ICS87016 outputs are LVCMOS drivers. Series termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note.
SCHEMATIC EXAMPLE
Figure 3 shows an application schematic example of the ICS87016. This schematic provides examples of input and output handling. The differential CLK1/nCLK1 input can accept various types of differential signal. This example shows the ICS87016 input driven by a 3.3V LVPECL driver. Additional examples for the input driven by other types of drivers
3.3V
Zo = 50
R1
~43
Zo = 50
Zo = 50
LVPECL
VDDO
R3 50
R4 50
VDD
R5 50
RS
43
Zo = 50 Ohm
LVCMOS
Ro+Rs=50 Ohm
Logic Input Pin Examples
VCC
1 2 3 4 5 6 7 8 9 10 11 12
VDD CLK1 nCLK1 CLK_SEL GND QA0 VDDOA QA1 GND QA2 VDDOA QA3
Ro=7 Ohm
48 47 46 45 44 43 42 41 40 39 38 37
3.3V
Set Logic Input to '1'
VCC
Set Logic Input to '0'
RU1 1K
RU2 SPARE
U1 ICS87016
To Logic Input pins
RD1 SPARE
RD2 1K
To Logic Input pins
R2 ~43
Zo = 50
VDD=3.3V
VDD
VDDO
(U1-1)
(U1-48)
(U1-14)
(U1-18)
(U1-22)
13 14 15 16 17 18 19 20 21 22 23 24
QD3 VDDOD QD2 GND QD1 VDDOD QD0 GND QC3 VDDOC QC2 GND
VDD CLK0 DIV_SELA DIV_SELB DIV_SELC DIV_SELD CLK_ENA CLK_ENB CLK_ENC CLK_END nMR/OE GND
GND QB0 VDDOB QB1 GND QB2 VDDOB QB3 GND QC0 VDDOC QC1
36 35 34 33 32 31 30 29 28 27 26 25
VDDO=3.3V, 2.5V or 1.8V
(U1-26)
(U1-30)
(U1-34)
(U1-38)
(U1-42)
C9 0.1u
C10 0.1u
C1 0.1u
C2 0.1u
C3 0.1u
C4 0.1u
C5 0.1u
C6 0.1u
C7 0.1u
C8 0.1u
FIGURE 3. APPLICATION SCHEMATIC EXAMPLE
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REV. A DECEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
48 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87016 is: 2034
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Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
48 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
87016AY
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REV. A DECEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87016AY ICS87016AYT Marking ICS87016AY ICS87016AY Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 85C 0C to 85C
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87016AY www.icst.com/products/hiperclocks.html REV. A DECEMBER 10, 2004
15
Integrated Circuit Systems, Inc.
ICS87016
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev A A
Table T5A, T5B, T5C
Page 6, 7, 8
T5A & T5B A
6&7 12 1 12
Description of Change AC Characteristics Table - corrected the first line in the Notes section, from "All parameters measured at 150MHz..." to 250MHz. Revised par t description title from "Differential-to-LVCMOS Clock Generator" to "LVCMOS Clock Generator". AC Characteristics Table - switched prop delay values for CLK0 and CLK1, nCLK1. Added Differential Clock Input Interface section. Updated format. Modified Block Diagram, corrected latch block. Added Schematic Example
Date 7/31/02 8/9/02
5/05/03
A A
6/4/03 12/10/04
87016AY
www.icst.com/products/hiperclocks.html
16
REV. A DECEMBER 10, 2004

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