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Integrated Circuit Systems, Inc.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
FEATURES
* 1 /2 differential 2.5V/3.3V LVPECL / ECL output * 1 CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 500MHz * Maximum input frequency: 1GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input * Part-to-part skew: 400ps (maximum) * Propagation delay: 1.6ns (maximum) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.8V * -40C to 85C ambient operating temperature * Compatible to part number MC100EP32
GENERAL DESCRIPTION
The ICS87332I-01 is a high performance /2 Differential-to-2.5V/3.3V ECL/LVPECL Clock HiPerClockSTM Generator and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels The ICS87332I-01 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS87332I-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
,&6
BLOCK DIAGRAM
CLK nCLK /2 Q nQ
PIN ASSIGNMENT
MR CLK nCLK nc 1 2 3 4 8 7 6 5 Vcc Q nQ VEE
MR
ICS87332I-01
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
87332AMI-01
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REV. A AUGUST 12, 2002
Integrated Circuit Systems, Inc.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
Type Input Input Input Unused Power Output Power Description Master reset. When LOW, outputs are enabled. When HIGH, Pulldown divider is reset forcing Q output LOW and nQ output HIGH. LVCMOS / LVTTL interface level. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. No connect. Negative supply pin. Differential output pair. LVPECL interface levels. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6, 7 8 Name MR CLK nCLK nc VEE Q, nQ VCC
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
CLK
MR
Q
FIGURE 1 - TIMING DIAGRAM
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REV. A AUGUST 12, 2002
Integrated Circuit Systems, Inc.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 112.7C/W (0 lfpm) -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, V O Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40C TO 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 3.8 30 Units V mA
TABLE 3B. LVCMOS DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current MR MR MR MR VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V A A
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.8V VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V VCC = 3.8V, VIN = 0V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
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REV. A AUGUST 12, 2002
Integrated Circuit Systems, Inc.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.65 Typical Maximum VCC - 1.0 VCC - 1.7 0.9 Units V V V
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40C TO 85C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40C TO 85C
Symbol fMAX Parameter Input Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise Time Output Fall Time 20% to 80% 20% to 80% 200 200 1GHz 1.1 1.4 Test Conditions Minimum Typical Maximum 1 1.6 400 700 700 51 Units GHz ns ps ps ps %
tPD tsk(pp)
tR tF
odc Output Duty Cycle 49 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
87332AMI-01
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REV. A AUGUST 12, 2002
Integrated Circuit Systems, Inc.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE = -1.8V to -0.375V
OUTPUT LOAD TEST CIRCUIT
V CC
nCLK V CLK
PP
Cross Points
V
CMR
VEE
DIFFERENTIAL INPUT LEVEL
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REV. A AUGUST 12, 2002
Integrated Circuit Systems, Inc.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
nQx PART 1 Qx
nQy PART 2 Qy
tsk(pp)
PART-TO-PART SKEW
80%
80% V
SWING
20% Clock Inputs and Outputs t t
20%
R
F
INPUT
AND
OUTPUT RISE
AND
FALL TIME
nCLK CLK
nQ Q
t
PD
PROPAGATION DELAY
nQ Q
Pulse Width t t odc = t
PW PERIOD
PERIOD
odc & tPERIOD
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87332AMI-01
REV. A AUGUST 12, 2002
Integrated Circuit Systems, Inc.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87332-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS87332-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 30mA = 114mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power_MAX (3.8V, with all outputs switching) = 114mW + 30.2mW = 144.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.144W * 103.3C/W = 99.9C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE qJA
FOR
8-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A AUGUST 12, 2002
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 2.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 2 - LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC _MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. A AUGUST 12, 2002
Integrated Circuit Systems, Inc.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87332I-01 is: 383
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REV. A AUGUST 12, 2002
Integrated Circuit Systems, Inc.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - M SUFFIX
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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REV. A AUGUST 12, 2002
Integrated Circuit Systems, Inc.
ICS87332I-01
/2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
Marking 332AI01 332AI01 Package 8 lead SOIC 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87332AMI-01 ICS87332AMI-01T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87332AMI-01
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