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Integrated Circuit Systems, Inc.
ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
FEATURES
* Fully integrated PLL * 14 LVCMOS/LVTTL outputs; (12) clock, (1) feedback, (1) sync * Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs * CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 8.33MHz to 125MHz * VCO range: 200MHz to 480MHz * Output skew: 550ps (maximum) * Cycle-to-cycle jitter: 100ps (typical) * Full 3.3V supply voltage * -40C to 85C ambient operating temperature * Pin compatible with MPC973 * Compatible with PowerPCTM and PentiumTM Microprocessors
GENERAL DESCRIPTION
,&6
HiPerClockSTM
The ICS87973I is a LVCMOS/LVTTL clock generator and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87973I has three selectable inputs and provides 14 LVCMOS/LVTTL outputs.
The ICS87973I is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 8.33MHz to125MHz. The input frequency range is 5MHz to 120MHz. The ICS87973I also has a QSYNC output which can by used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications: 1. System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2. Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. 3. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay.
PIN ASSIGNMENT
EXT_FB GNDO GNDO GNDO VDDO VDDO QB0 QB1 QB2 QB3 QFB VDD
FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 GNDO VCO_SEL
39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 56 78 9 10 11 12 13 25 24 23 22 21
FSEL_FB0
FSEL_FB1 QSYNC GNDO QC0 VDDO QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO INV_CLK
ICS87973I
20 19 18 17 16 15 14
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
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1
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2
PLL_SEL
REF_SEL
CLK_SEL
CLK0
CLK1
CLK
nCLK
REV. D JULY 9, 2003
VDDA
Integrated Circuit Systems, Inc.
ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
BLOCK DIAGRAM
VCO_SEL PLL_SEL REF_SEL CLK nCLK CLK0 CLK1 CLK_SEL EXT_FB 0 1 PHASE DETECTOR LPF VCO 1 0 0 1
D Q
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QA0 QA1 QA2 QA3
D
Q
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QB0 QB1 QB2 QB3
FSEL_FB2
nMR/OE POWER-ON RESET /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 2 2 FSEL_B0:1 FSEL_C0:1 FSEL_FB0:2 2 3 DATA GENERATOR SYNC PULSE 0 /2 1
D
Q
SYNC FRZ
QC0 QC1 QC2 QC3 QFB
D
Q
SYNC FRZ SYNC FRZ
FSEL_A0:1
/4, /6, /8, /10
D
Q
D
Q
SYNC FRZ
QSYNC
FRZ_CLK OUTPUT DISABLE CIRCUITRY 12
FRZ_DATA
INV_CLK
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Integrated Circuit Systems, Inc.
ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
nMR/OE
SIMPLIFIED BLOCK DIAGRAM
FSEL_A[0:1]
CLK nCLK CLK0 CLK1 CLK_SEL REF_SEL
/2 1 0 1 VCO RANGE 200MHz - 480MHz 0 0 1 /1 1 0 PLL
2
FSEL_ A1 A0 00 01 10 11
QAx /4 /6 /8 /12
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QA0 QA1 QA2 QA3
EXT_FB
FSEL_B[0:1]
2
VCO_SEL
PLL_SEL
FSEL_ B1 B0 00 01 10 11
QBx /4 /6 /8 /10
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QB0 QB1 QB2 QB3
FSEL_C[0:1]
2
FSEL_ C1 C0 00 01 10 11
QCx /2 /4 /6 /8
QC0
SYNC FRZ
QC1 QC2 QC3
0
SYNC FRZ SYNC FRZ
1 INV_CLK FSEL_FB[0:2]
3
FSEL_ FB2 FB1 FB0 QFB 0 0 0 /4 0 0 1 /6 0 1 0 /8 0 1 1 /10 1 0 0 /8 1 0 1 /12 1 1 0 /16 1 1 1 /20
FRZ_CLK FRZ_DATA
OUTPUT DISABLE CIRCUITRY SYNC FRZ
QFB
QSYNC
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Integrated Circuit Systems, Inc.
ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Power Input Input Input Input Pullup Pullup Pullup Pullup Description Power supply ground. Master reset and output enable. When HIGH, enables the outputs. When LOW, resets the outputs to tristate and resets output divide circuitry. Enables and disables all outputs. LVCMOS / LVTTL interface levels. Clock input for freeze circuitry. LVCMOS / LVTTL interface levels. Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels. Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels. Selects between the PLL and reference clocks as the input to the output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL. LVCMOS / LVTTL interface levels. Selects between CLK0 or CLK1 and CLK, nCLK inputs. When HIGH, selects CLK, nCLK. When LOW, selects CLK0 or CLK1. LVCMOS / LVTTL interface levels. Clock select input. Selects between CLK0 and CLK1 as phase detector reference. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Reference clock inputs. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 26, 27 Name GNDI nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2, FSEL_FB1, FSEL_FB0 PLL_SEL
6
Input
Pullup
7
REF_SEL
Input
Pullup
8 9, 10 11 12 13 14 15, 24, 30, 35, 39, 47, 51 16, 18, 21, 23 17, 22, 33, 37, 45, 49 19, 20 25 28 29 31 32, 34, 36, 38 40, 41 42, 43 44, 46, 48, 50 52
CLK_SEL CLK0,CLK1 CLK nCLK VDDA INV_CLK GNDO QC3, QC2, QC1, QC0 VDDO FSEL_C1, FSEL_C0 QSYNC VDD QFB EXT_FB QB3, QB2, QB1, QB0 FSEL_B1, FSEL_B0 FSEL_A1, FSEL_A0 QA3, QA2, QA1, QA0 VCO_SEL
Input Input Input Input Power Input Power Output Power Input Output Power Output Input Output Input Input Output Input
Pullup Pullup
Pullup Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Analog supply pin. Inver ted clock select for QC2 and QC3 outputs. Pullup LVCMOS / LVTTL interface levels. Power supply ground. Bank C clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins. Pullup Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams. LVCMOS / LVTTL interface levels. Core supply pins. Feedback clock output. LVCMOS / LVTTL interface levels. Pullup Extended feedback. LVCMOS / LVTTL interface levels. Bank B clock outputs.7 typical output impedance. LVCMOS / LVTTL interface levels. Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. Bank A clock outputs.7 typical output impedance. LVCMOS / LVTTL interface levels. Selects VCO. When HIGH, selects VCO / 1. When LOW, selects VCO / 2. LVCMOS / LVTTL interface levels.
Pullup Pullup
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
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ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions Minimum Typical 4 51 VDD, VDDA, VDDO = 3.465V 5 7 18 12 Maximum Units pF K pF
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP / RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup/Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance
TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs FSEL_A1 0 0 1 1 FSEL_A0 0 1 0 1 Outputs QA /4 /6 /8 /12 0 0 1 1 Inputs FSEL_B1 FSEL_B0 0 1 0 1 Outputs QB /4 /6 /8 /10 0 0 1 1 Inputs FSEL_C1 FSEL_C0 0 1 0 1 Outputs QC /2 /4 /6 /8
TABLE 3B. FEEDBACK CONFIGURATION SELECT FUNCTION TABLE
Inputs FSEL_FB2 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 Outputs QFB /4 /6 /8 /10 /8 /12 /16 /20
TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE
Control Pin VCO_SEL REF_SEL CLK_SEL PLL_SEL nMR/OE INV_CLK Logic 0 VCO/2 CLK0 or CLK1 CLK0 BYPASS PLL Master Reset/Output Hi Z Non-Inver ted QC2, QC3 Logic 1 VCO CLK, nCLK CLK1 Enable PLL Enable Outputs Inver ted QC2, QC3
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LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
1:1 MODE
fVCO
QA QC QSYNC
2:1 MODE
QA QC QSYNC
3:1 MODE
QC(/2) QA(/4) QSYNC
3:2 MODE
QC(/2) QA(/8) QSYNC
4:1 MODE
QC(/2) QA(/8) QSYNC
4:3 MODE
QA(/6) QC(/8) QSYNC
6:1 MODE
QA(/12) QC(/2) QSYNC
FIGURE 1. TIMING DIAGRAMS
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ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 42.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current All power pins Test Conditions Minimum 3.135 2.935 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 225 20 Units V V V mA mA
NOTE: Special thermal handling may be required in some configurations.
TABLE 4B. DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VIH VIL IIN VOH VOL VPP VCMR Input High Voltage Input Low Voltage Input Current Output High Voltage Output Low Voltage Peak-to-Peak Input Voltage; NOTE 1, 2 Common Mode Input Voltage; NOTE 1, 2 IOH = -20mA IOL = 20mA CLK, nCLK CLK, nCLK 0.3 VDD - 2V 2.4 0.5 1 VDD - 0.6V Test Conditions Minimum 2 Typical Maximum 3.6 0.8 120 Units V V A V V V V
NOTE 1: Common mode voltage is defined as VIH. NOTE 2. For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Test Conditions Minimum Typical Maximum Units CLK0, CLK1, 120 MHz fIN Input Frequency CLK, nCLK; NOTE 1 FRZ_CLK 20 MHz NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * Feedback Divide" is in the VCO range of 200MHz to 480MHz. Symbol Parameter
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ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions /2 Minimum Typical Maximum 125 120 80 60 -70 -130 -225 130 70 -25 330 270 175 550 100 200 480 10 0.8V to 2V 0.15 1.2 Units MHz MHz MHz MHz ps ps ps ps ps MHz mS ns ps ns ns
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter
fMAX
Output Frequency
/4 /6 /8
t(O)
CLK0 Static Phase Offset; CLK1 NOTE 1 CLK, nCLK Output Skew; NOTE 2 Cycle-to-Cycle Jitter; NOTE 3, 4 PLL VCO Lock Range PLL Lock Time; NOTE 3 Output Rise/Fall Time; NOTE 3 Output Pulse Width Output Enable Time; NOTE 3 Output Disable TIme; NOTE 3
QFB /8 In Frequency = 50MHz
tsk(o) tjit(cc)
fVCO tLOCK tR / tF tPW tPZL, tPZH tPLZ, tPHZ
tPERIOD/2 - 750 tPERIOD/2 500 tPERIOD/2 + 750 2 2 10 8
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% VDD VDD, VDDA, VDDO
SCOPE
nCLK
Qx
V
PP
LVCMOS
GND
Cross Points
V
CMR
CLK
GND -1.65V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
V
Qx
DDO
V QA0:QA3, QB0:QB3, QC0:QC3, QSYNC, QFB
DDO
V
DDO
V
DDO
2
2
n
2
2
V
Qy
DDO
2 tsk(o)
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
OUTPUT SKEW
nCLK
CYCLE-TO-CYCLE JITTER
VDD
CLK
CLK0, CLK1
VDD
EXT_FB
2
EXT_FB
t(O)
t(O) mean = Static Phase Offset
(where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
(where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
STATIC PHASE OFFSET (DIFFERENTIAL)
STATIC PHASE OFFSET (LVCMOS)
2.4V 0.5V tR
2.4V 0.5V tF
QA0:QA3, QB0:QB3, QC0:QC3, QSYNC, QFB
Clock Outputs
OUTPUT RISE/FALL TIME
87973DYI
tPW & tPeriod
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t(O)
t(O) mean = Static Phase Offset
VDDO 2 t PW
t PERIOD
odc =
t PW t PERIOD
VDDO 2
tcycle
tcycle n+1
2
VDD 2
VDDO 2
REV. D JULY 9, 2003
Integrated Circuit Systems, Inc.
ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER APPLICATION INFORMATION
USING THE OUTPUT FREEZE CIRCUITRY
OVERVIEW
To enable low power states within a system, each output of ICS87973I (Except QC0 and QFB) can be individually frozen (stopped in the logic "0" state) using a simple serial interface to a 12 bit shift register. A serial interface was chosen to eliminate the need for each output to have its own Output Enable pin, which would dramatically increase pin count and package cost. Common sources in a system that can be used to drive the ICS87973I serial interface are FPGA's and ASICs. FRZ_CLK signal. To place an output in the freeze state, a logic "0" must be written to the respective freeze enable bit in the shift register. To unfreeze an output, a logic "1" must be written to the respective freeze enable bit. Outputs will not become enabled/ disabled until all 12 data bits are shifted into the shift register. When all 12 data bits are shifted in the register, the next rising edge of FRZ_CLK will enable or disable the outputs. If the bit that is following the 12th bit in the register is a logic "0", it is used for the start bit of the next cycle; otherwise, the device will wait and won't start the next cycle until it sees a logic "0" bit. Freezing and unfreezing of the output clock is synchronous (see the timing diagram below). When going into a frozen state, the output clock will go LOW at the time it would normally go LOW, and the freeze logic will keep the output low until unfrozen. Likewise, when coming out of the frozen state, the output will go HIGH only when it would normally go HIGH. This logic, therefore, prevents runt pulses when going into and out of the frozen state.
PROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze Data) and FRZ_CLK (Freeze Clock). Each of the outputs which can be frozen has its own freeze enable bit in the 12 bit shift register. The sequence is started by supplying a logic "0" start bit followed by 12NRZ freeze enable bits. The period of each FRZ_DATA bit equals the period of the FRZ_CLK signal. The FRZ_DATA serial transmission should be timed so the ICS87973I can sample each FRZ_DATA bit with the rising edge of the
FRZ_DATA
rt Sta it B
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3 QSYNC
FRZ_CLK
FIGURE 2A. FREEZE DATA INPUT PROTOCOL
Qx FREEZE Internal
Qx Internal
Qx Out
FIGURE 2B. OUTPUT DISABLE TIMING
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FRZ Latched
FRZ Clocked
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ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87973I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F V DDA .01F 10 F 10
FIGURE 3. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 4 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
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LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87973I is: 8364
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LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 E E1 e L q ccc 0.45 0 --0.05 1.35 0.22 0.09 BCC MINIMUM NOMINAL 52 --1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC ---0.75 7 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Marking ICS87973DYI ICS87973DYI Package 52 Lead LQFP 52 Lead LQFP on Tape and Reel Count 160 per tray 500 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS87973DYI ICS87973DYIT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87973DYI
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LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
REVISION HISTORY SHEET
Rev A A B
Table T1
Page 4 2
Description of Change Pin Description Table - added pins 20 and 21. Block Diagram - added missing dividers to the Data Generator. DC Characteristics table - updated VCMR values from GND + 1.5V min., VDD max. to VDD - 2V min., VDD - 0.6V max. Pin Description Table - corrected CLK Type to read Pullup from Pulldown. Revised Package Drawing. Corrected Package Dimensions table to correspond with the Package Drawing. Added LVTTL to title. Corrected Package Outline to correspond with the Package Dimensions table. Pin Characteristics - changed the CPD limit from 25pF typical to 18pf max. Power Supply Table - changed the IDD limit from 215mA max. to 225mA max. Application Information: Added sections, "Power Supply Filtering Techniques" and "Wiring the Differential Level..." Added "Differential Clock Input Interface" section. Pin Characteristics - changed CIN from 4pF max. to 4pF typical. Corrected Freeze Data labeling on Figure 2A. Power Supply Table - changed VDDA minimum from 3.135V to 2.935V. Pin Characteristics Table - added Pullup/Pulldown to pin 12, nCLK. Pin Characteristics Table - added to ROUT 5 min. and 12 max.
Date 9/9/02 10/18/02 10/23/02
T4B T1
7 4 12 1
B
T8
11/18/02
B T2 T4A C
12 5 7 11 12 5 10 7 4 5
12/10/02
3/21/03
C D D
T2 T4A T1 T2
5/7/03 6/27/03 7/9/03
87973DYI
www.icst.com/products/hiperclocks.html
16
REV. D JULY 9, 2003

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