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Integrated Circuit Systems, Inc.
TM
ICS9217
Preliminary Product Preview
667MHz Direct Rambus Clock Generator II
General Description
The ICS9217 is a high-speed clock generator providing a differential clock source up to 667 MHz for a 2nd generation Direct RambusTM memory system. It includes signals to synchronize the Direct RambusTM Channel clock to an external system clock. The ICS9217 provides two power management mechanisms. A "Clock Stop" mode is controlled by the OE# pin. When OE# is asserted, the internal clock circuitry remains running, but the CLK_T/CLK_C output buffers are disabled. A "Power Down" mode, controlled by the PWRDN# pin turns off the internal circuitry and drives both clock outputs to ground. The internal resistor divider networks are also disconnected to further reduce power consumption. The ICS9217 is Spread Spectrum compatible.
Features
* * * * * * * Up to 667 MHz differential clock source for 2nd generation Direct RambusTM system Supports 4, 6, 8, and 16/3 frequency multipliers Cycle-to-cycle jitter less than +/- 20 ps Supports both systems needing to synchronize RambusTM channel clocks to system clocks and system that do not require such synchronization Power management features Space saving 24-pin SSOP package Flexible input voltage levels
Block Diagram
OE# PWRDN# MODE(1:0)
Pin Configuration
VDDIR 1 REFIN 2 AVDD 3 AGND 4 GND 5 PCLKM 6 24 MODE0 23 MODE1 22 VDD 21 GND
ICS9217
20 CLK_T 19 N/C 18 CLK_C 17 GND 16 VDD 15 FS0 14 FS1 13 GND
REFIN
CLK_T CLK_C
SYNCLKN 7 GND 8 VDD 9 VDDIPD 10 OE# 11 PWRDN# 12
FS(1:0) PCLKM SYNCLKN
24-Pin SSOP
0816B--10/06/03 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9217
Preliminary Product Preview
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME PIN TYPE VDDIR REFIN AVDD AGND GND PCLKM SYNCLKN GND VDD VDDIPD OE# PWRDN# GND FS1 FS0 VDD GND CLK_C N/C CLK_T GND VDD MODE1 MODE0 PWR IN PWR PWR PWR IN IN PWR PWR PWR IN IN PWR IN IN PWR PWR OUT N/C OUT PWR PWR IN IN DESCRIPTION Reference supply for REFIN input Reference Clock input 3.3V Analog Power pin for Core PLL Analog Ground pin for Core PLL Ground pin. Phase detector input Phase detector input Ground pin. Power supply, nominal 3.3V Reference supply for PCLKM, SYNCLKN, OE#, MODE(0:1) Active low input for enabling outputs. 1 = tri-state outputs, 0 = enable outputs Active-low input pin used to place the device into a low power state. The VCO is stopped, the resistor divider networks are disconnected and the outputs are both low, when in power down mode. Ground pin. Frequency select pin. Frequency select pin. Power supply, nominal 3.3V Ground pin. "Complimentary" clock of differential pair No Connection. "True" clock of differential pair Ground pin. Power supply, nominal 3.3V Mode Select Pin Mode Select Pin
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ICS9217
Preliminary Product Preview
Output Frequency for FS(0:1) and REFIN Inputs
Inputs FS0 FS1 50.00 0 0 Reserved 0 1 300.00 1 0 266.67 1 1 400.00 NOTE 1. Output Frequency = (REFIN x A)/B 2. Device operation not guaranteed at settings in shaded areas Fdbk/Prescaler A B 4 1 6 1 16 3 8 1 REFIN (MHz) 66.67 83.375 266.68 333.50 400.02 500.25 355.57 444.67 533.36 667.00 100.00 400.00 600.00 533.33 800.00 133.00 532.00 798.00 709.33 1064.00
Bypass and Test Mode Selection
Mode Normal Bypass Test Output Test (OE) MODE0 0 1 1 0 MODE1 0 0 1 1 CLK_T PA CLK PLL CLK REFIN Hi-Z CLK_C PA CLK# PLL CLK# REFIN# Hi-Z
NOTES 1. PA CLK is clock from phase aligner 2. PLL CLK is the full speed PLL clock with the Phase Aligner bypassed
Power Management Modes
State PWRDN# OE# CLK_T CLK_C Normal 1 1 PA CLK PA CLK# Clock Stop 1 0 VX,STOP VX,STOP Powerdown 0 X GND GND NOTES 1. PA CLK = clock from phase aligner
PLL Divider Selection for 600/667 MHz DRCG MULT0 MULT1 A B 0 0 4 1 0 1 6 1 1 1 8 1 1 0 16 3
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ICS9217
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage (AVDD, VDD, VDDIR, VDDIPD) GND - 0.5 V to 4.0 V Logic Input Voltage1
........................
GND - 0.5 V to VDDX + 0.5 V 0C to +70C
Ambient Operating Temperature . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only, and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum operating conditions for extended periods may affet product reliability.
Electrical Characteristics - DC
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/- 0.5% or 3.45V +/- 0.15 V (unless otherwise stated) Min Max Parameters Symbol 3.3 3.6 Supply Voltage (fout = 667 MHz) VDD1 3.135 3.465 Supply Voltage (fout <= 600 MHz) VDD2 1.235 3.6 Input supply reference for REFIN VDD,IR Input supply reference for PWRDN# inputs Operating Supply Current (fout = 667 MHz) Operating Supply Current (fout = 660 MHz) Operating Supply Current (fout = 533 MHz) Operating Supply Current (fout = 400 MHz) Output disabled operating supply current 2 Reference current in Power Down mode Reference current in Normal or Output Disabled mode Power down operating supply current 3 Input capacitance at PCLKM, SYNCLKN & REFIN Input Capacitance matching at PCLKM & SYNCLKN Input capacitance at CMOS pins Input (CMOS) signal low voltage Input (CMOS) signal high voltage REFIN input low voltage REFIN input high voltage Input signal low voltage for MULT(1:0) Input signal high voltage for MULT(1:0) Input signal low voltage for PWRDN# and OE# inputs Input signal high voltage for PWRDN# and OE# inputs Input leakage current Output crossing-point voltage Difference in Output crossing-point voltage Output voltage during Clk Stop Output voltage swing (peak to peak, single ended)1 Output high voltage Output low voltage Output low voltage Difference in Zout between CLK_T and CLK_C Output leakage current during Hi-Z Output leakage current during Clock stop Notes: 1. VCOS = VOH - VOL
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Unit V V V V mA mA mA mA mA A mA A pF pF pF VDD VDD VDDIR VDDIR VDDIPD VDDIPD VDDIPD VDDIPD A V V V V V V V A A
VDDI,PD I DD1 IDD2 IDD3 IDD4 I DDPD I REF,PWDN I REF,NORM I DDPD CIN,PD CIN,PD CIN,CMOS VIL VIH VIL,R VIH,R VIL,M VIH,M VIL,PD VIH,PD I IN VX VX VX,STOP VCOS VOH VOL VOL ZO IOZ I OZ,STOP
1.235
2.625 250 210 200 170 50 50 2 200 7 0.5 10 0.3 0.3 0.3 0.3 50 1.675 |0.2| 1.675 0.8 2.35 10 50 500
0.7 0.7 0.7 0.7 -50 1.3 0 1.1 0.6 0.9 0.9 -
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ICS9217
Preliminary Product Preview
Electrical Characteristics - AC 667 MHz Operation
TA = 0 - 70C; Supply Voltage VDD = 3.45 V +/- 0.15 V (unless otherwise stated) Parameters Symbol REFIN Input cycle time tCYCLE,IN 2 tJ,IN Input cycle-to-cycle Jitter Input duty cycle over 10,000 cycles DCIN f M,IN Input modulation frequency 3 Modulation index for triangular modulation3 Modulation index for non-triangular modulation3 Phase detector input cycle time at PCLKM & SYNCLKN Phase detector input cycle-to-cycle jitter Initial phase error at phase detector inputs Phase detector input duty cycle over 10k cycles Input slew rate (measured at 20%-80% of input voltage) for PCLKM, SYNCLKN & REFIN Clock cycle time Total jitter over 1 - 6 cycles (667 MHz) Phase aligner phase step size (CLK_T/CLK_C) Phase Detector phase error between PCLKM and SYNCLKN (rising edges)5 PLL output phase error when tracking spread spectrum clocks Output cycle-to-cycle duty cycle error Output rise & fall times ( measured at 20%-80% of output voltage) Difference between rise and fall times on a single device(20%-80%) Cycle-to-Cycle jitter during Test Mode Average output duty cycle over 10,000 cycles during Test Mode Output rise & fall times ( measured at 20%-80% of output voltage) during Test Mode
4
PM,IN t CYCLE,PD tJPD tERR,INT DCIN,PD tISR tCYCLE tJ tSTEP tERR,PD t ERR,SSC tDC,ERR t CR,tCF tCR,CF tJT DCT tCRT,tCFT
Min 7.5 40% 30 24 -0.5 25% 1 1.5 -20 2 -100 -100 -20 140 45% 250
Max 201 |200| 60% 33 0.6 0.5 100 3.5 0.5 75% 4 2.5 20 100 100 20 285 100 500 55% 900
Unit ns ps tCYCLE kHz % % ns ns tCYCLE,PD tCYCLE,PD V/ns ns ps ps ps ps ps ps ps ps tCYCLE,PD ps
NOTES 1. Maximum REFIN cycle time does not apply to Test Mode 2. REFIN jitter is measured at (nominal VDD,IR)/2 and is the absolute value of the worst case +/- deviation, not the peak-to-peak jitter. 3. If input modulation is used; input modulation is not required. 4. The input jitter for the Phase Detector inputs is defined from cycle-to-cycle on one input signal (not between the two Phase Detector inputs), and is measured at (nominal V DDI,PD)/2. 5. Phase detector phase error is a component specification and not an external distributed loop in a system. This specification applies to average phase error and does not include input clock jitter.
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ICS9217
Preliminary Product Preview
Electrical Characteristics - AC 600MHz or Less Operation
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/- 5% (unless otherwise stated) Parameters Symbol REFIN Input cycle time tCYCLE,IN 2 tJ,IN Input cycle-to-cycle Jitter Input duty cycle over 10,000 cycles DCIN f M,IN Input modulation frequency 3 Modulation index for triangular modulation3 Modulation index for non-triangular modulation3 Phase detector input cycle time at PCLKM & SYNCLKN Phase detector input cycle-to-cycle jitter4 Initial phase error at phase detector inputs Phase detector input duty cycle over 10k cycles Input slew rate (measured at 20%-80% of input voltage) for PCLKM, SYNCLKN & REFIN Clock cycle time Total jitter over 1 - 6 cycles (<= 600 MHz) Phase aligner phase step size (CLK_T/CLK_C) Phase Detector phase error between PCLKM and SYNCLKN (rising edges)5 PLL output phase error when tracking spread spectrum clocks Output cycle-to-cycle duty cycle error Output rise & fall times ( measured at 20%-80% of output voltage) Difference between rise and fall times on a single device(20%-80%) Cycle-to-Cycle jitter during Test Mode Average output duty cycle over 10,000 cycles during Test Mode Output rise & fall times ( measured at 20%-80% of output voltage) during Test Mode PM,IN tCYCLE,PD tJPD tERR,INT DCIN,PD tISR tCYCLE tJ tSTEP tERR,PD tERR,SSC tDC,ERR tCR,tCF tCR,CF tJT DCT tCRT,tCFT Min 7.5 40% 30 24 -0.5 25% 1 1.667 -20 2 -100 -100 -20 140 45% 250 Max 201 |200| 60% 33 0.6 0.5 100 3.5 0.5 75% 4 2.5 20 100 100 20 285 100 500 55% 900 Unit ns ps tCYCLE kHz % % ns ns tCYCLE,PD tCYCLE,PD V/ns ns ps ps ps ps ps ps ps ps tCYCLE,PD ps
NOTES 1. Maximum REFIN cycle time does not apply to Test Mode 2. REFIN jitter is measured at (nominal V DD,IR)/2 and is the absolute value of the worst case +/- deviation, not the peak-to-peak jitter. 3. If input modulation is used; input modulation is not required. 4. The input jitter for the Phase Detector inputs is defined from cycle-to-cycle on one input signal (not between the two Phase Detector inputs), and is measured at (nominal VDDI,PD)/2. 5. Phase detector phase error is a component specification and not an external distributed loop in a system. This specification applies to average phase error and does not include input clock jitter.
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ICS9217
Preliminary Product Preview
VDD turn-on M L Test N B K VDD turn-on Powerdown A
VDD turn-on G J
Normal
F E VDD turn-on Clk Stop C H
D
Figure 1: DRCG State Diagram
PWRDNB tPOWERUP CLK/CLKB tPOWERDN
Figure 2: PWRDNB Transition Timings
MULT0, MULT1 tMULT CLK/CLKB
Figure 3: MULT Transition Timings
S0 and/or S1 tCTL CLK/CLKB
Figure 4: S0 and S1 Transition Timings
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ICS9217
Preliminary Product Preview
tON tCLKON tCLKSETL
tSTOP
STOPB
tCLKOFF
CLK/CLKB
output clock not spec'd glitches ok
clock enabled and glitch free
clock output settled within 50ps of the phase before disabled
Figure 5: StopB Transition Timings
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ICS9217
Preliminary Product Preview
State Transition Latency Specifications
Transition From To Transition Latency Symbol A Powerdown Powerdown Powerdown VDD ON VDD ON VDD ON Normal Normal tPOWERUP Max 3 ms Time from PWRDNB ing tDISTLOCK). to CLK/CLKB output settled (excludDescription
C
Clk Stop
tPOWERUP
3 ms
Time from PWRDNB until the internal PLL and clock has turned ON and settled. Time from PWRDNB ing tDISTLOCK). to CLK/CLKB output settled (exclud-
K
Test
tPOWERUP
3 ms
G
Normal
tPOWERUP
3 ms
Time from when VDD is applied and settled until CLK/CLKB output is settled (excluding tDISTLOCK). Time from when VDD is applied and settled until the internal PLL and clock has turned ON and settled. Time from when VDD is applied and settled until the output clock has turned ON and settled. Time from when MULT0 or MULT1is changed until CLK/CLKB output has re-settled (excluding tDISTLOCK). Time from STOPB clock edges. until CLK/CLKB provides glitch-free
H
Clk Stop
tPOWERUP
3 ms
M
Test
tPOWERUP
3 ms
J
Normal
tMULT
1 ms
E
Clk Stop
Normal
tCLKON
10 ns
E
Clk Stop
Normal
tCLKSETL
20 cycles 5 ns 3 ms
Time from STOPB to CLK/CLKB output settled to within 50ps of the phase before CLK/CLKB was disabled. Time from STOPB to CLK/CLKB output disabled.
F L
Normal Test
Clk Stop Normal
tCLKOFF tCTL
Time from when S0 or S1 is changed until CLK/CLKB output has re-settled (excluding tDISTLOCK). Time from when S0 or S1 is changed until CLK/CLKB output has re-settled (excluding tDISTLOCK). Time from PWRDNB to the device in Powerdown Mode.
N
Normal
Test
tCTL
3 ms
B,D
Normal or Clk Stop
Powerdown
tPOWERDN
1 ms
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ICS9217
Preliminary Product Preview
Recommended Layout
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Capacitor Values: C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic Connections to VDD:
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ICS9217
Preliminary Product Preview
SYMBOL A A1 A2 B C D E e H L N S
X
COMMON DIMENSIONS MIN. NOM. MAX. .061 .064 .068 .004 .006 .0098 .055 .058 .061 .008 .010 .012 .0075 .008 .0098 SEE VARIATIONS .150 .155 .157 .025 BSC .230 .236 .244 .010 .013 .016 SEE VARIATIONS SEE VARIATIONS 0 5 8 0.85 0.93 .100
VARIATIONS AA AB AC AD MIN. .189 .337 .337 .386
D NOM. .194 .342 .342 .391 MAX. .196 .344 .344 .393 MIN. .0020 .0500 .0250 .0250
S NOM. .0045 .0525 .0275 .0280 MAX. .0076 .0550 .0300 .0300 N 16 20 24 28
150 mil SSOP Package
Diminisions are in inches
Ordering Information
ICS9217yF - LF
Example:
ICS XXXX y F - PPLF T
Designation for tape and reel packaging Lead Free (if required) Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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