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ILC6383
1-Cell to 3-Cell Boost with True Load Disconnect, 3.3V, 5V or Adjustable Output
Features
* * * * * * * * * * * * * 0.9V to 6V input voltage Guaranteed start up in PWM at 0.9V input Synchronous rectification requires no external diode True load disconnect from battery input in shutdown Up to 75mA at 3.3V and 40mA at 5V from 1V input Up to 375mA at 3.3V and 160mA at 5V from 3V input Peak efficiency > 90% 1A battery input current in shutdown (with VOUT = 0V) Internal Oscillator frequency: 300kHz to 15% ILC6383: Fixed 3.3V or 5V output ILC6383-ADJ: Adjustable output to 6V maximum Low battery detector with 100ms transient rejection delay Powergood output flag when VOUT is in regulation
Description
The ILC6383 series of step-up DC-DC converters operate from 1-cell to 3-cell input. They are direct replacement for ILC6382, in applications where SYNC pin is not used. The PFM or PWM operating mode is user selectable through SEL pin connected to ground or left open, respectively. The choice should be dependent upon the current to be delivered to the load: PFM is recommended for input voltage higher than 1.5V and loads below 100mA, while PWM is recommended for more than 50mA load current In shutdown mode, the device allows true load disconnect from battery input. Designed for wireless communications applications, the oscillator frequency is set at 300kHz with no harmonics at sub 20kHz audio band or at 455kHz IF band. Internal synchronous rectification and externally selectable PFM/PWM mode of operation allows the selection of the best efficiency at light or full load. The ILC6383 is capable of delivering 75mA at 3.3V output from a single cell input. The ILC6383-XX offers 3.3V or 5V fixed output voltage while the ILC6383-ADJ allows adjustable output voltage to 6V maximum. Output voltage accuracy is 2% over specified temperature range. Additional features include power good output (POK) and an internal low battery detector with 100ms transient rejection delay. The device will reject low battery input transients under 100ms in duration. The ILC6383 series is available in a space saving eight lead micro SOP (MSOP-8) package.
Applications
* Cellular Phones, Pagers * Palmtops, PDAs and portable electronics * High efficiency 1V step up converters
Typical Applications
C IN
47F
L + 15H 1 2 R5 3
ILC6383-XX
LX VIN LBI/SD SEL VOUT GND LBO POK
C IN
47F
L + 15H 1 2 R5 3
ILC6383-ADJ
LX VIN LBI/SD SEL VOUT GND
8 7 6 5
+
VIN
1 to 3-cell
47F COUT
VOUT VIN
1 to 3-cell
8 7 6 5
+
C OUT
47F
VOUT
ON OFF
R6 4
Low Battery Detector Output Power Good Output
R1 LBO
V FB
ON OFF R6
4
MSOP-8 PWM PFM PWM PFM
R2 MSOP-8 VOUT = 1.25 (1+R1/R2)
Figure 1: ILC6383CIR-XX
Figure 2: ILC6383CIR-ADJ
Rev. 1.2
(c)2001 Fairchild Semiconductor Corporation
ILC6383
Pin Assignments
LX V IN LB/SD SEL
1 2 3 4 8 7 6 5
V OUT GND LBO POK
LX V IN LB/SD SEL
1 2 3 4
8 7 6 5
V OUT GND LBO V FB
MSOP
(TOP VIEW)
MSOP
(TOP VIEW)
ILC6383CIR-XX
ILC6383CIR-ADJ
Pin Definitions
Pin Number 1 2 3 Pin Number LX VIN LBI/SD Connect directly to battery Low battery detect input and shutdown. Low battery detect threshold is set with this pin using a potential divider. If this pin is pulled to logic low then the device will shutdown. A low logic level signal applied to this pin selects PFM operation mode. If the pin is left open or high logic level is applied, PWM mode is selected. This open drain output pin will go high when output voltage is within regulation, 0.92*VOUT(NOM) < VOUT < 0.98*VOUT(NOM) Pin Description Inductor input. Inductor L connected between this pin and the battery
4 5
SEL POK (ILC6383CIR-XX)
VFB This pin sets the adjustable output voltage via an external resistor divider (ILC6383CIR-ADJ) network. The formula for choosing the resistors is shown in the "Applications Information" section. 6 7 8 LBO GND VOUT This open drain output will go low if the battery voltage is below the low battery threshold set at pin 3 Connect this pin to the battery and system ground This is the regulated output voltage
Absolute Maximum Ratings (Note 1)
Parameter Voltage on VOUT pin Voltage on LBI, Sync, LBO, POK, VFB, LX and VIN pins Peak switch current on LX pin Current on LBO pin Continuous total power dissipation at 85C Short circuit current Operating ambient temperature Maximum junction temperature Storage temperature Lead temperature (soldering 10 sec.) Package thermal resistance JA Symbol VOUT ILX ISINK(LBO) PD ISC TA TJ(MAX) Tstg Ratings -0.3 to 7 -0.3 to 7 1 5 315 Internally protected (1 sec. duration) -40 to 85 150 -40 to 125 300 206 Units V V A mA mW A C C C C C/W
(c)2001 Fairchild Semiconductor Corporation
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ILC6383
Electrical Characteristics ILC6383CIR-33 in PFM mode (SEL in LOW state)
Unless otherwise specified all limits are at VIN = VLBI = 2.4V, IOUT = 1mA TA = 25C. Test circuit figure 1. The * denotes specifications which apply over the specified operating temperature range. (Note 2) Parameter Output Voltage Output Current Load Regulation No Load Battery Input Current Efficiency Symbol VOUT * IOUT VOUT VOUT IIN(no load) VIN = 2.0V, VOUT = VOUT(NOM) 4% 1mA < IOUT < 20mA IOUT = 0mA IOUT = 20mA, VIN = 2.0V Conditions Min. 3.168 3.135 Typ. 3.3 100 1 250 88 Max. 3.432 3.465 Units V mA % A %
Electrical Characteristics ILC6383CIR-33 in PWM mode (SEL in open)
Unless otherwise specified all limits are at VIN = VLBI = 2.4V, IOUT = 50mA TA = 25C. Test circuit figure 1. The * denotes specifications which apply over the specified operating temperature range. (Note 2) Parameter Output Voltage Output Current Symbol VOUT(NOM) * IOUT VIN = 0.9V, VOUT = VOUT(NOM) 4% VIN = 1.2V, VOUT = VOUT(NOM) 4% VIN = 2.4V, VOUT = VOUT(NOM) 4% VIN = 3.0V, VOUT = VOUT(NOM) 4% VIN = 1.2V, 0mA < IOUT < 50mA VIN = 1.2V, IOUT = 0mA IOUT = 20mA, VIN = 2.0V Conditions Min. 3.234 3.201 Typ. 3.300 50 75 200 375 1.5 250 90 Max. 3.366 3.399 Units V mA
Load Regulation No Load Battery Input Current Efficiency
VOUT VOUT I GND
% A %
General Electrical Characteristics for all voltage versions.
Unless otherwise specified all limits are at VIN = VLBI = 2.4V and TA = 25C. Test circuits figure 1 and figure 2 for ILC6383CIR-XX and ILC6383CIR-ADJ respectively. The * denotes specifications which apply over the specified operating temperature range. (Note 2) Parameter LBO Output Voltage Low LBO Output Leakage Current Shutdown Input Voltage Low Shutdown Input Voltage High SEL Input Voltage High SEL Input Voltage Low Symbol VLBO(low) ILBO(hi) VSD(low) VSD(hi) VSEL(hi) VSEL(low) Conditions ISINK = 2mA, open drain output, VLBI = 1V VLBO = 5V * * * * * * 1 1.5 0.4 1 Min. Typ. Max. 0.4 2 0.4 6 Units V A V V V V
(c)2001 Fairchild Semiconductor Corporation
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ILC6383
General Electrical Characteristics (continued)
Parameter POK Output Voltage Low POK Output Voltage High POK Output Leakage Current POK Threshold POK Hysteresis Symbol VPOK(low) VPOK(hi) IL(POK) VTH(POK) VHYST * 1.225 1.212 Force 6V at pin 5 Conditions ISINK = 2mA, open drain output * * * 0.92 x VOUT 0.95 x VOUT 50 1.250 1.275 1.288 Min. Typ. Max. 0.4 6 2 0.98 x VOUT Units V V A V mV V
Feedback Voltage VFB (ILC6383CIR-ADJ only) VOUT(ADJ) min VIN = 0.9V, IOUT = 50mA Output Voltage Adjustment Range VOUT(ADJ) max VIN = 3V, IOUT = 50 mA (ILC6383CIR-ADJ only) Minimum Startup Voltage Input Voltage Range Battery Input Current in Load Disconnect Mode Switch on resistance Oscillator Frequency LBI Input Threshold Input Leakage Current LBI Hold Time VIN(start) VIN IIN(SD) IOUT = 10mA, PWM mode VOUT = VOUT(nominal) 4% IOUT = 10mA (Note 3) VLBI/SD < 0.4V, VOUT = 0V (short circuit) N-Channel MOSFET P-Channel MOSFET
2.5V 6V
V
* 0.9 1
0.9
1 VOUT(nominal) + +0.5V
V V A
* *
1
10
Rds(on) fOSC VREF
400 750 * 255 1.175 1.150 300 1.250 345 1.325 1.350 200 100 120
m kHz
* I LEAK tHOLD(LBI) Pins LB/SD, SEL and VFB, (Note 4) (Note 5)
nA mS
Notes: 1. Absolute maximum ratings indicate limits which, when exceeded, may result in damage to the component. Electrical specifications do not apply when operating the device outside its rated operating conditions. 2. Specified min/max limits are production tested or guaranteed through correlation based on statistical control methods. Measurements are taken at constant junction temperature as close to ambient as possible using low duty pulse testing. 3. VOUT(NOM) is the nominal output voltage at IOUT = 50mA in PWM mode. 4. Guaranteed by design. 5. In order to get a valid low-battery-output (LBO) signal, the input voltage must be lower than the low-battery-input (LBI) threshold for a duration greater than the low battery hold time (thold(LBI)). This feature eliminates false triggering due to voltage transients at the battery terminal.
(c)2001 Fairchild Semiconductor Corporation
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ILC6383
Applications Information
The ILC6383 performs boost DC-DC conversion by controlling the switch element as shown in the simplified circuit in figure 3 below.
300kHz. The control circuitry varies the power being delivered to the load by varying the on-time, or duty cycle, of the switch SW1 (see fig. 5). Since more on-time translates to higher current build-up in the inductor, the maximum duty cycle of the switch determines the maximum load current that the device can support. The minimum value of the duty cycle determines the minimum load current that can maintain the output voltage within specified values. There are two key advantages of the PWM type controllers. First, because the controller automatically varies the duty cycle of the switch's on-time in response to changing load conditions, the PWM controller will always have an optimized waveform for a steady-state load. This translates to very good efficiency at high currents and minimal ripple on the output. Ripple is due to the output cap constantly accepting and storing the charge received from the inductor, and delivering charge as required by the load. The "pumping" action of the switch produces a sawtooth-shaped voltage as seen by the output. The other key advantage of the PWM type controllers is that the radiated noise due to the switching transients will always occur at the (fixed) switching frequency. Many applications do not care much about switching noise, but certain types of applications, especially communication equipment, need to minimize the high frequency interference within their system as much as possible. Using a boost converter requires a certain amount of higher frequency noise to be generated; using a PWM converter makes that noise highly predictable thus easier to filter out.
Figure 3: Basic Boost Circuit When the switch is closed, current is built up through the inductor. When the switch opens, this current has to go somewhere and is forced through the diode to the output. As this on and off switching continues, the output capacitor voltage builds up due to the charge it is storing from the inductor current. In this way, the output voltage gets boosted relative to the input. In general, the switching characteristic is determined by the output voltage desired and the current required by the load. Specifically the energy transfer is determined by the power stored in the coil during each switching cycle. PL = (tON, VIN) Synchronous Rectification The ILC6383 also uses a technique called "synchronous rectification" which removes the need for the external diode used in other circuits. The diode is replaced with a second switch or in the case of the ILC6383, an FET as shown in figure 4 below.
V IN LX
SW1 SW2
+
PFM Mode Operation
For low loads the ILC6383 can be switched to PFM, or Pulse Frequency Modulation, technique at low currents. This technique conserves power loss by only switching the output if the current drain requires it. As shown in the figure 5, the waveform actually skips pulses depending on the power needed by the output. This technique is also called "pulse skipping" because of this characteristic. In the ILC6383, the switchover from PWM to PFM mode is determined by the user to improve efficiency and conserve power
ILC6383
V OUT
PWM/PFM CONTROLLER
POK GND
SHUTDOWN CONTROL
+ V REF DELAY
LBO
SEL
LB/SD
Switch Waveform
Figure 4: Simplified ILC6382 block diagram The two switches now open and close in opposition to each other, directing the flow of current to either charge the inductor or to feed the load. The ILC6383 monitors the voltage on the output capacitor to determine how much and how often to drive the switches.
V SET
V OUT
PWM Mode Operation
The ILC6383 uses a PWM or Pulse Width Modulation technique. The switches are constantly driven at typically
(c)2001 Fairchild Semiconductor Corporation
Figure 5: PFM Waveform
5
ILC6383
The Dual PWM/PFM mode architecture was designed specifically for applications such as wireless communications, which need the spectral predictability of a PWM-type DCDC converter, yet also need the highest efficiencies possible, especially in Standby mode.
2 VIN ILC6383 Shutdown R5 3 LBI/SD R6 6 + DELAY 100ms
3.3V R PU
LBO
Other Considerations
The other limitation of PWM techniques is that, while the fundamental switching frequency is easier to filter out since it's constant, the higher order harmonics of PWM will be present and may have to be filtered out, as well. Any filtering requirements, though, will vary by application and by actual system design and layout, so generalizations in this area are difficult, at best. However, PWM control for boost DC-DC conversion is widely used, especially in audio-noise sensitive applications or applications requiring strict filtering of the high frequency components.
1.25V Internal Reference 7 GND
Figure 6: Low Battery Detector
The output of the low battery detector is an open drain capable of sinking 2mA. A 10k pull-up resistor is recommended on this output.
Low Battery Detector
The ILC6383's low battery detector is a based on a CMOS comparator. The negative input of the comparator is tied to an internal 1.25V (nominal) reference, V REF. The positive input is the LBI/SD pin. It uses a simple potential divider arrangement with two resistors to set the LBI threshold as shown in Figure 6. The input bias current of the LBI pin is only 200nA. This means that the resistor values R1 and R2 can be set quite high. The formula for setting the LBI threshold is: VLBI = VREF x (1+R5/R6) Since the LBI input current is negligible (<200nA), this equation is derived by applying voltage divider formula across R6. A typical value for R6 is 100k. R5 = 100k x [(VLBI/VREF) -1], where VREF = 1.25V (nom.) The LBI detector has a built in delay of 120ms. In order to get a valid low-battery-output (LBO) signal, the input voltage must be lower than the low-battery-input (LBI) threshold for a duration greater than the low battery hold time (thold(LBI)) of 120msec. This feature eliminates false triggering due to voltage transients at the battery terminal caused by high frequency switching currents.
For VLBI < 1.25V
The low battery detector can also be configured for voltages <1.25V by bootstrapping the LBI input from VOUT. The circuitry for this is shown in figure 7.
ILC6383 R2 VIN R1 3 LBI/SD + 1.25V Internal Reference 7 GND 8 VOUT
Figure 7: VLBI < 1.25V The following equation is used when VIN is lower than 1.25V R1 = R2 x [(VREF - VIN) / (VOUT - VREF)], where VREF = 1.25V (nom.) This equation can also be derived using voltage divider formula across R2. A typical value for R2 is 100k.
(c)2001 Fairchild Semiconductor Corporation
6
ILC6383
Shut Down
The LBI pin is shared with the shutdown pin. A low voltage (<0.4V) will put the ILC6383 into a power down state. The simplest way to implement this is with an FET across R6 as shown in figure 8. Note that when the device is not in PWM mode or is in shutdown the low battery detector does not operate. When the ILC6383 is shut down, the synchronous rectifier disconnects the output from the input. This ensures that there is only leakage (IIN < 1A typical) from the input to the output so that the battery is not drained when the ILC6383 is shut down.
Negative Voltage Output
It is possible to generate a negative output voltage as a secondary supply using the ILC6383. This negative voltage may be useful in some applications where a negative bias voltage at low current is required.
1A Schottky Diodes -V 0.01F 0.01F ILC6383
1 LX
L VIN
2 VIN
2 VIN ILC6383 R5 3 ON/OFF LBI/SD R6 7 GND
Figure 10: Negative Output Voltage
Figure 8: Shut Down Control
Power Good Output (POK)
The POK output of the ILC6383 indicates when VOUT is within the regulation tolerance of the set output voltage. POK output is an open drain device output capable of sinking 2mA. It will remain pulled low until the output voltage has risen to typically 95% of the specified VOUT. Note that a pull-up resistor must be connected from the POK output (pin 5 of ILC6383CIR-XX) to either ILC6383's output or to some other system voltage source.
Adjustable Output Voltage Selection
The ILC6383-ADJ allows the output voltage to be set using a potential divider. The formula for setting the adjustable output voltage is; VOUT = VFB x (1+R1/R2), where VFB is the threshold set which is 1.25V nominal.
C IN
47F
ILC6383-ADJ L 1 LX VIN LBI/SD SEL VOUT GND LBO VFB MSOP-8 PWM PFM VOUT = 1.25 (1+R1/R2) 8 + 7 R1 3 6 5 R2
47F COUT
VOUT
VIN 1 to 3-cell ON OFF R6 R5
15H 2
4
Figure 9: Adjustable Voltage Configuration
(c)2001 Fairchild Semiconductor Corporation
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ILC6383
External Component Selection
Inductors
The ILC6383 is designed to work with a 15H inductor in most applications. There are several vendors who supply standard surface mount inductors to this value. Suggested suppliers are shown in table 1. Higher values of inductance will improve efficiency, but will reduce peak inductor current and consequently ripple and noise, but will also limit output current. Vendor Coilcraft Part No. D03308P-153 D03316P-153 D01608C-153 LQH4N150K LQH3C150K CDR74B-150MC CD43-150 CD54-150 NLC453232T-150K Contact (847) 639-6400
Layout and Grounding Considerations
High frequency switching and large peak currents means PCB design for DC-DC converters requires careful consideration. A general rule is to place the DC-DC converter circuitry well away from any sensitive RF or analog components. The layout of the DC-DC converters and its external components are also based on some simple rules to minimize EMI and output voltage ripple.
Layout
1. Place all power components, ILC6383, inductor, input capacitor and output capacitor as close together as possible. 2. Keep the output capacitor as close to the ILC6383 as possible with very short traces to the VOUT and GND pins. Typically it should be within 0.25 inches or 6mm. 3. Keep the traces for the power components wide, typically >50mil or 1.25mm. 4. Place the external networks for LBI and VFB close to the ILC6383, but away from the power components as far as possible.
muRata Sumida
(814) 237-1431 (847) 956-0666
TDK
(847) 390-4373
Capacitors
Input Capacitor
The input capacitor is necessary to minimize the peak current drawn from the battery. Typically a 10F tantalum capacitor is recommended. Low equivalent series resistance (ESR) capacitors will help to minimize battery voltage ripple.
Grounding
1. Use a star grounding system with separate traces for the power ground and the low power signals such as LBI/SD and VFB. The star should radiate from where the power supply enters the PCB. 2. On multilayer boards use component side copper for grounding around the ILC6383 and connect back to a quiet ground plane using vias.
Output Capacitor
Low ESR capacitors should be used at the output of the ILC6383 to minimize output ripple. The high switching speeds and fast changes in the output capacitor current, mean that the equivalent series impedance of the capacitor can contribute greatly to the output ripple. In order to minimize these effects choose an output capacitor with less than 10nH of equivalent series inductance (ESL) and less than 100m of equivalent series resistance (ESR). Typically these characteristics are met with ceramic capacitors, but may also be met with certain types of tantalum capacitors. Suitable vendors are shown in table 2. Description T495 series tantalum 595D series tantalum TAJ, TPS series tantalum Y5V Ceramic Vendor Kemet Sprague AVX TDK AVX muRata Contact (864) 963-6300 (603) 224-1961 (803) 946-0690 (847) 390-4373 (803) 946-0690 www.murata.com
C IN
47F
ILC6383 L1 1 LX VIN LBI/SD SEL VOUT GND LBO VFB 8 + 7 6 5 R2
COUT 47F
VOUT
VIN
15H 2 3
R1
R3 Load
ON/OFF PWM PFM 4
Local "Quiet" Ground Power Ground
Recommended application circuit schematic for ILC6383CIR-ADJ
(c)2001 Fairchild Semiconductor Corporation
8
ILC6383
U1 L1 C2
47F
U1
ILC6383XX
C2
1 LX VOUT 8 C1 GND 7 LBO 6 POK/VFB 5
47F R3
47F
ILC6383ADJ
L1
VOUT
1 15mH 2V IN ON OFF 3 LBI 4 SEL
LX
VOUT
8
47F
VOUT C1 R1 R3 10K LBO VFB R2
15H VIN ON OFF SEL GND 1MW PWM PFM R4 U2 4 SEL 2V IN 3 LBI
R1 10K 10K
VIN
LBO POK
GND 7 LBO 6 POK/VFB 5
SEL GND PWM PFM R4 1MW U2
NOTE: R1 and R2 are user determined values to set VOUT VFB(1+R1/R2) =
Evaluation Board Parts List For Printed Circuit Board Shown Above
Label U1 C L1 R1 and R2 R3 R4 Part Number ILC6383CIR-ADJ GRM43-2X5R476K6.3 LQS66C150M04 Manufacturer Fairchild Semiconductor muRata muRata Dale, Panasonic Dale, Panasonic Dale, Panasonic Description Step-up DC-DC converter 47F, ceramic capacitor 15H, 1.3A User Determined Values 10k, 1/10W, SMT 1M, 1/10W, SMT
Label U1 C L1 R1 and R3 R4
Part Number ILC6383CIR-XX GRM43-2X5R476K6.3 LQS66CA50M04 -
Manufacturer Fairchild Semiconductor muRata muRata Dale, Panasonic Dale, Panasonic
Description Step-up DC-DC converter 47F, ceremic capacitor 15H, 1.3A 10k, 1/10W, SMT 1m, 1/10W, SMT
(c)2001 Fairchild Semiconductor Corporation
9
ILC6383
Typical Performance Characteristics ILC6383CIR-33 (
Unless otherwise specified: TA = 25C, CIN = 47F, C
Efficiency (PWM Mode)
1 V IN = 2V 0.9 Efficiency V IN = 1.5V 0.8 Efficiency 0.8 V IN = 2.5V 0.85 0.9 V IN = 1.5V
OUT
= 3.3 V)
OUT = 47F, L = 15H.
Efficiency (PFM Mode)
V IN = 2V
V IN = 2.5V
0.7
0.6 30 50 100 150 200 250 300 Load Current (mA) 350 400
0.75
0.7
0.65 1 5 10 15 20 Load Current (mA) 25 30
Load Regulation (PWM Mode)
3.42 3.4 3.38 3.36
Load Regulation (PFM Mode)
3.36 3.34 Output Voltage (V) 3.32 3.3 3.28 3.26 3.24 3.22 3.2 1
50 100 150 200 250 300 350 400
V IN = 3V V IN = 2V V IN = 1.5V
Output Voltage (V)
3.34 3.32 3.3 3.28 3.26 3.24 3.22 3.2 3.18 Load Current (mA) V IN = 1.5V V IN = 2V V IN = 2.5V
5
10 15 20 Load Current (mA)
25
Start-up Input Voltage vs Output current in PFM
1.9 1.8 Start-up Input Voltage (V) 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 1 10 20 30 40 50 Load Current (mA)
(c)2001 Fairchild Semiconductor Corporation
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ILC6383
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 10/5/01 0.0m 001 Stock#DSxxxxxxxx 2001 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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