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LMH6503 Wideband, Low Power, Linear Variable Gain Amplifier
October 2003
LMH6503 Wideband, Low Power, Linear Variable Gain Amplifier
General Description
The LMH6503 is a wideband DC coupled differential input voltage controlled gain stage followed by a high-speed current feedback Op Amp which can directly drive a low impedance load. Gain adjustment range is more than 70dB for up to 10MHz. Maximum gain is set by external components and the gain can be reduced all the way to cut-off. Power consumption is 370mW with a speed of 135MHz . Output referred DC offset voltage is less than 350mV over the entire gain control voltage range. Device-to-device Gain matching is within 0.7dB at maximum gain. Furthermore, gain at any VG is tested and the tolerance is guaranteed. The output current feedback Op Amp allows high frequency large signals (Slew Rate = 1800V/s) and can also drive heavy load current (75mA). Differential inputs allow common mode rejection in low level amplification or in applications where signals are carried over relatively long wires. For single ended operation, the unused input can easily be tied to ground (or to a virtual half-supply in single supply application). Inverting or non-inverting gains could be obtained by choosing one input polarity or the other. To further increase versatility when used in a single supply application, gain control range is set to be from -1V to +1V relative to pin 11 potential (ground pin). In single supply operation, this ground pin is tied to a "virtual" half supply. Gain control pin has high input impedance to simplify its drive requirement. Gain control is linear in V/V and VG provides attenuation from the maximum setting. Maximum gain can be set to be anywhere between 1V/V to 100V/V or higher. For linear in dB gain control applications, see LMH6502 datasheet. The LMH6503 is available in the SOIC-14 package.
Features
VS = 5V, TA = 25C, RF = 1k, RG = 174, RL = 100, AV = AV(MAX) = 10, Typical values unless specified. n -3dB BW 135MHz n Gain control BW 100MHz n Adjustment range (typical over temp) 70dB 0.7dB n Gain matching (limit) n Slew rate 1800V/s n Supply current (no load) 37mA 75mA n Linear output current 3.2V n Output voltage (RL = 100) n Input voltage noise 6.6nV/ n Input current noise 2.4pA// n THD (20MHz, RL = 100, VO = 2Vpp) -57dBc n Replacement for CLC522
Applications
n n n n Variable attenuator AGC Voltage controller filter Multiplier
Typical Application
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Gain vs. VG for Various Temperature
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AVMAX = 10V/V
(c) 2003 National Semiconductor Corporation
DS200739
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LMH6503
Absolute Maximum Ratings
(Note 1)
Soldering Information: Infrared or Convection (20 sec) Wave Soldering (10 sec) Storage Temperature Range Junction Temperature 235C 260C -65C to +150C +150C
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance: (Note 4) Human Body Machine Model Input Current VIN Differential Output Current Supply Voltages (V - V ) Voltage at Input/ Output pins
+ - + -
2KV 200V
10mA (V+ -V-)
120mA (Note 3) 12.6V V +0.8V,V - 0.8V
Operating Ratings (Note 1)
Supply Voltages (V+ - V-) Temperature Range Thermal Resistance: 14-Pin SOIC JA 138C/W 5V to 12V -40C to +85C JC 45C/W
Electrical Characteristics(Note 2)
Unless otherwise specified, all limits guaranteed for TJ = 25C, VS = 5V, AV(MAX) = 10, VCM = 0V, RF = 1k, RG = 174, VIN_DIFF = 0.1V, RL = 100, VG = +1V. Boldface limits apply at the temperature extremes. Symbol BW GF Parameter -3dB Bandwidth Gain Flatness Conditions VOUT < 0.5PP VOUT < 0.5PP, AV(MAX) = 100 VOUT < 0.5VPP, -1V < VG < 1V, 0.2dB Min (Note 6) Typ (Note 6) 135 50 40 20 6.6 100 1.6 2.6 -48 79 68 2.2 10 1800 4.6 Max (Note 6) Units
Frequency Domain Response MHz MHz
Att Range Flat Band (Relative to Max Gain) Attenuation Range (Note 13) BW Control PL G Delay CT (dB) GR Gain Control Bandwidth Linear Phase Deviation Group Delay Feed-through Gain Adjustment Range
0.2dB Flatness, f < 30MHZ 0.1dB, f < 30MHZ
VG = 0V (Note 11) DC to 60MHz DC to 130MHz VG = -1.2V, 30MHz (Output Referred) f < 10MHz f < 30MHz
MHz MHz deg ns dB
dB
Time Domain Response t r , tf OS% SR G Rate Rise and Fall Time Overshoot Slew Rate Gain Change Rate 0.5V Step 0.5V Step 4V Step (Note 5) VIN = 0.3V, 10%-90% of final output 2VPP, 20MHz 2VPP, 20MHz 2VPP, 20MHz 1MHz to 150MHz 1MHz to 150MHz f = 4.43MHz, RL = 150, Neg. Sync f = 4.43MHz, RL = 150, Neg. Sync ns % V/s dB/ns
Distortion & Noise performance HD2 HD3 THD En tot In DG DP 2nd Harmonic Distortion 3 Harmonic Distortion Total Harmonic Distortion Total Equivalent Input Noise Input Noise Current Differential Gain Differential Phase
rd
-60 -61 -57 6.6 2.4 0.15 0.22
dBc dBc dBc nV/ pA/ % deg
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LMH6503
Electrical Characteristics(Note 2)
(Continued) Unless otherwise specified, all limits guaranteed for TJ = 25C, VS = 5V, AV(MAX) = 10, VCM = 0V, RF = 1k, RG = 174, VIN_DIFF = 0.1V, RL = 100, VG = +1V. Boldface limits apply at the temperature extremes. Parameter Gain Accuracy (see Application Notes) Gain Matching (see Application Notes) Gain Multiplier (see Application Notes) Input Voltage Range Differential Input Voltage RG Current Bias Current Pin 3 & 6 Common Mode, |CMRR| > 50dB (Note 9) Across pins 3 & 6 Pins 4 & 5 Pins 3 & 6 (Note 7) Pins 3 & 6 (Note 7), VS= 2.5V VG =1.0V 0V < VG < 1V -0.7V < VG < 1V VG = 1.0 0 < VG < 1V -0.7V < VG < 1V 1.58 1.58 Conditions Min (Note 6) Typ (Note 6) +0.25 Max (Note 6) +0.9/-0.4 +1.3/-1.5 +4.4/-4.3 dB Units
Symbol GACCU
DC & Miscellaneous Performance
0.3 0.4
- - - 1.72
G Match
0.7
+1.7/-1.1 +4.0/-4.7 1.87 1.91 V/V V dB
K VCM VIN_ DIFF IRG MAX IBIAS
2.0 1.80 0.34 0.28 1.70 1.60
2.2 0.37 2.30
11 3 100 0.01 5 750 5 45 20 70 1.3 2.0 2.5 18 20 10 13
V mA
A
TCBIAS I
OFF
Bias Current Drift Offset Current Offset Current Drift Input Resistance Input Capacitance VG Bias Current VG Bias Drift VG Input Resistance VG Input Capacitance Output Voltage Range
Pin 3 & 6 (Note 8) Pin 3 & 6 (Note 8) Pin 3 & 6 Pin 3 & 6 Pin 2, VG = 1.4V(Note 7) Pin 2 (Note 8) Pin 2 Pin 2 RL = 100 RL Open
nA/C A nA/C k pF A nA/C K pF
TC IOFF RIN CIN IVG TC IVG R VG C VG VOUT
3.00 2.97 3.95 3.90 75 70
3.20 4.05
0.1 V
ROUT IOUT VO
OFFSET
Output Impedance Output Current Output Offset Voltage +Power Supply Rejection Ratio (see (Note 10)) -Power Supply Rejection Ratio (see (Note 10)) Common Mode Rejection Ratio (see (Note 9)) Supply Current
DC VOUT 4V from Rails -1V < VG < 1V Input Referred, 1V change, VG = 1.4V Input Referred, 1V change, VG = 1.4V Input Referred, VG = 1V -1.8V < VCM < 1.8V RL = Open RL = Open, VS = 2.5V
mA
90 80
-80 -67 -67 37 12 50 53 20 23
350 380
-58 -56 -57 -51
mV dB dB dB
+PSRR -PSRR CMRR IS
mA
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LMH6503
Electrical Characteristics(Note 2)
(Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower. Note 4: Human body model: 1.5k in series with 100pF. Machine model: 0 in series with 200pF. Note 5: Slew Rate is the average of the rising and falling rates. Note 6: Typical values represent the most likely parametric norm. Bold numbers refer to over temperature limits. Note 7: Positive current correspondes to current flowing in the device. Note 8: Drift determined by dividing the change in parameter distribution at temperature extremes by the total temperature change. Note 9: CMRR definition: [|VOUT/VCM|/AV] with 0.1V differential input voltage. VOUT is the change in output voltage with offset shift subtracted out. Note 10: +PSRR definition: [|VOUT/V+| /AV], -PSRR definition: [|VOUT/V-| /AV] with 0.1V differential input voltage. VOUT is the change in output voltage with offset shift subtracted out. Note 11: Gain Control Frequency Response Schematic:
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Note 12: Gain/Phase normalized to low frequency value at each AV. Note 13: Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain flatness specified (either 0.2dB or 0.1dB), relative to AVMAX gain. For example, for f<30MHz, here are the Flat Band Attenuation ranges:
0.2dB: 0.1dB:
10V/V down to 1V/V=20dB range 10V/V down to 4.7V/V=6.5dB range
Connection Diagram
14-Pin SOIC
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Top View
Ordering Information
Package 14-pin SOIC Part Number LMH6503MA LMH6503MAX Package Marking LMH6503MA Transport Media 55 Units/Rail 2.5k Units Tape and Reel NSC Drawing M14A
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LMH6503
Typical Performance Charateristics
Small Signal Frequency Response (AV = 2)
Unless otherwise specified: VS = 5V, 25C, VG = VG_MAX, VCM = 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output: Large Signal Frequency Response (AV = 2)
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Frequency Response over Temperature (AV = 10)
Frequency Response for Various VG (AVMAX = 10)
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Frequency Response for Various VG (AVMAX = 10) (2.5V)
Small Signal Frequency Response
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = 5V, 25C, VG = VG_MAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output: (Continued) Frequency Response for Various VG (AVMAX = 100) (Small Signal)
Large Signal Frequency Response
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Frequency Response for Various VG (AVMAX = 100) (Large Signal)
Gain Control Frequency Response
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IS vs. VS
IS vs. VS
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = 5V, 25C, VG = VG_MAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output: (Continued) Input Bias Current vs. VS AVMAX vs. VS
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PSRR 5V
PSRR 2.5V
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CMRR 5V
CMRR 2.5V
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = 5V, 25C, VG = VG_MAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output: (Continued) AVMAX vs. VCM AVMAX vs. VCM
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Supply Current vs. VCM
Supply Current vs. VCM
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Output Offset Voltage vs.VCM (Typical Unit 1)
Output Offset Voltage vs.VCM (Typical Unit 2)
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = 5V, 25C, VG = VG_MAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output: (Continued) Output Offset Voltage vs.VCM (Typical Unit 3) Feed through Isolation
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Gain Flatness and Linear Phase Deviation
Gain Flatness Frequency vs. Gain (Note 13)
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Group Delay vs. Frequency
K Factor vs. RG
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = 5V, 25C, VG = VG_MAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output: (Continued) Gain vs. VG Including Limits BW vs. RF for Various RG
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Gain vs. VG (5V)
Output Offset Voltage vs. VG (Typical Unit 1)
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Output Offset Voltage vs. VG (Typical Unit 2)
Output Offset Voltage vs. VG (Typical Unit 3)
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = 5V, 25C, VG = VG_MAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output: (Continued) Output Offset Voltage vs. VS for Various VG (Typical Unit 1) Output Offset Voltage vs. VS for Various VG (Typical Unit 2)
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Output Offset Voltage vs. VS for Various VG (Typical Unit 3)
Gain vs. VG (2.5V)
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Noise vs. Frequency (AVMAX = 2)
Noise vs. Frequency (AVMAX = 10)
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = 5V, 25C, VG = VG_MAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output: (Continued) Noise vs. Frequency (AVMAX = 100) -1dB Compression
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Output Voltage vs. Output Current
HD2 vs. POUT
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HD3 vs. POUT
THD vs. POUT
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = 5V, 25C, VG = VG_MAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output: (Continued) HD2 & HD3 vs. VG THD vs. VG
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VG Bias Current vs. VG
Step Response Plot
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Step Response Plot
Gain vs. VG Step
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = 5V, 25C, VG = VG_MAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output: (Continued) VG Feedthrough
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Application Information
THEORY OF OPERATION The LMH6503 is a linear wideband variable-gain amplifier as illustrated in Figure 1. A voltage input signal may be applied differentially between the two inputs (+VIN, -VIN), or singleendedly by grounding one of the two unused inputs. The LMH6503 input buffers convert the input voltage to a current (IRG) that is a function of the differential input voltage (VINPUT = (+VIN) - (-VIN)) and the value of the gain setting resistor (RG). This current (IRG) is then mirrored to a gain stage with a current gain of K (1.72 nominal). The voltage controlled two-quadrant multiplier attenuates this current which is then converted to a voltage via the output amplifier. This output amplifier is a current feedback op amp configured as a Transimpedance amplifier. Its Transimpedance gain is the feedback resistor (RF). The input signal, output, and gain control are all voltages. The output voltage can easily be calculated as shown in Equation 1: (3) Notice also that Equation 3 holds for both differential and single ended operation.
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(1) Where K = 1.72 (Nominal) since:
FIGURE 1. LMH6503 Functional Block Diagram CHOOSING RF AND RG RG is calculated from Equation 4. VINPUTMAX is the maximum peak
The gain of the LMH6503 is therefore a function of three external variables: RG, RF, and VG as expressed in Equation 2: (4) input voltage (Vpk) determined by the application. IRGMAX is the maximum allowable current through RG and is typically 2.3mA. Once AVMAX is determined from the minimum input and desired output voltages, RF is then determined using Equation 5. These values of RF and RG are
(2) The gain control voltage (VG) has an ideal input range of -1V < VG < +1V. At VG = +1V, the gain of the LMH6503 is at its maximum as expressed in Equation 3:
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LMH6503
Application Information
(Continued)
(5) the minimum possible values that meet the input voltage and maximum gain constraints. Scaling the resistor values will decrease bandwidth and improve stability. Figure 2 illustrates the resulting LMH6503 bandwidths as a function of the maximum ( y axis) and minimum (related to x axis) input voltages when VOUT is held constant at 1VPP.
Once this is accomplished, the offset errors introduced by the input stage and multiplier core can then be treated. The second step requires the absence of an input signal and matched source impedances on the two input pins in order to cancel the bias current errors. This done, then +1.1V should be applied to VG and the trim pot located at R10 adjusted in order to null the offset voltage seen at the LMH6503's output. If a more limited gain range is anticipated, the above adjustments should be made at these operating points. These steps will minimize the output offset voltage. However, since the offset term itself varies with the gain setting, the correction is not perfect and some residual output offset will remain. GAIN ACCURACY Defined as the ratio of measured gain (V/V), at a certain VG, to the best fit line drawn through the typical gain (V/V) distribution for -1V < VG < 1V (results expressed in dB) (See Figure 4). The best fit gain (AV) is given by: (6) AV (V/V) = 4.87VG + 4.61 For: -1V VG + 1V, RF = 1k, RG = 174 For a VG range, the value specified in the tables represents the worst case accuracy over the entire range. The "Typical" value would be the worst case ratio between the "Typical Gain" and the best fit line. The "Max" value would be the worst case between the max/min gain limit and the best fit line. GAIN MATCHING Defined as the limit on gain variation at a certain VG (expressed in dB) (See Figure 4). Specified as "Max" only (no "Typical"). For a VG range, the value specified represents the worst case matching over the entire range. The "Max" value would be the worst case ratio between the max/min gain limit and the typical gain.
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FIGURE 2. Bandwidth vs. VINMAX and AVMAX ADJUSTING OFFSETS Treating the offsets introduced by the input and output stages of the LMH6503 is accomplished with a two step process. The offset voltage of the output stage is treated by first applying -1.1V on VG, which effectively isolates the input stage and multiplier core from the output stage. As illustrated in Figure 3, the trim pot located at R14 on the LMH6503 Evaluation Board (CLC730033) should then be adjusted in order to null the offset voltage seen at the LMH6503's output (pin 10).
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FIGURE 4. Gain Accuracy and Gain Matching Parameters Defined NOISE Figure 5 describes the LMH6503's output-referred spot noise density as a function of frequency with AVMAX = 10V/V. The plot includes all the noise contributing terms. However,
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FIGURE 3. Nulling the Output Offset Voltage
LMH6503
Application Information
(Continued)
with both inputs terminated in 50, the input noise contribution is minimal. At AVMAX = 10V/V, the LMH6503 has a typical flat-band input-referred spot noise density (ein) of 6.6nV/ . For applications with -3dB BW extending well into the flat-band region, the input RMS voltage noise can be determined from the following single-pole model:
(7)
minimum. Parasitic or load capacitance, CL, on the output (pin 10) degrades phase margin and can lead to frequency response peaking or circuit oscillation. The LMH6503 is fully stable when driving a 100 load. With reduced load (e.g. 1k) there is a possibility of instability at very high frequencies beyond 400MHz especially with a capacitive load. When the LMH6503 is connected to a light load as such, it is recommended to add a snubber network to the output (e.g. 100 and 39pF in series tied between the LMH6503 output and ground). CL can also be isolated from the output by placing a small resistor in series with the output (pin 10). Component parasitics also influence high frequency results. Therefore it is recommended to use metal film resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not recommended. National Semiconductor suggests the following evaluation board as a guide for high frequency layout and as an aid in device testing and characterization: Device LMH6503MA Package SOIC-14 Evaluation Board Part Number CLC730033
The evaluation board is shipped when a device sample request is placed with National Semiconductor. SINGLE SUPPLY OPERATION It is possible to operate the LMH6503 with a single supply. Two examples are shown in Figure 7 & Figure 8.
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FIGURE 5. Output Referred Voltage Noise vs. Frequency CIRCUIT LAYOUT CONSIDERATIONS Good high-frequency operation requires all of the decoupling capacitors shown in Fig. 6 to be placed as close as possible to the power supply pins in order to insure a proper high-frequency low-impedance bypass. Adequate ground plane and low inductive power returns are also
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FIGURE 7. AC Coupled Single Supply VGA
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FIGURE 6. Required Power Supply Decoupling required of the layout. Minimizing the parasitic capacitances at pins 3, 4, 5, 6, 9, 10 and 12 will assure best high frequency performance. The parasitic inductance of component leads or traces to pins 4, 5 and 9 should also be kept to a
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LMH6503
Application Information
(Continued)
(VS = 2.5V). In addition, there is the more drastic mechanism described in "b" above and shown in Figure 9. Similar plots for V+ = 5V operation are shown in Figure 10 for comparison and reference.
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FIGURE 8. Transformer Coupled Single Supply VGA OPERATING AT LOWER SUPPLY VOLTAGES The LMH6503 is rated for operation down to 5V supplies (V+ - V-). There are some specifications shown for operation at 2.5V within the data sheet (i.e. Frequency Response, CMRR, PSRR, Gain vs. VG, etc.). Compared to 5V operation, at lower supplies: a) VG range constricts. Referring to Figure 9, note that VG_MAX (VG voltage required to get maximum gain) is 0.5V (VS = 2.5V) compared to 1.0V for VS = 5V. At the same time, gain cut-off (VG_MIN) would shift to -0.5V from - 1V with VS = 5V. Table 1 shows the approximate expressions for various VG voltages as a function of V-: Table 1: VG Definition Based on V- VG VG_MIN VG_MID VG_MAX Definition Gain Cut-off AVMAX/2 AVMAX Expression (V) 0.2 x V- 0 -0.2 x V-
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FIGURE 9. VG_MAX, VG_LIMIT, & Max-gain vs. V- (V+ = 2.5V)
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b) VG_LIMIT (maximum permissible voltage on VG) is reduced. This is due to limitations within the device arising from transistor headroom. Beyond this limit, device performance will be affected (non-destructive). Referring to Figure 9, note that with V+ = 2.5V, and V- = -4V, VG_LIMIT is approaching VG_MAX and already "Max gain" is reduced by 1dB. This means that operating under these conditions has reduced the maximum permissible voltage on VG to a level below what is needed to get Max gain. If supply voltages are asymmetrical, reference Figure 9 and Figure 10 plots to make sure the region of operation is not overly restricted by the "pinching" of VG_LIMIT, and VG_MAX curves. c) "Max_gain" reduces. There is an intrinsic reduction in max gain when the total supply voltage is reduced (see Typical Performance Characteristics plots for Gain vs. VG
FIGURE 10. VG_MAX, VG_LIMIT, & Max-gain vs. V- (V+ = 5V)
Application Circuits
FOUR-QUADRANT MULTIPLIER Applications requiring multiplication, squaring or other nonlinear functions can be implemented with four-quadrant multipliers. The LMH6503 implements a four-quadrant multiplier as illustrated in Figure 11:
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LMH6503
Application Circuits
(Continued)
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FIGURE 11. Four Quadrant Multiplier
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FREQUENCY SHAPING Frequency shaping and bandwidth extension of the LMH6503 can be accomplished using parallel networks connected across the RG ports. The network shown in the Figure 12 schematic will effectively extend the LMH6503's bandwidth.
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FIGURE 13. Tunable Bandpass Filter
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FIGURE 12. Frequency Shaping 2nd ORDER TUNABLE BANDPASS FILTER The LMH6503 Variable-Gain Amplifier placed into a feedback loop provides signal processing function such as in a 2nd order tunable bandpass filter. The center frequency of the 2nd order bandpass shown in Figure 13 is adjusted through the use of the LMH6503's gain control voltage, VG. The integrators implemented with two sections of a LMH6682, provide the coefficients for the transfer function.
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LMH6503 Wideband, Low Power, Linear Variable Gain Amplifier
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Pin SOIC NS Package Number M14A
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