View M41T60_989327.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M41T60
Serial Access Real-Time Clock
PRELIMINARY DATA
FEATURES SUMMARY

TIMEKEEPING DOWN TO 1.0V 1.3V TO 3.6V I2C BUS OPERATING VOLTAGE COUNTERS FOR SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEARS, AND CENTURY SERIAL INTERFACE SUPPORTS I2C BUS (400KHz) SOFTWARE CLOCK CALIBRATION LOW OPERATING CURRENT OF 350A OSCILLATOR STOP DETECTION AUTOMATIC LEAP YEAR COMPENSATION SOFTWARE PROGRAMMABLE OUTPUT (OUT) OPERATING TEMPERATURE OF -40 TO 85C LEAD-FREE 16-PIN QFN
Figure 1. Package
QFN16 (Q)
Figure 2. 16-pin QFN Connections
NC NC VCC 14 NC 13 12 11 10 9 5 VSS 6 NC 7 NC 8 NC NC OFIRQ/OUT SCL SDA
(1)
16 XI XO VSS FT
(1)
15
1 2 3 4
AI08870
Note: 1. Open Drain Output only.
May 2004
1/22
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M41T60
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. 16-pin QFN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Stop data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Century Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Century Bits Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 13.AC Testing Input/Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 14.Crystal Isolation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/22
M41T60
Table 6. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 15.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 16.QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline . . . . . . . . 18 Table 10. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data . 19 Figure 17.QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Footprint . . . . . . . 19 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
M41T60
SUMMARY DESCRIPTION
The M41T60 Serial Access TIMEKEEPER(R) is a low power Serial RTC with a built-in 32.768KHz oscillator (external crystal controlled). Eight registers are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two-line bi-directional bus. The built-in address register is incremented automatically after each WRITE or READ data byte. The eight clock address locations contain the century, year, month, date, day, hour, minute, and second; in 24-hour BCD format. Corrections for 28-, 29- (leap year), 30-, and 31-day months are made automatically. The M41T60 is supplied in 16-lead QFN package.
Figure 3. Logic Diagram
VCC
Table 1. Signal Names
XI XO FT Oscillator Input Oscillator Output Frequency Test Output (Open Drain) Serial Data Address Input / Output Serial Clock Oscillator Fail Interrupt/OUT Output (Open Drain) Supply Voltage Ground
XI SCL SDA M41T60
XO FT OFIRQ/OUT
SDA SCL OFIRQ/OUT VCC
VSS
AI08869
VSS
4/22
M41T60
Figure 4. Block Diagram
FT FT OUT OFIE OSCILLATOR FAIL DETECT SECONDS MINUTES HOURS VCC VSS CONTROL LOGIC DAY DATE CENTURY/ MONTH SERIAL BUS INTERFACE YEAR ADDRESS REGISTER CALIBRATION OFIRQ/OUT
1 Hz XI OSCILLATOR 32.768 kHz XO DIVIDER
SCL
SDA
AI08871
5/22
M41T60
OPERATION
The M41T60 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1. Seconds Register 2. Minutes Register 3. Hours Register 4. Day Register 5. Date Register 6. Century/Month Register 7. Years Register 8. Calibration Register 2-Wire Bus Characteristics This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line while the clock line is High will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy. Both data and clock lines remain High. Start data transfer. A change in the state of the data line, from High to Low, while the clock is High, defines the START condition. Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the message is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves". Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition.
6/22
M41T60
Figure 5. Serial Bus Data Transfer Sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 6. Acknowledgement Sequence
START SCLK FROM MASTER 1 2 8 CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
7/22
M41T60
READ Mode In this mode, the master reads the M41T60 slave after setting the slave address (see Figure 7). Following the WRITE Mode Control Bit (R/W = 0) and the Acknowledge Bit, the word address An is written to the on-chip address pointer. Next the START condition and slave address are repeated, followed by the READ Mode Control Bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Bit. The M41T60 slave transmitter will now place the data byte at address An+1 on the bus. The master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (0h to 6h). The update will resume due to Figure 7. Slave Address Location
R/W
a Stop Condition or when the pointer increments to any non-clock address (7h). An alternate READ Mode may also be implemented, whereby the master reads the M41T60 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 9., page 9). WRITE Mode In this mode the master transmitter transmits to the M41T60 slave receiver. Bus protocol is shown in Figure 10., page 9. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T60 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see Figure 7).
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
8/22
M41T60
Figure 8. READ Mode Sequence
START START R/W
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An)
S
R/W
DATA n
DATA n+1
ACK
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS
DATA n+X
P
AI00899
Figure 9. Alternate READ Mode Sequence
START R/W STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
Figure 10. WRITE Mode Sequence
START
NO ACK
STOP
ACK
BUS ACTIVITY: MASTER
R/W
SDA LINE
S
WORD ADDRESS (An)
ACK ACK
DATA n
DATA n+1
DATA n+X
P
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
ACK
STOP
9/22
M41T60
CLOCK OPERATION
The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of 32.768KHz. The accuracy of the Real-Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The M41T60 is tested to meet 35 ppm with a nominal crystal. The eightbyte Clock Register (see Table 2., page 11) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, Minutes, and Hours are contained within the first three registers. Bits D6 and D7 of Clock Register 05h (Century/ Month Register) contain the CENTURY Bit 0 (CB0) and the CENTURY Bit 1 (CB1). See Table 3., page 13 for additional explanation. Bits D0 through D2 of Register 03h contain the Day (day of the week). Registers 04h, 05h, and 06h contain the Date (day of the month), Century/Month, and Years. the eighth clock register is the Calibration Register (this is described in the Clock Calibration section). Bit D7 of Register 00h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0,' the oscillator restarts within one second (typical). Note: Upon initial power-up, the user should set the ST Bit to a '1,' then immediately reset the ST Bit to '0.' This provides an additional "kick-start" to the oscillator circuit. Bit D7 of Register 01h contains the Oscillator Fail Interrupt Enable Bit (OFIE - see the description in the Oscillator Fail Detection section). Note: A WRITE to ANY location within the first seven bytes of the clock register (0h-6h), including the OFIE and ST Bit, will result in an update of the system clock and a reset of the divider chain. This could result in an inadvertent change of the current time. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The seven Clock Registers may be read one byte at a time, or in a sequential block. The Calibration Register (Address location 7h) may be accessed independently. Provision has been made to ensure that a clock update does not occur while any of the clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. this will prevent a transition of data during the READ. Calibrating the Clock The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, with a nominal crystal (see Note 1 of Table 8., page 16). When the Calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25C. The oscillation rate of crystals changes with temperature (see Figure 11., page 12). The M41T60 design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 12., page 12. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration Bits found in the Calibration Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Bits occupy the five lower-order bits (D4-D0) in the Calibration Register 07h. These bits can be set to represent any value between 0 and 31 in binary format. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64-minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles. That is, +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per day which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T60 may require: - The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note 934, "TIMEKEEPER(R) CALIBRATION." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte.
10/22
M41T60
- The second approach is better suited to a manufacturing environment, and involves the use of the Frequency Test (FT) pin. The FT pin will toggle at 512Hz when the ST Bit is set to '0,' and the OUT Bit and FT Bit are set to '1.' Any measured deviation from the 512Hz frequency indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the Calibration Byte for correction. Note: Setting or changing the Calibration Byte does not affect the Frequency Test output frequency. the FT pin is an open drain pin which requires a pull-up resistor to VCC for proper operation. A 500-10k resistor is recommended in order to control the rise time.
Table 2. Register Map
Data Address D7 0 1 2 3 4 5 6 7 OUT ST OFIE 0 0 0 CB1 0 0 0 CB0 0 D6 D5 10 Seconds 10 Minutes 10 Hours 0 10 Date 10 M. 0 0 Date Month Years Calibration
OUT = Output level S = Sign Bit ST = STOP Bit
D4
D3
D2
D1
D0
Function/Range BCD Format Seconds Minutes Hours Day Date Century/Month Year Calibration 00-59 00-59 00-23 01-07 01-31 0-3/01-12 00-99
Seconds Minutes Hours Day
10 Years FT S
Keys: 0 = Must be set to '0.' CB0, CB1 = Century Bits FT = Frequency Test Bits OFIE = Oscillator Fail Interrupt Enable Bit
11/22
M41T60
Figure 11. Crystal Accuracy Across Temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = K x (T - T )2 O F K = -0.036 ppm/C 0.006 ppm/C TO = 25C 5C
2 2
Temperature C
AI07888
Figure 12. Calibration Waveform
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
12/22
M41T60
Century Bits These two bits will increment in a binary fashion at the turn of the century, and handle leap years correctly. See Table 3 for additional explanation. Output Driver Pin When the OFIE Bit is not set to generate an interrupt, the OFIRQ/OUT pin becomes an output driver that reflects the contents of D7 of the Calibration Register. In other words, when D7 (OUT Bit) is a '0,' then the OFIRQ/OUT pin will be driven low. Note: The OFIRQ/OUT pin is an open drain which requires an external pull-up resistor. Oscillator Stop Detection In the event that the oscillator has either stopped, or was stopped for some period of time, and if the Oscillator Fail Interrupt Enable (OFIE) Bit is set to a '1,' it will generate an interrupt. This interrupt can be used to judge the validity of the clock and date data. The interrupt will be active any time the oscillator stops. The following conditions will cause the OFIRQ pin to be active: Table 3. Century Bits Examples
CB0 0 0 1 1 CB1 0 1 0 1 Leap Year? Yes No No No Example(1) 2000 2100 2200 2300
The first time power is applied (defaults active on power-up). - The voltage present on VCC or back-up supply is insufficient to support oscillation. - The ST Bit is set to '1.' - External interference of the crystal. The Oscillator Fail Interrupt (OFIRQ) will remain enabled until the OFIE Bit is reset to '0,' or the oscillator restarts. The oscillator must start and have run for at least 4 seconds before attempting to set the OFIE Bit to '1.' Initial Power-on Defaults Upon initial application of power to the device, the OFIE and OUT Bit will be set to a '1,' while the ST and FT Bits will be set to '0.' Therefore, the OFIRQ pin will be low on power-up. All other Register bits will initially power-on in a random state.
-
Note: 1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
13/22
M41T60
MAXIMUM RATING
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 4. Absolute Maximum Ratings
Symbol TSTG VCC TSLD(1) VIO IO PD Parameter Storage Temperature (VCC Off, Oscillator Off) Supply Voltage Lead Solder Temperature for 10 Seconds Input or Output Voltages Output Current Power Dissipation Value -55 to 125 -0.3 to 4.6 260 -0.2 to VCC + 0.2 20 1 Unit C V C V mA W
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
14/22
M41T60
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 5. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
M41T60 1.3 to 3.6 -40 to 85 50 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
Unit V C pF ns V V
Figure 13. AC Testing Input/Output Waveform
Figure 14. Crystal Isolation Example
Local Grounding Plane (Layer 2)
XI
0.8VCC
Crystal 0.7VCC 0.3VCC
GND AI02568 XO
0.2VCC
AI09127
Note: Substrate pad should be tied to VSS.
Table 6. Capacitance
Symbol CIN COUT(3) tLP Parameter(1,2) Input Capacitance (SCL) Output Capacitance (SDA, OUT) Low-pass filter input time constant (SDA and SCL) Min Max 7 10 50 Unit pF pF ns
Note: 1. Effective capacitance measured with power supply at 3.6V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
15/22
M41T60
Table 7. DC Characteristics
Sym Parameter Test Condition(1) Clock(2) I2C Bus (400KHz) VCC = 3.6V ICC1 Supply Current SCL = 400KHz (No Load) VCC = 3.0V VCC = 2.5V VCC = 2.0V Supply Current (Standby) SCL = 0Hz All inputs VCC - 0.2V VSS + 0.2V @ 25C IOSC VIL VIH VOL Oscillator Current -40C to 85C Input Low Voltage Input High Voltage VCC = 3.6V, IOL = 3mA (SDA) Output Low Voltage VCC = 3.6V, IOL = 1mA (OFIRQ/OUT) Pull-up Supply Voltage (Open Drain) ILI ILO Input Leakage Current Output Leakage Current FT, OFIRQ/OUT 0V VIN VCC 0V VOUT VCC -1.0 -1.0 0.4 3.6 +1.0 +1.0 V V A A -0.2 0.7 VCC 0.3 VCC VCC + 0.2 0.4 A V V V 3.6V 3.0V 2.0V VCC = 3.0V 0.3 Min 1.0 1.3 Typ Max 3.6 3.6 400 350 300 250 0.70 0.65 0.60 0.5 Unit V V A A A A A A A A
VCC(3) Operating Voltage
ICC2
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 1.3 to 3.6V (except where noted). 2. Oscillator start-up guaranteed at 1.5V only. 3. When using battery back-up, VCC fall time should not exceed 10mV/s.
Table 8. Crystal Electrical Characteristics
Symbol Parameter(1,2) Resonant Frequency Series Resistance Load Capacitance 6 Min Typ 32.768 60(3) Max Unit KHz K pF
fO
RS CL
Note: 1. These values are externally supplied. STMicroelectronics recommends the Citizen CFS-145 (1.5x5mm) and the KDS DT-38 (3x8mm) for thru-hole, or the KDS DMX-26S (3.2x8mm) for surface-mount, tuning fork-type quartz crystals. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp. Citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com. 2. Load capacitors are integrated within the M41T60. Circuit board layout considerations for the 32.768KHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. Guaranteed by design.
16/22
M41T60
Figure 15. Bus Timing Requirements Sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
Note: P = STOP and S = START
Table 9. AC Characteristics
Symbol fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tSU:DAT tHD:DAT(2) tSU:STO tBUF SCL Clock Frequency Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time (after this period the first clock pulse is generated) START Condition Setup Time (only relevant for a repeated start condition) Data Setup Time Data Hold Time STOP Condition Setup Time Time the bus must be free before a new transmission can start 600 600 100 0 600 1.3 Parameter(1) Min 0 1.3 600 300 300 Typ Max 400 Unit KHz s ns ns ns ns ns ns s ns s
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 1.3 to 3.6V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
17/22
M41T60
PACKAGE MECHANICAL INFORMATION
Figure 16. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline
D
E
A3
A1
A
ddd C
b L
e K
1 2
E2
3
Ch
K D2
QFN16-A
Note: Drawing is not to scale.
18/22
M41T60
Table 10. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data
mm Symb Typ A A1 A3 b D D2 E E2 e K L ddd Ch N 0.90 0.02 0.20 0.25 3.00 1.70 3.00 1.70 0.50 0.20 0.40 - - Min 0.80 0.00 - 0.18 2.90 1.55 2.90 1.55 - - 0.30 0.08 0.33 16 Max 1.00 0.05 - 0.30 3.10 1.80 3.10 1.80 - - 0.50 - - Typ 0.035 0.001 0.008 0.010 0.118 0.067 0.118 0.067 0.020 0.008 0.016 - - Min 0.032 0.000 - 0.007 0.114 0.061 0.114 0.061 - - 0.012 0.003 0.013 16 Max 0.039 0.002 - 0.012 0.122 0.071 0.122 0.071 - - 0.020 - - inches
Figure 17. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Footprint
1.70 0.70 0.20
3.50
1.70
0.30 0.25 0.50
AI09126
Note: Substrate pad should be tied to VSS.
19/22
M41T60
PART NUMBERING
Table 11. Ordering Information Scheme
Example: M41T 60 Q 6 F
Device Family M41T
Device Type and Supply Voltage 60 = VCC = 1.3 to 3.6V
Package Q = QFN16 (3X3mils)
Temperature Range 6 = -40 to 85C
Shipping Method F = Lead-Free Package (ECO PACK(R)), Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
20/22
M41T60
REVISION HISTORY
Table 12. Document Revision History
Date November 13, 2003 20-Nov-03 25-Dec-03 13-Jan-04 26-Feb-04 02-Mar-04 26-Apr-04 13-May-04 Version 1.0 1.1 2.0 2.1 2.2 2.3 3.0 4.0 First Issue Update characteristics (Figure 2, 3, 4; Table 1, 2, 5, 7, 9) Reformatted; add crystal isolation, footprint (Figure 14) Update characteristics (Figure 11, 12, 14; Table 7, 11) Update characteristics and mechanical dimensions (Figure 16, 17; Table 4, 7, 10) Update characteristics (Table 7) Reformat and republish Update characteristics (Table 4, 7, 8; Figure 14, 17) Revision Details
M41T60, 41T60, T60, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, Leap year, Leap year, Leap year, Leap year, Leap year, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP
21/22
M41T60
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
22/22

▲Up To Search▲

Price & Availability of M41T60

	To Download M41T60 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .