 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Microcomputer Components 8-Bit CMOS Microcontroller C515C-8E Addendum to C515C User's Manual 08.96 Rev. 1.0 05.97 C515C-8E C515C-8E - Addendum to C515C User's Manual V1.0 05.97 Revision History : Original Version Previous Releases : Page / Chapters none Subjects (changes since last revision) Contents 1 2 2.1 2.2 3 3.1 3.2 4 4.1 4.2 4.2.1 4.2.2 4.2.3 5 5.1 5.2 5.3 5.4 5.5 5.6 6 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Extended Functionality of the C515C-8E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Second Pin for Wake-up from Software Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Switch-off Capability of the CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration of OTP Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definitions in OTP Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Basic Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Lock Bits Programming / Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Access of Version Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 OTP Memory Programming Mode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Semiconductor Group 2 Addendum V1.0 05.97 C515C-8E 1 Introduction The C515C-8E is the OTP version in the C515C-8R microcontroller with a one-time programmable 64K byte program memory. With the C515C-8E fast programming cycles are achieved (1 byte in 100 sec). Also several levels of OTP memory protection can be selected. The basic functionality of the C515C-8E as a microcontroller is upward compatible to the C515C-8R (ROM part) or C515CL (romless part) functionality. Additionally, the functionality of the C515C-8E has been upgraded by two features : - the wake-up from software power down mode can, additionally to the external pin P3.2/INT0 wake-up capability, also be triggered alternatively by a second pin P4.7/RXDC. - for power consumption reasons the on-chip CAN controller can be switched off during normal operating mode of the C515C-8E. This document describes in detail the C515C-8E programming interface. The description of the detailed microcontroller functions of the C515C is given in the "C515C User's Manual 08.96". Semiconductor Group 2 Addendum V1.0 05.97 C515C-8E 2 2.1 Extended Functionality of the C515C-8E Second Pin for Wake-up from Software Power Down Additionally to pin P3.2/INT0 of the C515C-8R, the C515C-8E provides a second pin (P4.7/RXDC) which can be used alternatively for the wake-up from software power down mode operation. The selection of the port pin for the wake-up function is controlled by bit WS in SFR PCON1. PCON1 is a mapped SFR at address 88H and can only be accessed when bit RMAP (bit 4 in SFR SYSCON (B1H)) is set. See pages 9-7 and 9-8 of the C515C User's Manual 08.96 for detailed description of the wake-up sequence. The timing for the wake-up sequence of pin P4.7/RXDC is identical to the timing for pin P3.2/INT0. Special Function Register PCON1 (Mapped Address 88H) Bit No. 88H MSB 7 EWPD Reset Value : 0XX0XXXXB LSB 0 - PCON1 6 - 5 - 4 WS 3 - 2 - 1 - Symbol EWPD Function External wake-up from power down enable bit Setting EWPD before entering software power down mode, enables the external wake-up from software power down mode capability of the C515C8E. Wake-up from software power down mode source select WS = 0 : wake-up via pin P3.2/INT0 selected (default after reset) WS = 1 : wake-up via pin P4.7/RXDC selected Reserved bits for future use. Read by CPU returns undefined values. WS - Semiconductor Group 3 Addendum V1.0 05.97 C515C-8E 2.2 Switch-off Capability of the CAN Controller For power consumption reasons the on-chip CAN controller can be switched off during normal operating mode of the C515C-8E by setting bit CSWO in SFR SYSCON. When the CAN controller is switched off its clock signal is turned off and the operation of the CAN controller is stopped. This switch-off state of the CAN controller is equal to its state in software power down mode. Any message transfer is interrupted. In order to ensure that the CAN controller is not stopped while sending a dominant level ("0") on the CAN bus, the microcontroller should set bit INIT in the Control Register prior to setting bit CSWO. The C515C-8E can check, if a transmission is in progress by reading bits TXRQ and NEWDAT in the message objects and bit TXOK in the Control Register. After clearing bit CSWO again the CAN controller has to be reconfigured. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H - Reset Value : XX100001B LSB 0 SYSCON 6 5 4 RMAP 3 - 2 1 PMOD EALE CSWO XMAP1 XMAP0 The functions of the shaded bits are not described in this section. Bit - CSWO Function Reserved bits for future use. Read by CPU returns undefined values. CAN controller switch-off bit CSWO = 0 : CAN controller is enabled (default after reset). CSWO = 1 : CAN controller is switched off. When the C515C-8E is put into software power down mode, bit CSWO is not affected. This means, when software power down mode is entered with CAN controller switched off, the CAN controller stays in switch-off state after the wake-up from software power down mode has been left*. Semiconductor Group 4 Addendum V1.0 05.97 C515C-8E 3 Programming Configuration During normal program execution the C515C-8E behaves like the C515C-8R/C515C-L. For programming of the device, the C515C-8E must be put into the programming mode. This typically is done not in-system but in a special programming hardware. In the programming mode the C515C-8E operates as a slave device similar as an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5 V programming voltage. In the programming mode port 0 provides the bidirectional data lines and port 2 is used for the multiplexed address inputs. The upper address information at port 2 is latched with the signal PALE. For basic programming mode selection the inputs RESET, PSEN, EA/VPP, ALE, PMSEL1/0, and PSEL are used. Further, the inputs PMSEL1,0 are required to select the access types (e.g. program/verify data, write lock bits, ....) in the programming mode. In programming mode VCC/VSS and a clock signal at the XTAL pins must be applied to the C515C-8E. The 11.5 V external programming voltage is applied to the EA/VPP pin. Figure 1 shows the pins of the C515C-8E which are required for controlling of the OTP programming mode. VCC VSS A0-A7 / A8-A13 PALE PMSEL0 PMSEL1 Port 2 Port 0 D0-D7 EA/VPP PROG PRD RESET C515C-8E XTAL1 XTAL2 PSEN PSEL Figure 1 Programming Mode Configuration Semiconductor Group 5 Addendum V1.0 05.97 C515C-8E 3.1 Pin Configuration of OTP Programming Mode Figure 2 shows the detailed pin configuration (P-MQFP-44-2 package) of the C515C-8E in programming mode. RESET N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VCC PMSEL0 PMSEL1 PSEL PRD PALE N.C. 80 1 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS N.C. VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. 75 70 65 61 60 5 55 10 C515C-8E 50 15 45 20 21 25 30 35 41 40 N.C. D7 D6 D5 D4 D3 D2 D1 D0 VSS VCC EA/VPP PROG PSEN N.C. A7 / A15 A6 / A14 A5 / A13 A4 / A12 A3 / A11 Figure 2 Pin Configuration of the C515C-8E in OTP Programming Mode (Top View) Semiconductor Group N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VCC VCC VSS VSS XTAL2 XTAL1 A0 / A8 A1 / A9 A2 / A10 6 Addendum V1.0 05.97 C515C-8E 3.2 Pin Definitions in OTP Programming Mode The following table 1 contains the functional description of all C515C-8E pins which are required for OTP memory programming Table 1 Pin Definitions and Functions in Programming Mode Symbol RESET Pin Number 1 I/O*) Function I Reset This input must be at static "0" (active) level during the whole programming mode. Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PMSEL1 0 0 1 1 PSEL 17 I PMSEL0 0 1 0 1 Access Mode Reserved Read version bytes Program/read lock bits Program/read OTP memory byte PMSEL0 PMSEL1 15 16 I I Basic programming mode select This input is used for the basic programming mode selection and must be switched according figure 3. Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. Programming address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level whenever the logic level of PMSEL1,0 is changed. XTAL2 Input to the oscillator amplifier. XTAL1 Output of the inverting oscillator amplifier. Address lines P2.0-7 are used as multiplexed address input lines A0-A7 and A8-A15. A8-A15 must be latched with PALE. PRD 18 I PALE 19 I XTAL2 XTAL1 A0/A8 A7/A15 36 37 38 - 45 I O I *) I = Input O = Output Semiconductor Group 7 Addendum V1.0 05.97 C515C-8E Table 1 Pin Definitions and Functions in Programming Mode (cont'd) Symbol PSEN Pin Number 47 I/O*) Function I Program store enable This input must be at static "0" level during the whole programming mode. Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations. During basic programming mode selection a low level must be applied to PROG. External Access / Programming voltage This pin must be at 11.5 V (VPP) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation this pin must be at high level (VIH). This pin is also used for basic programming mode selection. At basic programming mode selection a low level must be applied to EA/VPP. Data lines 0-7 During programming mode, data bytes are read or written from or to the C515C-8E via the bidirectional D0-7 which are located at port 0. Circuit ground potential must be applied to these pins in programming mode. Power supply terminal must be applied to these pins in programming mode. Not Connected These pins should not be connected in programming mode. PROG 48 I EA/VPP 49 I D0 - 7 52 - 58 I/O VSS VCC N.C. 13, 34, 35, 51, 70 14, 32, 33, 50, 69 - - 2-12, 20-31, - 46, 60-67, 69, 71-80 *) I = Input O = Output Semiconductor Group 8 Addendum V1.0 05.97 C515C-8E 4 Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts : - Basic programming mode selection - Access mode selection With the basic programming mode selection the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic. Further, after selection of the basic programming mode, OTP memory accesses are executed by using one of the access modes. These access modes are OTP memory byte program/read, version byte read, and program/read lock byte operations. 4.1 Basic Programming Mode Selection The basic programming mode selection scheme is shown in figure 3. VCC Clock (XTAL1/XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA 5V stable "0" "0" 0,1 "0" "1" "0" EA/VPP AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA 0V VPP VIH Ready for access mode selection During this period signals are not actively driven Figure 3 Basic Programming Mode Selection Semiconductor Group 9 Addendum V1.0 05.97 C515C-8E The basic programming mode is selected by executing the following steps : - With a stable VCC and a clock signal applied to the XTAL pins; the RESET and PSEN pins are set to "0" level. - PROG, PALE, PMSEL1 and EA/VPP are set to "0" level; PRD, PSEL, and PMSEL0 are set to "1" level. - PSEL is set to from "1" to "0" level and thereafter PROG is switched to "1" level. - PMSEL1,0 can now be changed; after EA/VPP has been set to VIH high level or to VPP the OTP memory is ready for access. The pins RESET and PSEN must stay at static "0" signal level during the whole programming mode. With a falling edge of PSEL the logic state of PROG and EA/VPP is internally latched. These two signals are now used as programming write pulse signal (PROG) and as programming voltage input pin VPP. After the falling edge of PSEL, PSEL must stay at "0" state during all programming operations. 4.2 OTP Memory Access Mode Selection When the C515C-8E has been put into the programming mode using the basic programming mode selection, several access modes of the OTP memory programming interface are available. The conditions for the different control signals of these access modes are listed in table 2. Table 2 Access Modes Selection Access Mode Program OTP memory byte Read OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte EA/ VPP VPP VIH VPP VIH VIH H H L H Byte addr. of sign. byte H H H L PROG PRD H PMSEL 1 H 0 H Address (Port 2) A0-7 A8-15 - Data (Port 0) D0-7 D1,D0 see table 3 D0-7 The access modes from the table above are basically selected by setting the two PMSEL1,0 lines to the required logic level. The PROG and PRD signal are the write and read strobe signal. Data is transferred via port 0 and addresses are applied to port 2. The following sections describe the details of the different access modes. Semiconductor Group 10 Addendum V1.0 05.97 C515C-8E 4.2.1 Program / Read OTP Memory Bytes The program/read OTP memory byte access mode is defined by PMSEL1,0 = 1,1. It is initiated when the PMSEL1,0 = 1,1 is valid at the rising edge of PALE. With the falling edge of PALE the upper addresses A8-A15 of the 16-bit OTP memory address are latched. After A8-A15 has been latched, A0-A7 is put on the address bus (port 2). A0-A7 must be stable when PROG is low or PRD is low. If subsequent OTP address locations are accessed with constant address information at the high address lines A8-15, A8-A15 must only be latched once (page address mechanism). Figure 4 shows a typical OTP memory programming cycle with a following OTP memory read operation. In this example A0-A15 of the read operation are identical to A8-A15 of the preceeding programming operation. PMSEL1,0 AAAAAA A A AAAAAA A AAAAAA A AAAAAA A AAAAAA AAAAAA A A AAAAAA A AAAAAA 1, 1 A8A15 Port 2 A0-A7 PALE D0-D7 min. 100 s PROG min. 100 ns D0-D7 Port 0 PRD Figure 4 Programming / Verify OTP Memory Access Waveform If the address lines A8-A15 must be updated, PALE must be activated for the latching of the new A8A15 value. Control, address, and data information must only be switched when the PROG and PRD signals are at high level. The PALE high pulse must always be executed if a different access mode has been used prior to the actual access mode. Semiconductor Group 11 Addendum V1.0 05.97 C515C-8E Figure 5 shows a waveform example of the program/read mode access for several OTP memory bytes. In this example OTP memory locations 3FDH to 400H are programmed. Thereafter, OTP memory locations 400H and 3FDH are read. PMSEL1,0 PALE Port 2 Port 0 PROG PRD AAAAA AAAAA AAAAA AAAAA 1, 1 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA 03 AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA 3FD FD 3FE FE 3FF FF 04 400 00 400 00 03 3FD FD AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Data 1 Data 2 AAAAAAA Data 3 AAAAAAA AAAAAAA AAAAAAA Data 4 AAAAA AAAAAAAAAAA AAAAA Data 4 AAAAAAAAAAAData 1 AAAAAAAAAAA AAAAA AAAAA AAAAAAAAAAA Figure 5 Typical OTP Memory Programming/Verify Access Waveform Semiconductor Group 12 Addendum V1.0 05.97 C515C-8E 4.2.2 Lock Bits Programming / Read The C515C-8E has two programmable lock bits which, when programmed according table 3, provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can also be read. Table 3 Lock Bit Protection Types Lock Bits at D1,D0 D1 1 1 D0 1 0 Protection Protection Type Level Level 0 Level 1 The OTP lock feature is disabled. During normal operation of the C515C-8E, the state of the EA pin is not latched on reset. During normal operation of the C515C-8E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible according to ROM verification mode 2, as it is defined for a protected ROM version of the C515C-8R (see OTP verification mode 2 on page 27). Further programming of the OTP memory is disabled (reprogramming security). Same as level 1, but also OTP memory read operation using ROM verification mode 2 is disabled. Same as level 2; but additionally external code execution by setting EA=low during normal operation of the C515C-8E is no more possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the ROM boundary), is still possible. 0 0 1 0 Level 2 Level 3 Note : A 1 means that the lock bit is unprogrammed. 0 means that lock bit is programmed. For a OTP verify operation at protection level 1, the C515C-8E must be put into the ROM verification mode 2. This mode is selected as defined in the C515C User' Manual 08.96 at pages 4-11 and 4-12. If a device is programmed with protection level 2 or 3, it is no more possible to verify the OTP content of a customer rejected (FAR) OTP device. When a protection level has been activated by programming of the lock bits, the basic programming mode must be left for activation of the protection mechanisms. This means, after the activation of a protection level further OTP program/verify operations are still possible if the basic programming mode is maintained. Figure 6 shows the waveform of a lock bit write/read access. For a simple drawing, the PROG pulse is shortened. In reality, for Lock Bit programming, a 100s PROG low puls must be applied. Semiconductor Group 13 Addendum V1.0 05.97 C515C-8E PMSEL1,0 PALE Port 0 PROG PRD AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA 1, 0 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA (D1,D0) AAAAAAA 1,0 AA AAAAAA AAAA AAAAAA 1,0 AAAAAA AAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA The example shows the programming and reading of a protection level 1. Figure 6 Write/Read Lock Bit Waveform Semiconductor Group 14 Addendum V1.0 05.97 C515C-8E 4.2.3 Access of Version Bytes The C515C-8E provides three version bytes at address locations FCH, FDH, and FEH. The information stored in the version bytes, is defined by the mask of each microcontroller step, Therefore, the version bytes can be read but not written. The three version bytes hold information as manufacturer code, device type, and stepping code. For reading of the version bytes the control lines must be used according table 2 and figure 7. The address of the version byte must be applied at the port 1 address lines. PALE must not be activated. PMSEL1,0 PALE Port 2 Port 0 PROG PRD AAAAAAA AAAAAAA AAAAAAA AAAAAAA 0, 1 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA FC FD FE AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAAAAA AAAAAAAAAAA VR0 AAAAAA VR1 AAAAA VR2 AAAAAA AAAAA AAAAAA AAAAAA AAAAAAAAAAA AAAAAA AAAAA AAAAAA AAAAAAAAAAA AAAAAA AAAAA AAAAAA VRx means content of version byte x. Figure 7 Read Version Byte(s) Waveform Version bytes are typically used by programming systems for adapting the programming firmware to specifc device characteristics such as OTP size etc. Note: The 3 version bytes are implemented in a way that they can be also read during normal program execution mode as a mapped SFR when bit RMAP in SFR SYSCON is set. The SFR addresses of the version bytes in normal mode are identical to the addresses which are used in programming mode. Therefore, in normal operating mode of the C515C-8E, the SFR locations which hold the signature bytes are also referenced as version registers. The first step of the C515C-8E will contain the following information at the signature bytes : Name Version Byte 0 = Version Register 0 Version Byte 1 = Version Register 1 Version Byte 2 = Version Register 2 Address FCH FDH FEH Value C5H 95H 01H Future steppings of the C515C-8E will typically have a different version byte 2 (incremented value). Semiconductor Group 15 Addendum V1.0 05.97 C515C-8E 5 5.1 Device Specifications Absolute Maximum Ratings Ambient temperature under bias (TA) .............................................................. 0 C to + 110 C Storage temperature (TST)................................................................................- 65 C to + 150 C Voltage on VCC pins with respect to ground (VSS) ............................................- 0.5 V to 6.5 V Voltage on any pin with respect to ground (VSS) ..............................................- 0.5 V to VCC + 0.5 V Input current on any pin during overload condition ..........................................- 10 mA to + 10 mA Absolute sum of all input currents during overload condition ..........................| 100 mA | Power dissipation.............................................................................................TBD Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Semiconductor Group 16 Addendum V1.0 05.97 C515C-8E 5.2 DC Characteristics VCC = 5 V + 10%, - 15%; VSS = 0 V TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C Limit Values min. max. for the SAB-C515C-8E for the SAF-C515C-8E for the SAH-C515C-8E Unit Test Condition Parameter Input low voltages all exc. EA/VPP, RESET, HWPD EA/VPP pin RESET and HWPD pins Port 5 in CMOS mode Input high voltages all except XTAL2, RESET, and HWPD) XTAL2 pin RESET and HWPD pins Port 5 in CMOS mode Symbol VIL VIL1 VIL2 VILC - 0.5 - 0.5 - 0.5 - 0.5 0.2 VCC - 0.1 V 0.2 VCC - 0.3 V 0.2 VCC + 0.1 V 0.3 VCC V - - - - VIH VIH1 VIH2 VIHC 0.2 VCC + 0.9 0.7 VCC 0.6 VCC 0.7 VCC - - - 2.4 0.9 VCC 2.4 0.9 VCC 0.9 VCC 0.9 VCC - 10 - 65 VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.45 0.45 0.45 - - - - - - - 70 - 650 V V V V V V V V V V V V V A A - - - - Output low voltages Ports 1, 2, 3, 4, 5, 7 (incl. CMOS) VOL VOL1 Port 0, ALE, PSEN, CPUR P4.1, P4.3 in push-pull mode VOL3 Output high voltages Ports 1, 2, 3, 4, 5, 7 Port 0 in external bus mode, ALE, PSEN, CPUR Port 5 in CMOS mode P4.1, P4.3 in push-pull mode Logic 0 input current Ports 1, 2, 3, 4, 5, 7 Logical 0-to-1 transition current Ports 1, 2, 3, 4, 5, 7 Input leakage current Port 0, EA/VPP, P6, HWPD, AIN0-7 Input low current To RESET for reset XTAL2 PE/SWD Pin capacitance Overload current Programming voltage IOL = 1.6 mA 1) IOL = 3.2 mA 1) IOL = 3.75 mA 1) IOH = - 80 A IOH = - 10 A) IOH = - 800 A 2) IOH = - 80 A 2) IOH = - 800 A IOH = - 833 A VIN = 0.45 V VIN = 2 V VOH VOH2 VOHC VOH3 IIL ITL ILI ILI2 ILI3 ILI4 CIO IOV VPP - - - - - - 10.9 1 - 100 - 15 - 20 10 A A A A pF mA V 0.45 < VIN < VCC VIN = 0.45 V VIN = 0.45 V VIN = 0.45 V fc = 1 MHz, TA = 25 C 7) 8) 5 12.1 11.5 V 5% Semiconductor Group 17 Addendum V1.0 05.97 C515C-8E Parameter Symbol Limit Values typ. 9) max. TBD TBD TBD TBD 50 30 Unit Test Condition Power supply current: Active mode, 6 MHz 6) Idle mode, 6 MHz 6) Active mode, 10 MHz 6) Idle mode, 10 MHz 6) Power-down mode Power supply current at EA/VPP in programming mode ICC ICC ICC ICC IPD ICCP TBD TBD TBD TBD - - mA mA mA mA A mA VCC = 5 V, 4) VCC = 5 V, 5) VCC = 5 V, 4) VCC = 5 V, 5) VCC = 2...5.5 V3) 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = RESET = Port 0 = Port 6 = V CC ; XTAL1 = N.C.; XTAL2 = V SS ; PE/SWD = V SS ; HWPD = V CC ; VAGND = VSS ; VAREF = VCC ; all other pins are disconnected. IPD (hardware power-down mode) is independent of any particular pin connection. 4) ICC (active mode) is measured with: XTAL2 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL1 = N.C.; EA = PE/SWD = Port 0 = Port 6 = VCC ; HWPD = VCC ; RESET = VSS ; all other pins are disconnected. 5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL1 = N.C.; RESET = VCC ; EA = VSS ; Port0 = VCC ; all other pins are disconnected; 6) ICC max at other frequencies is given by: active mode: TBD idle mode: TBD where fosc is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5 V. 7) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 8) Not 100% tested, guaranteed by design characterization 9) The typical ICC values are periodically measured at TA = +25 C but not 100% tested. Semiconductor Group 18 Addendum V1.0 05.97 C515C-8E 5.3 A/D Converter Characteristics VCC = 5 V + 10%, - 15%; VSS = 0 V TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C for the SAB-C515C-8E for the SAF-C515C-8E for the SAH-C515C-8E 4 V VAREF VCC+0.1 V ; VSS-0.1 V VAGND VSS+0.2 V Parameter Analog input voltage Sample time Conversion cycle time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Notes see next page. Symbol Limit Values min. max. Unit V ns ns LSB Test Condition 1) VAIN tS tADCC TUE VAGND - - - - - - VAREF 16 x tIN 8 x tIN 96 x tIN 48 x tIN 2 - 0.25 Prescaler / 8 Prescaler / 4 Prescaler / 8 Prescaler / 4 2) 3) VSS+0.5V VIN VCC-0.5V 4) RAREF RASRC CAIN tADC / 250 k tS / 500 - 0.25 50 pF k tADC in [ns] tS in [ns] 6) 5) 6) 2) 6) Clock calculation table : Clock Prescaler Ratio /8 /4 1 0 ADCL tADC 8 x tIN 4 x tIN tS 16 x tIN 8 x tIN tADCC 96 x tIN 48 x tIN Further timing conditions : tADC min = 500 ns tIN = 1 / fOSC = tCLP Semiconductor Group 19 Addendum V1.0 05.97 C515C-8E Notes: 1) V AIN may exeed V AGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE is tested at V AREF = 5.0 V, VAGND = 0 V, V CC = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization. Semiconductor Group 20 Addendum V1.0 05.97 C515C-8E 5.4 AC Characteristics VCC = 5 V + 10%, - 15%; VSS = 0 V TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C for the SAB-C515C-8E for the SAF-C515C-8E for the SAH-C515C-8E (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values 10-MHz clock Duty Cycle 0.4 to 0.6 min. ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN *) Unit Variable Clock 1/CLP = 2 MHz to 10 MHz min. CLP - 40 max. - ns ns ns ns ns ns max. - - - 113 - - 75 - 30 - 180 tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ *) tPXAV *) tAVIV tAZPL 60 15 15 - 20 115 - 0 - 35 - 0 TCLHmin -25 - TCLHmin -25 - - 2 CLP - 87 TCLLmin -20 - - CLP+ TCLHmin -30 - 0 - TCLLmin - 5 - 0 ns CLP+ TCLHmin- 65 - ns TCLLmin -10 ns - ns ns 2 CLP + TCLHmin -60 - ns Interfacing the C515C to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group 21 Addendum V1.0 05.97 C515C-8E External Data Memory Characteristics Parameter Symbol 10-MHz clock Duty Cycle 0.4 to 0.6 min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 150 Limit Values Variable Clock 1/CLP= 2 MHz to 10 MHz Unit min. 3 CLP - 70 3 CLP - 70 CLP - 15 - 0 max. - - - 2 CLP+ TCLHmin - 90 - CLP - 20 4 CLP - 133 4 CLP + TCLHmin -155 CLP+ TCLLmin+ 50 - TCLHmin + 25 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 230 230 48 - 0 - - - 90 103 15 5 218 13 - 80 267 285 190 - 65 - - - 0 - - - CLP + TCLLmin - 50 2 CLP - 97 TCLHmin - 25 TCLLmin - 35 - 3 CLP + TCLLmin - 122 TCLHmin - 27 - - 0 Semiconductor Group 22 Addendum V1.0 05.97 C515C-8E SSC Interface Characteristics Parameter Clock Cycle Time : Master Mode Slave Mode Clock high time Clock low time Data output delay Data output hold Data input setup Data input hold TC bit set delay Symbol min. Limit Values max. - - - - 100 - - - 8 CLP s s ns ns ns ns ns ns ns 0.8 1.0 360 360 - 0 100 100 - Unit tSCLK tSCLK tSCH tSCL tD tHO tS tHI tDTC External Clock Drive at XTAL2 Parameter Symbol CPU Clock = 10 MHz Duty cycle 0.4 to 0.6 min. Oscillator period High time Low time Rise time Fall time Oscillator duty cycle Clock cycle CLP TCLH TCLL 100 40 40 - - 0.4 40 max. 100 - - 12 12 0.6 60 Variable CPU Clock 1/CLP = 2 to 10 MHz min. 100 40 40 - - 40 / CLP CLP * DCmin max. 500 CLP-TCLL CLP-TCLH 12 12 1 - 40 / CLP CLP * DCmax ns ns ns ns ns - ns Unit tR tF DC TCL Note: The 10 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. Semiconductor Group 23 Addendum V1.0 05.97 C515C-8E Program Memory Read Cycle Data Memory Read Cycle Semiconductor Group 24 Addendum V1.0 05.97 C515C-8E Data Memory Write Cycle External Clock Cycle Semiconductor Group 25 Addendum V1.0 05.97 C515C-8E Notes : Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid for the other cases accordingly. In the case of slave mode and CPHA=0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). In the case of master mode and CPHA=0, the MSB becomes valid after the data has been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition. SSC Timing Semiconductor Group 26 Addendum V1.0 05.97 C515C-8E OTP Verification Mode 2 (for Memory Verification in OTP Protection Level 1) Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ CLP 6 CLP - - max. - - 2 CLP - - 6 ns ns ns ns ns MHz - - - 4 CLP - 4 Unit tAWD tACY tDVA tDSA tAS 1/ CLP tCL - ROM/OTP Verification Mode 2 Semiconductor Group 27 Addendum V1.0 05.97 C515C-8E 5.5 OTP Memory Programming Mode Characteristics VCC = 5 V 10 %; VPP = 11.5 V 5 %; Parameter ALE pulse width PMSEL setup to ALE rising edge TA = 25 C 10 C Symbol min. Limit Values max. - - - - - - - - - - 75 20 - 20 - ns ns ns ns ns ns s ns ns ns ns ns s ns ns ns 35 10 10 10 100 0 10 10 100 100 - - 0 - 1 100 TBD Unit tPAW tPMS tPAS tPAH tPCS tPCH tPMS tPMH tPWW tPRW tPAD tPRD tPDH tPDF tPWH1 tPWH2 tCLKP Address setup to ALE, PROG, or PRD falling edge Address hold after ALE, PROG, or PRD falling edge Address, data setup to PROG or PRD Address, data hold after PROG or PRD PMSEL setup to PROG or PRD PMSEL hold after PROG or PRD PROG pulse width PRD pulse width Address to valid data out PRD to valid data out Data hold after PRD Data float after PRD PROG high between two consecutive PROG low pulses PRD high between two consecutive PRD low pulses XTAL clock period Semiconductor Group 28 Addendum V1.0 05.97 C515C-8E tPAW PALE tPMS PMSEL1,0 AAAAAA A AAAAAA A A AAAAAA AAAAAA A AAAAAA A AAAAAA A AAAAAA A H, H tPAS Port 2 AAAAAAAAAAAAAA A AAAAAAAAAAAAAA A AAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAA A AAAAAAAAAAAAAA A AA AAAAAAAAAAAAAA A tPAH A0-7 AAAA AAA AA AAA AA AAAA AAA AA AAAA AAAA AAA AA AAAA AAA AA AAA AA AAAA AAA AA AAAA A8-13 Port 0 D0-7 tPWW PROG tPWH tPCS Notes : PRD must be high during a programming write cycle tPCH Figure 8 Programming Code Byte - Write Cycle Timing Semiconductor Group 29 Addendum V1.0 05.97 C515C-8E tPAW PALE tPMS PMSEL1,0 AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA H, H tPAS AA AAAAAAAAAAAAAAA Port 2 AAAAAAAAAAAAAAA A8-13 AAAAAAAAAAAAAA AA AAA AAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AA tPAH A0-7 AA AA AAAAAA AA AAAA AA AAAAAA AA AAAAAA AAAAAA AA AA AAAAAA AA AAAAAA tPAD Port 0 D0-7 tPDH tPRD PRD tPDF tPWH tPCS tPRW Notes : PROG must be high during a programming read cycle tPCH Figure 9 Verify Code Byte - Read Cycle Timing Semiconductor Group 30 Addendum V1.0 05.97 C515C-8E PMSEL1,0 AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA H, L AAAAAA A AA AA AAAAAA A AAAAAA A AA A AA AAAAAA AAAAAA A AA AA AAAAAA A A AA AAAAAA H, L AAAAA AA AA AAAAA AAAAA AA AA AAAAA AAAAA AA AA AAAAA AA AAAAA Port 0 D0, D1 D0, D1 tPCS tPMS PROG tPCH tPMH tPRD tPWW tPMS tPDH tPDF tPMH PRD tPRW Note : PALE should be low during a lock bit read/write cycle Figure 10 Lock Bit Access Timing PMSEL1,0 AAA AAAAAAA AAAAAAA AAA AAAAAAA AAA AAA AAAAAAA AAAAAAA AAA AAA AAAAAAA AAAAAAA AAA AAAAAAA AAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAAA AAA AAAAAAAAAA AAA AAAAAAAAAA AAA AAAAAAAAAA AAA AAAAAAAAAA AAA AA L, H AA AAAAAAA AA AAAAAAA AA AAAAAAA AA AAAAAAA AA AAAAAAA AA AAAAAAA AA AAAAAAA AA AAAAAAA AA AAAAAAAAAA AA AAAAAAAAAA AA AAAAAAAAAA AA AAAAAAAAAA AA AAAAAAAAAA AA AAAAAAAAAA AA AAAAAAAAAA Port 2 e.g. FDH tPCH D0-7 Port 0 tPCS tPMS PRD tPRD tPDH tPDF tPMH tPRW Note : PROG must be high during a programming read cycle Figure 11 Version Byte - Read Timing Semiconductor Group 31 Addendum V1.0 05.97 C515C-8E AC Inputs during testing are driven at VCC - 0.5 V for a logic '1' and 0.45 V for a logic '0'. Timing measurements are made at VIHmin for a logic '1' and VILmax for a logic '0'. AC Testing: Input, Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA AC Testing : Float Waveforms Crystal / Resonator Oscillator Mode Driving from External Source C XTAL1 2 - 10 MHz C XTAL2 XTAL2 External Oscillator Signal N.C. XTAL1 Crystal Mode : C = 20 pF 10 pF (incl. stray capacitance) Resonator Mode : C = depends on selected ceramic resonator Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 32 Addendum V1.0 05.97 C515C-8E 5.6 Package Information Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Pack) SMD = Surface Mounted Device P-MQFP-80-1 Package Outline Dimensions in mm Semiconductor Group 33 Addendum V1.0 05.97 C515C-8E 6 Addendum Table 4 Cross Reference of Pins in Normal/Programming Mode Pin Number 1 15 16 17 18 19 36 37 38 - 45 47 48 49 52 - 59 Pin in Normal Mode RESET PMSEL0 PMSEL1 PSEL PRD PALE XTAL2 XTAL1 A0/A8 - A7/A15 PSEN PROG EA/VPP D0 - D7 Pin in Programming Mode RESET P3.0 P3.1 P3.2 P3.3 P3.4 XTAL2 XTAL1 P2.0 - P2.7 PSEN ALE EA P0.0 - P0.7 Semiconductor Group 34 Addendum V1.0 05.97 |
Price & Availability of M515C8E
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |