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MITSUBISHI LSIs
1998.6.18 Ver.A
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M512R88DJ is a family of 131072-word by 8-bit static RAMs, fabricated with the high performance CMOS A0 1 A1 2 inputs application. A2 3 A3 4 These devices operate on a single 3.3V supply, and are chip select S5 input directly TTL compatible. They include a power down inputs/ DQ1 6 data DQ2 7 feature as well. outputs (3.3V) VCC 8 (0V) GND 9 FEATURES data DQ3 10 *Fast access time M5M512R88DJ-10 ... 10ns(max) inputs/ DQ4 11 M5M512R88DJ-12 ... 12ns(max) outputs M5M512R88DJ-15 ... 15ns(max) write control W 12 input *Low power dissipation Active .................... 297mW(typ) A4 13 address A5 14 inputs *Single +3.3V power supply A6 15 *Fully static operation : No clocks, No refresh A7 16 *Common data I/O *Easy memory expansion by S *Three-state outputs : OR-tie capability Outline *OE prevents data contention in the I/O bus *Directly TTL compatible : All inputs and outputs silicon gate process and designed for high speed address A16 A15 inputs 30 A14 29 A13 output enable 28 OE input data 27 DQ8 inputs/ 26 DQ7 outputs 25 GND (0V) 24 VCC (3.3V) data 23 DQ6 inputs/ 22 DQ5 outputs 21 A12 20 A11 address 19 A10 inputs 18 A9 17 A8
32 31 address
PIN CONFIGURATION (TOP VIEW)
32P0K
APPLICATION
High-speed memory units
PACKAGE
M5M512R88DJ : 32pin 400mil SOJ
BLOCK DIAGRAM
A0 A1 A2
address inputs
1 2 3 4
MEMORY ARRAY 512 ROWS 2048 COLUMNS
6 7 10 11 22 23 26 27
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
data inputs/ outputs
A3
A4 13 A5 14 A6 15 A7 16 A8 17
COLUMN I/O CIRCUITS
S
5
COLUMN ADDRESS COLUMN DECODERS ADDRESS
8 24 9 25
W
12
DECODERS
COLUMN INPUT BUFFERS
VCC (3.3V)
OE 28
GND (0V)
18 19 20 21 29 30 31 32 A9 A10 A11 A12 A13 A14 A15 A16
address inputs
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M512R88DJ is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S are in an active state (S=L). When setting S at high level, the chip is in a nonselectable mode in which both reading and writing are disable. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time.
FUNCTION TABLE
S H L L L W X L H H OE X X L H Mode Non selection Write Read DQ High-impedance Din Dout High-impedance Icc Stand by Active Active Active
ABSOLUTE MAXIMUM RATINGS
Symbol V cc VI VO Pd Topr T stg
* Pulse
Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature
Conditions With respect to GND
Ratings - 2.0 * 4.6 ~ *~ VCC+0.5 - 2.0 - 2.0*~ VCC 1000 0 ~ 70 - 10 ~ 85 - 65 ~ 150
+10% - 5%
Unit V V V mW C C C
Ta=25C
Tstg(bias) Storage temperature(bias) Storage temperature
width5ns, In case of DC: - 0.5V
DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70C, Vcc=3.3V
Symbol VIH VIL VOH VOL II I OZ Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Condition
,unless otherwise noted)
Limits Min 2.0 2.4 0.4 2 2 Typ Max Vcc+0.3 0.8 Unit V V V V uA uA
I OH = - 4mA IOL = 8mA VI= 0 ~ Vcc VI(S)=VIH Output current in off-state VI/O= 0 ~ Vcc Active supply current (TTL level) VI(S)=VIL other inpus=VIH or VIL Output-open(duty 100%) 10ns cycle AC 12ns cycle 15ns cycle DC 10ns cycle AC 12ns cycle 15ns cycle DC
I CC1
90
I CC2
Stand by current (TTL level)
VI(S)=VIH VI(S)=Vcc0.2V other inputs VI0.2V or VI Vcc - 0.2V
180 170 160 100 60 55 50 30 10
mA
mA
I CC3
Stand by current
mA
Note 1: Direction for current flowing into an IC is positive (no mark).
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
CAPACITANCE (Ta=0~70C, Vcc=3.3V
Symbol CI CO Parameter Input capacitance Output capacitance
+10% -5%
,unless otherwise noted)
Test Condition Min Limit Typ Max 6 8 Unit pF pF
V I =GND, V I =25mVrms,f=1MHz V O=GND, V O=25mVrms,f=1MHz
Note 2: CI,CO are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS (Ta=0~70C, Vcc=3.3V (1)MEASUREMENT CONDITION
+10% -5%
,unless otherwise noted)
Input pulse levels .................................... VIH=3.0V, VIL=0.0V Input rise and fall time .................................................... 3ns Input timing reference levels ........................ VIH=1.5V, VIL=1.5V Output timing reference levels ................. VOH =1.5V, VOL=1.5V Output loads ........................................................ Fig.1,Fig.2
5.0V OUTPUT Z0=50 DQ RL=50 VL=1.5V DQ 255 480 5pF (including scope and JIG)
Fig.1 Output load
Fig.2 Output load for ten , t dis
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
(2)READ CYCLE
Limits
Symbol Parameter M5M512R88DJ -10 M5M512R88DJ -12 M5M512R88DJ -15 Unit
Min tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tv(A) tPU tPD
Read cycle time Address access time Chip select access time Output enable access time Output disable time after S high Output disable time after OE high Output enable time after S low Output enable time after OE low Data valid time after address change Power-up time after chip selection Power-down time after chip selection
Max
Min 12
Max
Min 15
Max ns 15 15 7 ns ns ns ns ns ns ns ns ns 15 ns
10 10 10 5 0 0 4 3 4 0 10 5 5
12 12 6 0 0 4 3 4 0 12 6 6 0 0 4 3 4 0
7 7
(3)WRITE CYCLE
Limits
Symbol Parameter M5M512R88DJ -10 M5M512R88DJ -12 M5M512R88DJ -15 Unit
Min tCW tw tsu(A)1 tsu(A)2 tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE)
Write cycle time Write pulse width Address setup time(W) Address setup time(S) Chip select setup time Data setup time Data hold time Write recovery time Output disable time after W low Output disable time after OE high Output enable time after W high Output enable time after OE low
Max
Min 12 10 0 0 10 6 0 0
Max
Min 15 12 0 0 12 7 0 0
Max ns ns ns ns ns ns ns ns 7 7 ns ns ns ns ns
10 9 0 0 9 5 0 0 0 0 0 0 9 5 5
0 0 0 0 10
6 6
0 0 0 0 12
tsu(A-WH) Address to W High
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle 1 A 0~16
VIH VIL
t CR
ta(A) tv(A) tv(A)
UNKNOWN DATA VALID PREVIOUS DATA VALID
DQ1~8
VOH VOL W=H S=L OE=L
Read cycle 2 (Note 3)
t CR
S
VIH VIL
ta(S) ten(S)
(Note 4)
tdis(S)
(Note 4)
DQ1~8
VOH VOL
UNKNOWN
DATA VALID
tPU
tPD
50% 50%
Icc
ICC1 ICC2 W=H OE=L
Note 3. Addresses valid prior to or coincident with S transition low. 4. Transition is measured 500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5) OE
VIH VIL
t CR
(Note 4)
ta(OE)
(Note 4)
tdis(OE)
ten(OE)
UNKNOWN DATA VALID
DQ1~8
VOH VOL W=H S=L
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (W control mode)
t CW
A 0~16 S
VIH VIL VIH VIL
(Note 6)
tsu(S)
(Note 6)
tsu(A-WH)
OE
VIH VIL
tsu(A)
tw(W)
trec(W)
W
VIH VIL
tsu(D)
th(D)
DQ1~8
(Input Data)
VIH VIL
DATA STABLE
tdis(W) tdis(OE)
(Note 4)
ten(OE) ten(W)
Hi-Z
(Note 4)
DQ1~8
(Output Data)
VOH VOL
Write cycle(S control)
t CW
A 0~16
VIH VIL
tsu(A)
tsu(S)
trec(W)
S
VIH VIL
tw(W)
W
VIH VIL
(Note 6) (Note 6)
tsu(D)
th(D)
DQ1~8
(Input Data)
VIH VIL
DATA STABLE
ten(S)
tdis(W)
(Note 4)
DQ1~8
(Output Data)
VOH VOL
(Note 4)
Hi-Z
(Note 7)
Note 6: Hatching indicates the state is don't care. 7: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance. 8: ten,tdis are periodically sampled and are not 100% tested.
MITSUBISHI ELECTRIC
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