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19-2434; Rev 1; 1/03
10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust
General Description
The MAX3910 is a 10.7Gbps transimpedance amplifier designed for SONET OC-192/SDH STM-64, DWDM, and 10Gbps systems employing optical amplifiers. Operating from a single +5V or -5.2V supply, it converts a photodiode current into a measurable differential voltage. This product has a linear gain for an input current up to 950AP-P and a soft-limiting feature that provides an increasing output swing for an input current up to the 3.5mAP-P overload. An offset adjust circuit and output-level monitors allow system threshold adjustments. Additional features include back-terminated 50 outputs and an integrated 200 filter resistor to bias the photodiode. The MAX3910 has a small-signal bandwidth of 9.1GHz and a small-signal transimpedance of 1.65k. The part achieves an input sensitivity of 15.5AP-P for a BER of 10-12, translating to an optical sensitivity of -19.3dBm for a PIN (r = 0.9, re = 6.6) photo detector and -28.8dBm for an APD (M = 8, = 0.9, re = 10) photo detector. The MAX3910 is fabricated in Maxim's in-house SiGe process and is available in die form. o 950AP-P Linear Range o 15.5AP-P Sensitivity o 3.5mAP-P Overload o 1.65k Transimpedance o 9.1GHz Bandwidth o 110mA Supply Current o Output Offset Adjustment o Soft-Limiting Beyond Linear Input Range o Single +5V or -5.2V Power Supply o ESD Protection
Features
MAX3910
Ordering Information
PART MAX3910U/D TEMP RANGE 0C to +85C PIN-PACKAGE Dice*
Applications
DWDM Systems OC-192/STM-64 Transmission Systems 10Gbps Systems Using Optical Amplifiers 10Gbps Optical Receivers
*Dice are designed to operate over a 0C to +100C junction temperature (TJ) range, but are tested and guaranteed at TA = +25C.
Typical Operating Circuit
VEE VCC
RFILT FILT
MON+
MON-
OUT+ PIN IN LIMITING AMPLIFIER MONIN
OUT -
MAX3910
CHF OSADJ
VEE
________________________________________________________________ Maxim Integrated Products
1
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10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust MAX3910
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC - VEE) ........................-0.5V to +6.0V Continuous Input Current (IN)............................................4.2mA Continuous Input Current (FILT) ........................................9.8mA Continuous Output Current (OUT+, OUT-) .........................35mA Voltage at CHF, FILT, MON+, MON-, MONIN, OSADJ ................................(VEE - 0.5V) to the lesser of +6.0V and (VCC + 0.5V) Storage Ambient Temperature Range (TSTG) ...-55C to +150C Die Attach Temperature ..................................................+400C Operating Temperature Range (Junction Temperature Range)......................-20C to +120C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 4.75V to 5.5V, TJ = 0C to +100C. Typical values are at VEE = -5.2V, VCC = GND, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Supply Current Supply Current Power-Supply Noise Rejection Input Bias Voltage IIN 450AP-P IIN = 1.0mAP-P IIN = 2.0mAP-P (Note 5) CHF open, IIN 450AP-P CHF = 0.1F, IIN 450AP-P RFILT To OUT+ or OUTTo VCC VOD VOS (Note 6) Outputs DC-coupled to 50 to VCC (Note 6) IIN = 7.5A DC IIN = 1.4mA DC VOSADJ 42 1.45 -1.3 -7 -10 15 -2.1 -1.375 VOSADJ = -0.4V, RL = 50 to VCC -1.25 -320 20 -0.4 -1.125 -250 165 1.40 SYMBOL IEE IEE PSNR CONDITIONS VEE2 open, Figure 1 (Note 3) VEE2 connected to negative supply, Figure 1 (Note 3) IIN 450AP-P, f 1MHz IIN 450AP-P, f 10MHz (Note 4) MIN TYP 95 110 23 22 VEE + 0.95 ZF ILIN 1.65 1.37 0.84 950 6 0.5 200 10 50 1.75 59 1.90 0 +7 +10 240 25 VEE + 1.1 1.87 k AP-P kHz k VP-P V mV k V V mV MAX 138 158 UNITS mA mA dB V
Transimpedance (Note 5) Linear Input Current Range Low-Frequency Cutoff Photodiode Filter Resistor Output Monitor Resistance Single-Ended Output Resistance Maximum Differential Output Swing Single-Ended Output Range Output DC Offset OSADJ Input Resistance OSADJ Input Range OSADJ Voltage for Zero Offset Minimum Differential Output Offset
450
2
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10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 4.75V to 5.5V, TJ = 0C to +100C. Typical values are at VEE = -5.2V, VCC = GND, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Maximum Output Offset OSADJ Voltage Control Factor: OUT+ OSADJ Voltage Control Factor: OUTSYMBOL CONDITIONS VOSADJ = -2.1V, RL = 50 to VCC (VOSADJ)/VOUT+ (VOSADJ)/VOUTMIN 250 -3 TYP 320 -2 2 3 MAX UNITS mV V/V V/V
MAX3910
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 4.75V to 5.5V, TJ = 0C to +100C. Typical values are at VEE = -5.2V, VCC = GND, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Bandwidth Input-Referred Noise Input Sensitivity Input Overload Gain Flatness Gain Ripple Deterministic Jitter (Notes 2, 10) Single-Ended Output Return Loss (Note 2) IOL SYMBOL BW3dB IN (Notes 2, 7) (Notes 2, 8) AC component (Note 9) DC component (Note 9) 100MHz - 4GHz, IIN 450AP-P (Note 2) 4GHz - BW3dB, IIN 450AP-P (Note 2) IIN 450AP-P 450AP-P IIN 2.5mAP-P 7.5GHz 2.5 1.4 CONDITIONS IIN 450AP-P (Notes 2, 11) MIN 8.2 TYP 9.1 1.1 15.5 3.5 1.8 0.75 1.5 6.2 7.5 10 10.7 14.6 1.62 MAX UNITS GHz ARMS AP-P mAP-P mA dB dB psP-P dB
Default test conditions: VEE2 and CHF = open (Figure 1), RL = 50 to VCC, DC-coupled at each output, unless otherwise noted. AC characteristics are guaranteed by design and characterization. Note 2: Source capacitance = 0.25pF, source series resistance = 20, and source series inductance = 0.6nH. Output series inductance = 0.5nH at each of the differential outputs. Note 3: Supply current increases as average signal level increases. Maximum supply current is specified for IIN = 1.4mA average current. Typical supply current is specified for IIN 225A average current. Note 4: PSNR is measured by detecting the differential output voltage VOUT while applying VEE = 55mVP-P signal on VEE1. PSNR = 20log(VEE/VOUT). Output offset adjust feature disabled. Note 5: Transimpedance is defined as VOUT(P-P) / IIN(P-P) at 10MHz. Linear range is defined as the input signal level where the transimpedance deviates from the small-signal transimpedance value by no more than 10% (Figure 2). Note 6: Input current 2.5mAP-P and 1.4mA DC. Note 7: Measured with a 4th-order Bessel-Thompson filter with a cutoff frequency of 8GHz. Note 8: Input sensitivity calculated from S/N 14.1 (BER 10-12). Note 9: For input signal less than or equal to the input overload, deterministic jitter is guaranteed to be within specifications. Note 10: Deterministic jitter is characterized with 27 - 1 PRBS + 80 zeros + 80 ones at 10.7Gbps. Note 11: Bandwidth is measured in an electrical environment and corrected to match the conditions of Note 2. Note 1:
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10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust MAX3910
Typical Operating Characteristics
(VEE = -5.2V, VCC = GND, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT
MAX3910 toc01
DETERMINISTIC JITTER
MAX3910 toc02
LINEAR RANGE
1600 DIFFERENTIAL OUTPUT (mVP-P) 1400 1200 1000 800 600 400 200 0 END OF LINEAR RANGE
MAX3910 toc03
11 10 9 8 7 6 5 450AP-P INPUT 0 10 20 30 40 50 60 70 80 2.5mAP-P INPUT
1800
125 SUPPLY CURRENT (mA) 115 105 95 85
VEE2 = OPEN
1.4mA DC INPUT
225A DC INPUT 75 65 -60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (C)
DETERMINISTIC JITTER (psP-P)
90
0
500
1000
1500
2000
2500
AMBIENT TEMPERATURE (C)
INPUT CURRENT (AP-P)
POWER-SUPPLY NOISE REJECTION
MAX3910 toc04
INPUT-REFERRED NOISE
1.35 INPUT-REFERED NOISE (ARMS) 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90
MAX3910 toc05
0 POWER-SUPPLY NOISE REJECTION (dB) 5 10 15 20 25 30 35 0 1 2 3 4 5 6 7 8 9
1.40
10
-60
-40
-20
0
20
40
60
80
100
FREQUENCY (MHz)
AMBIENT TEMPERATURE (C)
TRANSIMPEDANCE
1.6 TRANSIMPEDANCE (k) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 500 1000 1500 2000 2500 INPUT CURRENT (AP-P)
MAX3910 toc06
OFFSET ADJUST CIRCUIT
300 OUTPUT DC OFFSET (mV) 200 100 0 -100 -200 -300 -400 -2.25 -1.85 -1.55 -1.05 -0.65 -0.25 VOSADJ (V)
MAX3910 toc07
1.8
400
4
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10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust
Typical Operating Characteristics (continued)
(VEE = -5.2V, VCC = GND, TA = +25C, unless otherwise noted.)
ELECTRICAL EYE DIAGRAM (150AP-P INPUT) ELECTRICAL EYE DIAGRAM (1mAP-P INPUT)
MAX3910 toc09
MAX3910
MAX3910 toc08
ELECTRICAL EYE DIAGRAM (2.5mAP-P INPUT)
MAX3910 toc10
13ps/div
13ps/div
13ps/div
Pad Description
PAD 1, 8-16, 31, 32, 33 2 3, 4, 7 5 6 17 18, 19, 21, 23, 24, 26, 30 20 22 25 27 28 29 NAME VEE1 MONIN N.C. IN FILT VEE2 VCC OUTOUT+ CHF MONMON+ OSADJ Main Negative Power-Supply Voltage* Monitor Output Providing Replica Current from DC Offset Loop. Internally connected to VCC through 1k resistor. No Connection. Do not connect. Signal Input. Connected to photodiode anode. On-Chip Resistor for Photodiode Biasing. Internally connected to VCC through a 200 resistor. Separate Power Supply for Output Offset Adjustment. Leave open to disable this feature. Offset adjust feature must be disabled for AC-coupled load.* Positive Power-Supply Voltage* Inverted Data Output with 50 Back Termination Noninverted Data Output with 50 Back Termination Connect a capacitor to ground to increase the on-chip DC-cancellation loop time constant. Monitors DC Voltage at OUT-. Internally connected to OUT- through a 10k resistor. Monitors DC Voltage at OUT+. Internally connected to OUT+ through a 10k resistor. DC Offset Control. Voltage at this pad sets the output DC offset when the offset adjust feature is enabled. (See Figure 3.) FUNCTION
*The MAX3910 can operate with a positive supply (VEE = GND) or a negative supply (VCC = GND). 4.75V (VCC - VEE) 5.5V.
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10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust MAX3910
VCC VCC
MAX3910
VEE1 VCC
50
50 OUT+
RL = 50
FILT
200
OUT10k MON+
REF PIN 10k MONTIA IN VEE1 1.6pF 30k 1.2k DC-CANCELLATION LOOP AND CONTROL MONIN OSADJ gm 90k VCC VCC
RL = 50
-1.25V
CHF
VEE1
VEE2
VEE1
Figure 1. Functional Diagram
Detailed Description
Figure 1 is a functional diagram of the MAX3910 linear transimpedance amplifier. It comprises a transimpedance amplifier stage, a gain stage, an output buffer, and a DC-cancellation circuit. An output offset adjust circuit is implemented to perform threshold adjust for systems using optical amplifiers.
tor bonded between CHF and VCC can be used to further reduce the cutoff frequency. This circuit minimizes PWD for data sequences that exhibit a 50% duty cycle and mark density. A duty cycle or mark density significantly different from 50% causes the MAX3910 to generate PWD.
Voltage Amplifier
The single-ended signal from the transimpedance amplifier stage is converted to a differential signal and further amplified.
Transimpedance Amplifier
The photodiode current flows into the summing node of a high-gain amplifier and a shunt feedback resistor. A DC-cancellation circuit removes the average current, and the AC component is linearly converted into a voltage over a wide input range.
Output Buffer
In addition to having a wide linear range, the MAX3910 has a soft-limiting feature. For inputs less than 950AP-P, the MAX3910 operates linearly. Beyond this range, a soft-limiting feature is implemented so that the differential output swing is proportional to the input current, as shown in Figure 2. The output buffer is back-terminated with 50 on-chip resistors and can drive either a DCcoupled 50 load to VCC or a 50 AC-coupled load.
DC-Cancellation Loop
The DC-cancellation circuit uses low-frequency feedback to remove the DC component of the input signal. This feature centers the input signal within the transimpedance amplifier's linear range, thereby reducing pulse-width distortion (PWD) on large input signals. The DC-cancellation circuit has a built-in capacitor to achieve a low-frequency cutoff of 25kHz, and an external capaci6
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10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust
MONIN Pad
LINEAR RANGE
1600 DIFFERENTIAL OUTPUT (mVP-P) 1400 1200 1000 800 600 400 200 0 0 500 1000 1500 2000 2500 INPUT CURRENT (AP-P) END OF LINEAR RANGE
MAX3910 toc03
MAX3910
1800
The voltage at MONIN (VMONIN) serves as a received signal strength indicator (RSSI). The transimpedance gain of the average input current (IINAVE) to VMONIN is typically: VMONIN = 1000(V / A) IINAVE
Design Procedure
Power Supply
The MAX3910 requires wideband power-supply decoupling. Power-supply bypassing should provide low impedance between VEE1 and VCC for frequencies up to 10GHz. If the offset-adjust circuit is enabled, it is recommended that the same filtering be applied to VEE2.
Figure 2. Linear Range of the MAX3910
Photodiode Filter
Supply-voltage noise at the cathode of the photodiode produces a noise current I = CPD V/t, which reduces the receiver sensitivity (CPD is the photodiode capacitance). The MAX3910 contains an internal 200 resistor between the FILT pad and VCC. Combining this resistor with an external capacitor connected between the FILT pad and VEE1 creates a lowpass filter, which reduces photodiode noise current and improves receiver sensitivity. Current generated by supply-noise voltage is divided between the external capacitance and the photodiode capacitance. Assuming the filter capacitance is much larger than the photodiode capacitance, the input noise current because of supply noise is: INOISE = VNOISE x CPD RFILT x CFILT
Offset Adjust Circuit
Connecting VEE2 to the negative supply enables the offset adjust circuit. The circuit compares the external voltage applied to the OSADJ pad to an internal (VCC 1.25V) reference to introduce a DC offset at the differential outputs (Figure 3). This function is useful in systems that need threshold adjust. For AC-coupled loads, the circuit must be disabled. The input network of the offset adjust circuit creates a lowpass filter with a cutoff frequency of approximately 85MHz. If the pad is left unconnected, an internal voltage-divider sets the voltage at the pad to (V CC 1.25V). The input impedance is approximately 20k.
OFFSET ADJUST CIRCUIT
400 300 OUTPUT DC OFFSET (mV) 200 100 0 -100 -200 -300 -400 -2.25 -1.85 -1.55 -1.05 -0.65 -0.25 VOSADJ (V)
where CFILT is the external capacitance. If the amount of tolerable noise is known, the filter capacitance can be selected easily.
Wire Bonding
For high-current density and reliable operation, the MAX3910 uses gold metalization. Make connections to the die with gold wire only. Aluminum bonding is not recommended. Die thickness is typically 8 mils. Bondwire inductance between the photodiode and the IN pad can be optimized to obtain best performance. Higher inductance improves bandwidth, and lower bondwire inductance reduces time domain ringing. Keep bondwires on all other pads as short as possible to optimize performance. The backside of the MAX3910 die is fully insulated and can be connected to VCC or VEE.
Figure 3. Offset Adjust Circuit Behavior _______________________________________________________________________________________ 7
10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust MAX3910
Input Capacitance
Noise and bandwidth are adversely affected by capacitance on the MAX3910's input node. Use any techniques available to minimize input capacitance.
Optical Linear Range
The MAX3910 has high gain and operates in a linear range for inputs not exceeding: I x (r + 1) Linear range = 10log LIN e dBm 2 x (re - 1) where ILIN(mAP-P) is the peak-to-peak linear range.
Output-Coupling Capacitors
The outputs of the MAX3910 can be AC- or DC-coupled. For more information on selecting AC-coupling capacitors, visit Maxim's website and follow the links to HFAN01.1: Choosing AC-Coupling Capacitors.
Applications Information
Optical Power Relations
Many MAX3910 specifications relate to the input signal amplitude. When working with fiber optic receivers, the input sometimes is expressed in terms of average optical power and extinction ratio. Optical power relations are shown in Table 1 for an average mark density of 50% and an average duty cycle of 50%.
Table 1. Optical Power Relations*
PARAMETER Average Extinction Optical Power of a 1 Optical Power of a 0 Optical Modulation Amplitude SYMBOL PAVG re P1 P0 PIN-PACKAGE PAVG = (P0 + P1) / 2 re = P1 / P0 P1 = 2PAVG
re re +1
P0 = 2PAVG / (re + 1)
Optical Sensitivity Calculation
The MAX3910 input-referred RMS noise current (IN) generally determines receiver sensitivity. To obtain a system bit-error rate of 10-12, the signal-to-noise ratio must be 14.1 or better. The input sensitivity, expressed in average power, can be estimated as: 14.1 x IN x (re + 1) Sensitivity = 10log x 1000 dBm 2 x x (re - 1)
PIN
r -1 PIN = P1 - P0 = 2PAVG e re + 1
*Assuming a 50% average mark density.
P1
OPTICAL POWER
where is the photodiode responsivity in A/W, and IN is measured in amperes.
PAVG
PIN
Input Optical Overload
The overload is the largest input that the MAX3910 accepts while meeting specifications. Optical overload can be estimated in terms of average power with the following equation: I x (r + 1) Overload = 10log OL e dBm 2 x (re - 1) where IOL(mAP-P) is the DC overload for the MAX3910.
P0
TIME
Figure 4. Optical Power Relations
8
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10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust
Pad Coordinates
PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 NAME VEE1 MONIN N.C. N.C. IN FILT N.C. VEE1 VEE1 VEE1 VEE1 VEE1 VEE1 VEE1 VEE1 VEE1 VEE1 VCC VCC OUTVCC OUT+ VCC VCC CHF VCC MONMON+ OSADJ VCC VEE1 VEE1 VEE1 COORDINATES (m) X Y 38 1259 43 1034 43 908 43 782 43 656 43 530 50 282 47 47 173 47 299 47 425 47 551 47 677 47 803 47 929 47 1055 47 1181 47 1255 267 1255 393 1255 519 1255 645 1255 771 1255 897 1255 1055 1172 1259 1046 1259 920 1259 794 1259 668 1259 542 1259 416 1259 290 1259 164 1259
Chip Information
TRANSISTOR COUNT: 1291 PROCESS: BiPOLAR SiGe, SOI Die Size: 1.6mm 1.6mm
MAX3910
VCC (30) OSADJ (29)
MON+ (28)
VEE1 (33)
VEE1 (32) VEE1 (31)
MON- (27)
VEE1 (1) MONIN (2) N.C. (3) N.C. (4) IN (5) FILT (6) N.C. (7) VCC (24) VCC (23) OUT+ (22) VCC (21) OUT- (20) VCC (19) VCC (18) 63 mils (1.6mm)
VEE1 (10)
VEE1 (12) VEE1 (13)
VEE1 (14)
VEE1 (15)
VEE1 (16)
63 mils (1.6mm)
Coordinates are in m from the lower left corner of the circuit die to the center of the pad. For more information, refer to HFAN-08.0.1: Understanding Bonding Coordinates and Physical Die Size.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
VEE2 (17)
VEE1(11)
VEE1 (8)
VEE1 (9)
CENTER OF PAD (47m, 47m)
CHF (25)
VCC (26)

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