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Parts Not Suitable for New Designs For Additional Information End-Of-Life Product Change Notice
MC68341
Integrated Processor User's Manual
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
(c) MOTOROLA, 1993
PREFACE
The complete documentation package for the MC68341 consists of the MC68341UM/AD, MC68341 Integrated Processor User's Manual, M68000PM/AD, MC68000 Family Programmer's Reference Manual, and the MC68341P/D, MC68341 Integrated Processor Product Brief. The MC68341 Integrated Processor User's Manual describes the programming, capabilities, registers, and operation of the MC68341; the MC68000 Family Programmer's Reference Manual provides instruction details for the MC68341; and the MC68341 Integrated Processor Product Brief provides a brief description of the MC68341 capabilities. This user's manual is organized as follows: Section 1 Section 2 Section 3 Section 4 Section 5 Section 6 Section 7 Section 8 Device Overview Signal Descriptions Bus Operation System Integration Module CPU32 DMA Controller Module Serial Module Timer Modules Section 9 Section 10 Section 11 Section 12 Section 13 Queued Serial Peripheral Module IEEE 1149.1 Test Access Port Applications Electrical Characteristics Ordering Information and Mechanical Data
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Applications and Technical Information
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TABLE OF CONTENTS
Paragraph Number Title Section 1 Device Overview 1.1 Features .............................................................................................. 1-2 Section 2 Signal Descriptions 2.1 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.3 2.3.1 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.5 2.5.1 2.5.2 2.5.3 2.6 2.6.1 2.6.2
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Signal Index ........................................................................................ 2-3 Bus Signals ......................................................................................... 2-5 Address Bus .................................................................................... 2-6 Address Bus (A23-A0) ................................................................ 2-6 Address Bus (A31-A24) .............................................................. 2-6 Address Strobe (AS)........................................................................ 2-6 M68000 Address Strobe (68KAS) .................................................... 2-6 Data Bus (D15-D0) ......................................................................... 2-6 Data Strobe (DS) ............................................................................. 2-7 Upper And Lower Data Strobes (UDS , LDS) ................................... 2-7 Byte Write Enable (UWE , LWE) ....................................................... 2-7 Read/Write (R/W) ............................................................................ 2-7 Transfer Size (SIZ1, SIZ0)............................................................... 2-8 Function Codes (FC3-FC0)............................................................. 2-8 Chip Selects (CS7 -CS1 , CS0 /AVEC).............................................. 2-8 Interrupt Request Level (IRQ7 - IRQ1) ........................................... 2-9 Bus Control Signals............................................................................. 2-9 Data and Size Acknowledge (DSACK1 , DSACK0) .......................... 2-9 Bus Arbitration Signals ........................................................................ 2-9 Bus Request (BR) ............................................................................ 2-9 Bus Grant (BG ) ................................................................................ 2-10 Bus Grant Acknowledge (BGACK) .................................................. 2-10 Read-Modify-Write Cycle (RMC/RTCOUT) ..................................... 2-10 Exception Control Signals ................................................................... 2-10 Reset (RESET) ................................................................................ 2-10 Halt (HALT) ...................................................................................... 2-10 Bus Error (BERR ) ............................................................................ 2-10 Clock Signals ...................................................................................... 2-11 System Clock (CLKOUT)................................................................. 2-11 Crystal Oscillator (EXTAL, XTAL) .................................................... 2-11
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Paragraph Number 2.6.3 2.6.4 2.6.5 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.9 2.9.1 2.9.2 2.9.3 2.9.4 2.9.5 2.9.6 2.9.7 2.9.8 2.10 2.10.1 2.10.2 2.10.3 2.10.4 2.11 2.11.1 2.11.2 2.11.3 2.12 2.12.1 2.12.2 2.12.3 2.12.4 2.13 2.13.1 2.13.2 2.13.3 2.14 Title Page Number
External Clock (EXTCLK) ................................................................ 2-11 External Filter Capacitor (XFC) ....................................................... 2-11 Clock Mode Select (MODCK, Port B0) ............................................ 2-11 Instrumentation and Emulation Signals............................................... 2-11 Instruction Fetch (IFETCH ).............................................................. 2-11 Instruction Pipe (IPIPE) ................................................................... 2-12 Breakpoint (BKPT ) .......................................................................... 2-12 Freeze (FREEZE) ............................................................................ 2-12 DMA Module Signals .......................................................................... 2-12 DMA Request (DREQ2 , DREQ1 ) .................................................... 2-12 DMA Acknowledge (DACK2, DACK1/DDACK2 , DDACK1 ) ............. 2-13 DMA Done (DONE2 , DONE1 ) ......................................................... 2-13 Data Transfer Complete (DTC ) ....................................................... 2-13 DMA Ready (RDY2, RDY1) ............................................................ 2-13 Serial Module Signals ......................................................................... 2-13 Serial Crystal Oscillator (X2, X1) ..................................................... 2-13 Serial External Clock Input (SCLK) ................................................. 2-13 Receive Data (RxDA, RxDB) ........................................................... 2-14 Transmit Data (TxDA, TxDB)........................................................... 2-14 Clear to Send (CTSA, CTSB) .......................................................... 2-14 Request to Send (RTSA, RTSB) ..................................................... 2-14 Transmitter Ready (TRDYA ).......................................................... 2-14 Receiver Ready (RRDYA) ............................................................. 2-14 Queued Serial Module Signals ........................................................... 2-15 Master In Slave Out (MISO) ............................................................ 2-15 Master Out Slave In (MOSI) ............................................................ 2-15 QSPI Serial Clock (QSCLK) ............................................................ 2-15 QSPI Peripheral Chip Select (PCS1, PCS0) ................................... 2-15 Timer Signals ...................................................................................... 2-15 Timer Gate (TGATE2 ) ..................................................................... 2-15 Timer Input (TIN) ............................................................................. 2-16 Timer Output (TOUT) ...................................................................... 2-16 Test Signals ........................................................................................ 2-16 Test Clock (TCK) ............................................................................. 2-16 Test Mode Select (TMS) ................................................................. 2-16 Test Data In (TDI) ............................................................................ 2-16 Test Data Out (TDO) ....................................................................... 2-16 Real Time Clock Mode Signals ........................................................... 2-16 Battery Switch (BSW ) ...................................................................... 2-16 Battery Voltage (VBATT ) ................................................................. 2-16 Real Time Clock Output (RMC/RTCOUT) ....................................... 2-17 System Power and Ground (VCC AND GND) .................................... 2-17
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Paragraph Number Title Section 3 Bus Operation 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.2.11.1 3.1.11.2 3.2.11.3 3.3 3.3.1 3.3.2 3.3.3 3.3.3.1 3.3.3.2 3.3.3.3 3.3.3.4 3.3.3.5 3.3.3.6 3.3.3.7 3.3.4 3.3.5 3.3.6 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 3.5.1
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68000 Bus Mode ..................................................................................... 3-1 Bus Transfer Signals ............................................................................... 3-2 Bus Control Signals ............................................................................. 3-3 Function Code Signals ............................................................................ 3-4 Address Bus (A31-A0)............................................................................ 3-5 Address Strobe (AS) ............................................................................... 3-5 68000 Address Strobe (AS68K) .............................................................. 3-5 Data Bus (D15-D0) ................................................................................. 3-5 Data Strobe (DS )..................................................................................... 3-5 Upper and Lower Data Strobes (UDS and LDS ) ..................................... 3-6 Upper and Lower Write Enables (UWE and LWE) .................................. 3-6 Data Transfer Complete (DTC ) ............................................................... 3-6 Bus Cycle Termination Signals ............................................................... 3-6 Data Transfer and Size Acknowledge Signals (DSACK1 and DSACK0). ................................................................. 3-6 Bus Error (BERR) ............................................................................. 3-7 Autovector (AVEC)........................................................................... 3-7 Data Transfer Mechanism ....................................................................... 3-7 Dynamic Bus Sizing ................................................................................ 3-7 Misaligned Operands .............................................................................. 3-9 Operand Transfer Cases......................................................................... 3-10 Byte Operand to 8-Bit Port, Odd or Even (A0 = X) .......................... 3-10 Byte Operand to 16-Bit Port, Even (A0 = 0) ................................ ..... 3-10 Byte Operand to 16-Bit Port, Odd (A0 = 1) ...................................... 3-11 Word Operand to 8-Bit Port, Aligned ............................................... 3-11 Word Operand to 16-Bit Port, Aligned ............................................. 3-12 Long-word Operand to 8-Bit Port, Aligned. ...................................... 3-12 Long-Word Operand to 16-Bit Port, Aligned .................................... 3-14 Bus Operation ...................................................................................... 3-16 Synchronous Operation with DSACK ................................................ 3-16 Fast Termination Cycles ...................................................................... 3-17 Data Transfer Cycles ........................................................................... 3-18 M68300 Read Cycle ................................................................................ 3-18 68000 Read Cycle ................................................................................... 3-21 M68300 Write Cycle ................................................................................ 3-23 68000 Write Cycle ................................................................................... 3-26 Read-Modify-Write Cycle ........................................................................ 3-29 CPU Space Cycles.................................................................................. 3-31 Breakpoint Acknowledge Cycle............................................................... 3-31
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Paragraph Number 3.5.2 3.5.3 3.5.4 3.5.4.1 3.5.4.2 3.5.4.3 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.7 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 3.8 Title Page Number
LPSTOP Broadcast Cycle....................................................................... 3-32 Module Base Address Register Access .................................................. 3-36 Interrupt Acknowledge Bus Cycles ......................................................... 3-36 Interrupt Acknowledge Cycle--Terminated Normally.......................... 3-36 Autovector Interrupt Acknowledge Cycle............................................. 3-38 Spurious Interrupt Cycle ...................................................................... 3-39 Bus Exception Control Cycles................................................................. 3-41 Bus Errors ............................................................................................... 3-43 Retry Operation ....................................................................................... 3-45 Halt Operation ......................................................................................... 3-47 Double Bus Fault .................................................................................... 3-48 Bus Arbitration ........................................................................................ 3-49 Bus Request ........................................................................................... 3-52 Bus Grant ................................................................................................ 3-52 Bus Grant Acknowledge ......................................................................... 3-52 Bus Arbitration Control ............................................................................ 3-53 Show Cycles ........................................................................................... 3-53 Reset Operation ...................................................................................... 3-55 Section 4 System Integration Module
4.1 4.2 4.2.1 4.2.2 4.2.2.1 4.2.2.2 4.2.2.3 4.2.2.4 4.2.2.5 4.2.2.6 4.2.2.6.1 4.2.2.6.2 4.2.2.7 4.2.3 4.2.3.1 4.2.3.2 4.2.3.3 4.2.4 4.2.4.1 4.2.4.2
Module Overview .................................................................................... 4-1 Module Operation.................................................................................... 4-2 Module Base Address Register Operation .......................................... 4-2 System Configuration and Protection Operation ................................. 4-3 System Configuration ...................................................................... 4-5 Internal Bus Monitor......................................................................... 4-6 Double Bus Fault Monitor ................................................................ 4-6 Spurious Interrupt Monitor ............................................................... 4-6 Software Watchdog ......................................................................... 4-6 Periodic Interrupt Timer ................................................................... 4-7 Periodic Timer Period Calculation ................................................ 4-8 Using the Periodic Timer as a Real-Time Clock........................... 4-9 Simultaneous Interrupts by Sources in the SIM41 ........................... 4-9 Clock Synthesizer Operation ............................................................... 4-9 Phase Comparator and Filter........................................................... 4-12 Frequency Divider. ........................................................................... 4-12 Clock Control ................................................................................... 4-15 Chip Select Operation ......................................................................... 4-15 Programmable Features .................................................................. 4-15 Global Chip Select Operation .......................................................... 4-16
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Paragraph Number 4.2.5 4.2.5.1 4.2.5.2 4.2.6 4.2.7 4.3 4.3.1 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.2.4 4.3.2.5 4.3.2.6 4.3.2.7 4.3.2.8 4.3.3 4.3.4 4.3.4.1 4.3.4.2 4.3.4.3 4.3.4.4 4.3.4.5 4.3.5 4.3.5.1 4.3.5.2 4.3.5.3 4.3.5.4 4.3.5.5 4.3.5.6 4.3.5.7 4.3.5.8 4.4 4.4.1 4.4.2 4.4.3 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 Title Page Number
External Bus Interface Operation ........................................................ 4-17 Port A. .............................................................................................. 4-17 Port B ............................................................................................... 4-17 Low-Power Stop .................................................................................. 4-18 Freeze.................................................................................................. 4-19 Programming Model ................................................................................ 4-19 Module Base Address Register (MBAR) ............................................. 4-22 System Configuration and Protection Registers .................................. 4-23 Module Configuration Register (MCR) ............................................. 4-23 Autovector Register (AVR)............................................................... 4-25 Reset Status Register (RSR) ........................................................... 4-25 Software Interrupt Vector Register (SWIV) ...................................... 4-26 System Protection Control Register (SYPCR) ................................. 4-26 Periodic Interrupt Control Register (PICR)....................................... 4-28 Periodic Interrupt Timer Register (PITR) ......................................... 4-28 Software Service Register (SWSR) ................................................. 4-29 Clock Synthesizer Control Register (SYNCR) ..................................... 4-29 Chip Select Registers .......................................................................... 4-31 Base Select Registers ......................................................................... 4-31 Address Mask Registers .................................................................. 4-33 Bus Select Register.......................................................................... 4-35 Map Select Register......................................................................... 4-35 Chip Select Registers Programming Example ................................. 4-35 External Bus Interface Control............................................................. 4-36 Port A Pin Assignment Register 1 (PPARA1) .................................. 4-36 Port A Pin Assignment Register 2 (PPARA2) .................................. 4-36 Port A Data Direction Register (DDRA). .......................................... 4-37 Port A Data Register (PORTA) ........................................................ 4-37 Port B Pin Assignment Register (PPARB) ....................................... 4-37 Port B Data Direction Register (DDRB) ........................................... 4-38 Port B Data Register (PORTB, PORTB1) ........................................ 4-38 Port C Pin Assignment Register (PPARC)....................................... 4-38 Real Time Clock ...................................................................................... 4-39 Reset ................................................................................................... 4-39 RTC Interrupt Control Register (RICR)................................................ 4-39 RTC Control/Status Register (RCR) .................................................... 4-40 RTC Calibration Control Register (RCCR) .......................................... 4-41 RTC Time of Day Registers ................................................................. 4-43 RTC Alarm Registers........................................................................... 4-45 RTC Power Up Operation .................................................................... 4-46 RTC Power Down Operation ............................................................... 4-46
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Paragraph Number 4.5 4.5.1 4.5.2 4.5.3 Title Page Number
MC68340 Initialization Sequence............................................................ 4-46 Startup ................................................................................................. 4-47 SIM41 Module Configuration ............................................................... 4-47 SIM41 Example Configuration Code ................................................... 4-48 SECTION 5 CPU32
5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.1.1 5.3.1.1.1 5.3.1.1.2 5.3.1.2 5.3.2 5.3.3 5.3.3.1 5.3.3.2 5.3.3.3 5.3.3.4 5.3.3.5 5.3.3.6 5.3.3.7 5.3.3.8 5.3.3.9 5.3.3.10 5.3.4 5.3.4.1 5.3.4.2 5.3.4.3 5.3.4.4 5.3.4.5 5.3.5
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Overview ............................................................................................. 5-1 Features .......................................................................................... 5-2 Virtual Memory ................................................................................ 5-2 Loop Mode Instruction Execution .................................................... 5-3 Vector Base Register....................................................................... 5-4 Exception Handling.......................................................................... 5-4 Addressing Modes........................................................................... 5-5 Architecture Summary ........................................................................ 5-5 Programming Model ........................................................................ 5-6 Registers ......................................................................................... 5-7 Instruction Set ..................................................................................... 5-8 M68000 Family Compatibility .......................................................... 5-10 New Instructions .......................................................................... 5-10 Low-Power Stop (LPSTOP) ..................................................... 5-10 Table Lookup and Interpolate (TBL)......................................... 5-10 Unimplemented Instructions ........................................................ 5-10 Instruction Format and Notation ...................................................... 5-10 Instruction Summary ....................................................................... 5-13 Condition Code Register .............................................................. 5-18 Data Movement Instructions ........................................................ 5-19 Integer Arithmetic Operations ...................................................... 5-20 Logic Instructions ......................................................................... 5-22 Shift and Rotate Instructions ........................................................ 5-22 Bit Manipulation Instructions ........................................................ 5-23 Binary-Coded Decimal (BCD) Instructions................................... 5-24 Program Control Instructions ....................................................... 5-24 System Control Instructions ......................................................... 5-25 Condition Tests ............................................................................ 5-27 Using the TBL Instructions .............................................................. 5-27 Table Example 1 Standard Usage ........................................... 5-28 Table Example 2 Compressed Table ....................................... 5-29 Table Example 3 8-Bit Independent Variable........................... 5-30 Table Example 4 Maintaining Precision ................................... 5-32 Table Example 5 Surface Interpolations .................................. 5-34 Nested Subroutine Calls.................................................................. 5-34
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Paragraph Number 5.3.6 5.4 5.4.1 5.4.2 5.4.2.1 5.4.2.2 5.4.2.3 5.5 5.5.1 5.5.1.1 5.5.1.2 5.5.1.3 5.5.1.4 5.5.2 5.5.2.1 5.5.2.2 5.5.2.3 5.5.2.4 5.5.2.5 5.5.2.6 5.5.2.7 5.5.2.8 5.5.2.9 5.5.2.10 5.5.2.11 5.5.2.12 5.5.3 5.5.3.1 5.5.3.1.1 5.5.3.1.2 5.5.3.1.3 5.5.3.1.4 5.5.3.2 5.5.3.2.1 5.5.3.2.2 5.5.3.2.3 5.5.3.2.4 5.5.3.2.5 5.5.3.2.6 5.5.3.2.7 5.5.4 5.5.4.1 Title Page Number
Pipeline Synchronization with the NOP Instruction ......................... 5-34 Processing States ............................................................................... 5-34 State Transitions.............................................................................. 5-35 Privilege Levels ............................................................................... 5-35 Supervisor Privilege Level ........................................................... 5-35 User Privilege Level ..................................................................... 5-36 Changing Privilege Level ............................................................. 5-36 Exception Processing.......................................................................... 5-36 Exception Vectors ............................................................................ 5-37 Types of Exceptions..................................................................... 5-38 Exception Processing Sequence ................................................. 5-38 Exception Stack Frame. ............................................................... 5-39 Multiple Exceptions ...................................................................... 5-39 Processing of Specific Exceptions................................................... 5-41 Reset............................................................................................ 5-41 Bus Error ...................................................................................... 5-43 Address Error ............................................................................... 5-43 Instruction Traps .......................................................................... 5-44 Software Breakpoints ................................................................... 5-44 Hardware Breakpoints ................................................................. 5-45 Format Error ................................................................................. 5-45 Illegal or Unimplemented Instructions .......................................... 5-45 Privilege Violations....................................................................... 5-46 Tracing ......................................................................................... 5-47 Interrupts ...................................................................................... 5-48 Return from Exception ................................................................. 5-49 Fault Recovery ................................................................................ 5-50 Types of Faults ............................................................................ 5-52 Type I--Released Write Faults................................................. 5-52 Type II--Prefetch, Operand, RMW, and MOVEP Faults .......... 5-53 Type III--Faults During MOVEM Operand Transfer ................ 5-54 Type IV--Faults During Exception Processing......................... 5-54 Correcting a Fault......................................................................... 5-55 Type I--Completing Released Writes via Software ................. 5-55 Type I--Completing Released Writes via RTE......................... 5-55 Type II--Correcting Faults via RTE.......................................... 5-56 Type III--Correcting Faults via Software .................................. 5-56 Type III--Correcting Faults by Conversion and Restart ........... 5-56 Type III--Correcting Faults via RTE......................................... 5-57 Type IV--Correcting Faults via Software ................................. 5-57 CPU32 Stack Frames ...................................................................... 5-58 Four-Word Stack Frame .............................................................. 5-58
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Paragraph Number 5.5.4.2 5.5.4.3 5.6 5.6.1 5.6.1.1 5.6.1.2 5.6.1.3 5.6.2 5.6.2.1 5.6.2.2 5.6.2.2.1 5.6.2.2.2 5.6.2.2.3 5.6.2.3 5.6.2.4 5.6.2.5 5.6.2.5.1 5.6.2.5.2 5.6.2.5.3 5.6.2.6 5.6.2.7 5.6.2.7.1 5.6.2.7.2 5.6.2.8 5.6.2.8.1 5.6.2.8.2 5.6.2.8.3 5.6.2.8.4 5.6.2.8.5 5.6.2.8.6 5.6.2.8.7 5.6.2.8.8 5.6.2.8.9 5.6.2.8.10 5.6.2.8.11 5.6.2.8.12 5.6.2.8.13 5.6.2.8.14 5.6.2.8.15 5.6.2.8.16 5.6.3 5.6.3.1 Title Page Number
Six-Word Stack Frame ................................................................. 5-58 Bus Error Stack Frame ................................................................ 5-58 Development Support ......................................................................... 5-61 CPU32 Integrated Development Support ........................................ 5-61 Background Debug Mode (BDM) Overview................................. 5-62 Deterministic Opcode Tracking Overview.................................... 5-62 On-Chip Hardware Breakpoint Overview..................................... 5-63 Background Debug Mode................................................................ 5-63 Enabling BDM .............................................................................. 5-63 BDM Sources............................................................................... 5-64 External BKPT Signal............................................................... 5-64 BGND Instruction ..................................................................... 5-64 Double Bus Fault...................................................................... 5-64 Entering BDM .............................................................................. 5-64 Command Execution.................................................................... 5-65 BDM Registers ............................................................................. 5-65 Fault Address Register (FAR) .................................................. 5-65 Return Program Counter (RPC) ............................................... 5-65 Current Instruction Program Counter (PCC). ........................... 5-65 Returning from BDM .................................................................... 5-66 Serial Interface ............................................................................. 5-66 CPU Serial Logic ...................................................................... 5-67 Development System Serial Logic ........................................... 5-69 Command Set .............................................................................. 5-71 Command Format .................................................................... 5-71 Command Sequence Diagram ................................................. 5-72 Command Set Summary .......................................................... 5-73 Read A/D Register (RAREG/RDREG) ................................ ..... 5-74 Write A/D Register (WAREG/WDREG).................................... 5-75 Read System Register (RSREG) ............................................. 5-75 Write System Register (WSREG) ............................................ 5-76 Read Memory Location (READ) ............................................... 5-77 Write Memory Location (WRITE) ............................................. 5-78 Dump Memory Block (DUMP). ................................................. 5-79 Fill Memory Block (FILL) .......................................................... 5-80 Resume Execution (GO) .......................................................... 5-81 Call User Code (CALL) ............................................................ 5-82 Reset Peripherals (RST) .......................................................... 5-84 No Operation (NOP) ................................................................. 5-84 Future Commands.................................................................... 5-85 Deterministic Opcode Tracking ....................................................... 5-85 Instruction Fetch (IFETCH) .......................................................... 5-85
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Paragraph Number 5.6.3.2 5.6.3.3 5.7 5.7.1 5.7.1.1 5.7.1.2 5.7.1.3 5.7.1.3.1 5.7.1.3.2 5.7.1.3.3 5.7.1.4 5.7.1.5 5.7.1.6 5.7.1.7 5.7.2 5.7.2.1 5.7.2.2 5.7.2.3 5.7.3 5.7.3.1 5.7.3.2 5.7.3.3 5.7.3.5 5.7.3.6 5.7.3.7 5.7.3.8 5.7.3.9 5.7.3.10 5.7.3.11 5.7.3.12 5.7.3.13 5.7.3.14 Title Page Number
Instruction Pipe (IPIPE) ................................................................ 5-85 Opcode Tracking During Loop Mode ........................................... 5-87 Instruction Execution Timing ............................................................... 5-87 Resource Scheduling ...................................................................... 5-87 Microsequencer............................................................................ 5-87 Instruction Pipeline....................................................................... 5-87 Bus Controller Resources ............................................................ 5-88 Prefetch Controller ................................................................... 5-89 Write-Pending Buffer. ............................................................... 5-89 Microbus Controller .................................................................. 5-89 Instruction Execution Overlap ...................................................... 5-89 Effects of Wait States ................................................................... 5-90 Instruction Execution Time Calculation ........................................ 5-91 Effects of Negative Tails .............................................................. 5-92 Instruction Stream Timing Examples ............................................... 5-92 Timing Example 1--Execution Overlap ....................................... 5-93 Timing Example 2--Branch Instructions ...................................... 5-93 Timing Example 3--Negative Tails .............................................. 5-94 Instruction Timing Tables ................................................................ 5-95 Fetch Effective Address ............................................................... 5-97 Calculate Effective Address ......................................................... 5-98 MOVE Instruction ......................................................................... 5-99 Arithmetic/Logic Instructions ........................................................ 5-101 Immediate Arithmetic/Logic Instructions ...................................... 5-102 Binary-Coded Decimal and Extended Instructions ...................... 5-103 Single Operand Instructions......................................................... 5-103 Shift/Rotate Instructions ............................................................... 5-104 Bit Manipulation Instructions ........................................................ 5-105 Conditional Branch Instructions ................................................... 5-105 Control Instructions ...................................................................... 5-106 Exception-Related Instructions and Operations........................... 5-107 Save and Restore Operations...................................................... 5-108
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Paragraph Number Title Section 6 DMA Controller Module 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.3.1 6.3.1.1 6.3.1.2 6.3.2 6.3.2.1 6.3.2.2 6.3.2.3 6.4 6.4.1 6.4.1.1 6.4.1.2 6.4.2 6.4.2.1 6.4.2.2 6.5 6.6 6.6.1 6.6.2 6.6.2.1 6.6.2.2 6.6.3 6.6.3.1 6.6.3.2 6.6.3.3 6.7 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6
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DMA Module Overview ........................................................................... 6-2 DMA Module Signal Definitions............................................................... 6-4 DMA Request (DREQ1, DREQ2) ........................................................ 6-4 DMA Acknowledge (DACK1,DACK2).................................................. 6-4 Ready (RDY1, RDY2) ......................................................................... 6-4 DMA Done (DONE1, DONE2)............................................................. 6-4 Data Transfer Complete (DTC ) ........................................................... 6-4 Transfer Request Generation.................................................................. 6-4 Internal Request Generation ............................................................... 6-5 Internal Request, Maximum Rate .................................................... 6-6 Internal Request, Limited Rate ........................................................ 6-6 External Request Generation .............................................................. 6-6 External Burst Mode ........................................................................ 6-6 External Cycle Steal Mode............................................................... 6-6 External Request With Other Modules............................................. 6-7 Data Transfer modes .............................................................................. 6-8 Single-Address Mode .......................................................................... 6-8 Single-Address Read ....................................................................... 6-8 Single-Address Write ....................................................................... 6-11 Dual-Address Mode............................................................................. 6-13 Dual-Address Read ......................................................................... 6-13 Dual-Address Write .......................................................................... 6-16 Bus Arbitration ........................................................................................ 6-19 DMA Channel Operation ......................................................................... 6-19 Channel Initialization and Startup........................................................ 6-19 Data Transfers..................................................................................... 6-20 Internal Request Transfers .............................................................. 6-20 External Request Transfers ............................................................. 6-20 Channel Termination ........................................................................... 6-21 Channel Termination........................................................................ 6-21 Interrupt Operation ........................................................................... 6-21 Fast Termination Option .................................................................. 6-22 Register Description................................................................................ 6-23 Byte Transfer Counter Register (BTC) ................................................ 6-25 Channel Control Register (CCR) ......................................................... 6-25 Channel Status Register (CSR) .......................................................... 6-29 Destination Address Register (DAR) ................................................... 6-30 Function Code Register (FCR) ............................................................ 6-31 Interrupt Register (INTR) ..................................................................... 6-32
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Paragraph Number 6.7.7 6.7.8 6.8 6.9 6.9.1 6.9.1.1 6.9.1.2 6.9.2 6.10 6.10.1 6.10.2 6.10.3 6.10.4 Title Page Number
Module Configuration Register (MCR) ................................................ 6-33 Source Address Register (SAR) .......................................................... 6-35 Data Packing ........................................................................................... 6-36 DMA Channel Initialization Sequence ..................................................... 6-36 DMA Channel Configuration ................................................................ 6-37 DMA Channel Operation In Single-Address Mode .......................... 6-38 DMA Channel Operation In Dual-Address Mode ............................. 6-39 DMA Channel Example Configuration Code ....................................... 6-40 MC68341 DMA Enhancements............................................................... 6-47 RDY ................................................................................................... 6-47 Delayed DACK ................................................................................... 6-47 DTC ..................................................................................................... 6-47 Timing Examples ................................................................................. 6-48 Section 7 Serial Module
7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.3 7.3.1 7.3.2 7.3.2.1 7.3.2.2 7.3.2.3
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Module Overview ................................................................................ 7-2 Serial Communication Channels A and B........................................ 7-3 Baud Rate Generator Logic ............................................................. 7-3 Internal Channel Control Logic ........................................................ 7-3 Interrupt Control Logic ..................................................................... 7-3 Comparison of the Serial Module to the MC68681.......................... 7-4 Serial Module Signal Definitions.......................................................... 7-4 Crystal Input or External Clock (X1) ................................................ 7-5 Crystal Output (X2) .......................................................................... 7-5 External Input (SCLK) ..................................................................... 7-6 Channel A Transmitter Serial Data Output (TxDA) ......................... 7-6 Channel A Receiver Serial Data Input (RxDA) ............................... 7-6 Channel B Transmitter Serial Data Output (TxDB) ......................... 7-6 Channel B Receiver Serial Data Input (RxDB) ............................... 7-6 Channel A Request-To-Send (RTSA ).............................................. 7-6 Channel B Request-To-Send (RTSB ).............................................. 7-7 Channel A Clear-To-Send (CTSA ) ................................................. 7-7 Channel B Clear-To-Send (CTSB ) ................................................. 7-7 Channel A Transmitter Ready (TRDYA ) ........................................ 7-7 Channel A Receiver Ready (RRDYA) ............................................ 7-7 Operation ............................................................................................ 7-8 Baud Rate Generator ...................................................................... 7-8 Transmitter and Receiver Operating Modes.................................... 7-8 Transmitter ................................................................................... 7-10 Receiver ....................................................................................... 7-11 FIFO Stack ................................................................................... 7-13
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Paragraph Number 7.3.3 7.3.3.1 7.3.3.2 7.3.3.3 7.3.4 7.3.5 7.3.5.1 7.3.5.2 7.3.5.3 7.4 7.4.1 7.4.1.1 7.4.1.2 7.4.1.3 7.4.1.4 7.4.1.5 7.4.1.6 7.4.1.7 7.4.1.8 7.4.1.9 7.4.1.10 7.4.1.11 7.4.1.12 7.4.1.13 7.4.1.14 7.4.1.15 7.4.1.16 7.4.1.17 7.4.2 7.4.2.1 7.4.2.2 7.4.2.3 7.5 7.5.1 7.5.2 Title Page Number
Looping Modes ................................................................................ 7-14 Automatic Echo Mode.................................................................. 7-14 Local Loopback Mode.................................................................. 7-14 Remote Loopback Mode .............................................................. 7-14 Multidrop Mode ................................................................................ 7-15 Bus Operation ................................................................................. 7-17 Read Cycles ................................................................................ 7-17 Write Cycles................................................................................. 7-17 Interrupt Acknowledge Cycles ..................................................... 7-17 Register Description and Programming .............................................. 7-18 Register Description ........................................................................ 7-18 Auxiliary Control Register (ACR) ................................................. 7-20 Clock-Select Register (CSR) ....................................................... 7-20 Command Register (CR) ............................................................. 7-22 Input Port Change Register (IPCR) ............................................. 7-25 Input Port Register (IP) ................................................................ 7-26 Interrupt Enable Register (IER) ................................................... 7-27 Interrupt Level Register (ILR) ...................................................... 7-28 Interrupt Status Register (ISR)..................................................... 7-28 Interrupt Vector Register (IVR) .................................................... 7-30 Module Configuration Register (MCR) ......................................... 7-31 Mode Register 1 (MR1) ............................................................... 7-33 Mode Register 2 (MR2) ............................................................... 7-35 Output Port Data Register (OP) ................................................... 7-37 Outport Port Control Register (OPCR)......................................... 7-38 Receiver Buffer (RB) .................................................................... 7-39 Status Register (SR) .................................................................... 7-39 Transmitter Buffer (TB) ................................................................ 7-41 Programming ................................................................................... 7-42 Serial Module Initialization. .......................................................... 7-42 I/O Driver Example....................................................................... 7-42 Interrupt Handling ........................................................................ 7-42 Serial Module Initialization Sequence ................................................ 7-48 Serial Module Configuration ............................................................ 7-48 Serial Module Example Configuration Code ................................... 7-50
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Paragraph Number Title Section 8 Timer Module 8.1 8.1.1 8.1.1.1 8.1.1.2 8.1.1.3 8.1.1.4 8.1.2 8.1.3 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.9.1 8.3.9.2 8.3.9.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.5 8.5.1 8.5.2 Module Overview ................................................................................. 8-1 Timer and Counter Functions ...........................................................8-2 Prescaler and Counter .................................................................. 8-2 Time-Out Detection ....................................................................... 8-2 Comparator ................................................................................... 8-2 Clock Selection Logic .................................................................... 8-3 Internal Control Logic ....................................................................... 8-3 Interrupt Control Logic ...................................................................... 8-4 Timer Modules Signal Definitions......................................................... 8-4 Timer Input (TIN) .............................................................................. 8-5 Timer Gate (TGATE) ........................................................................ 8-5 Timer Output (TOUT) ....................................................................... 8-5 Operating Modes.................................................................................. 8-5 Input Capture/Output Compare ........................................................8-5 Square-Wave Generator .................................................................. 8-7 Variable Duty-Cycle Square-Wave Generator.................................. 8-8 Variable-Width Single-Shot Pulse Generator ...................................8-10 Pulse-Width Measurement ............................................................... 8-11 Period Measurement ........................................................................ 8-12 Event Count ...................................................................................... 8-13 Timer Bypass.................................................................................... 8-15 Bus Operation ................................................................................... 8-16 Read Cycles.................................................................................. 8-16 Write Cycles ..................................................................................8-16 Interrupt Acknowledge Cycles ...................................................... 8-16 Register Description ............................................................................. 8-16 Module Configuration Register (MCR) ............................................. 8-17 Interrupt Register (IR) ....................................................................... 8-18 Control Register (CR) ....................................................................... 8-19 Status Register (SR)......................................................................... 8-22 Counter Register (CNTR) ................................................................. 8-24 Preload 1 Register (PREL1) ............................................................. 8-24 Preload 2 Register (PREL2) ............................................................. 8-25 Compare Register (COM) ................................................................. 8-25 Timer Module Initialization Sequence .................................................. 8-26 Timer Module Configuration ............................................................. 8-26 Timer Module Example Configuration Code..................................... 8-27 Page Number
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Paragraph Number Title Section 9 Queued Serial Peripheral Module 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.2.1 9.4.2.2 9.4.2.3 9.4.2.4 9.4.3 9.4.3.1 9.4.3.2 9.4.3.3 9.5 9.5.1 9.5.1.1 9.5.1.2 9.5.1.3 9.5.1.4 9.5.1.5 9.5.1.6 9.5.1.7 9.5.2 9.5.3 9.5.4 9.5.4.1 9.5.4.2 9.5.4.3 9.5.4.4 9.5.4.5 9.5.4.6 9.5.4.6.1 9.5.4.6.2 9.5.4.6.3 9.5.5 9.5.5.1 9.5.5.1.1 9.5.5.1.2
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Block Diagram ..................................................................................... 9-1 Memory Map ....................................................................................... 9-2 QSPM Pins ......................................................................................... 9-3 Registers ............................................................................................. 9-4 Overall QSPM Configuration Summary........................................... 9-7 QSPM Global Registers .................................................................. 9-8 QSPM Configuration Register (QMCR) ....................................... 9-8 QSPM Test Register (QTEST)..................................................... 9-10 QSPM Interrupt Level Register (QILR) ........................................ 9-10 QSPM Interrupt Vector Register (QIVR) ...................................... 9-11 QSPM Pin Control Registers ........................................................... 9-11 QSPM Port Data Register (QPDR) .............................................. 9-12 QSPM Pin Assignment Register (QPAR) .................................... 9-12 QSPM Data Direction Register (QDDR) ...................................... 9-13 QSPI Submodule ................................................................................ 9-13 Features .......................................................................................... 9-14 Programmable Queue ................................................................. 9-14 Programmable Peripheral Chip Selects....................................... 9-14 Wraparound Transfer Mode......................................................... 9-14 Programmable Transfer Length ................................................... 9-15 Programmable Transfer Delay ..................................................... 9-15 Programmable Queue Pointer ..................................................... 9-15 Continuous Transfer Mode .......................................................... 9-15 Block Diagram ................................................................................. 9-16 QSPI Pins ........................................................................................ 9-16 Programmer's Model and Registers ................................................ 9-17 QSPI Control Register 0 (SPCR0) ............................................... 9-18 QSPI Control Register 1 (SPCR1) ............................................... 9-20 QSPI Control Register 2 (SPCR2) ............................................... 9-22 QSPI Control Register 3 (SPCR3) ............................................... 9-24 QSPI Status Register (SPSR) ..................................................... 9-25 QSPI RAM ................................................................................... 9-26 Receive Data RAM (REC.RAM) ............................................... 9-27 Transmit Data RAM (TRAN.RAM)............................................ 9-27 Command RAM (COMD.RAM) ................................................ 9-27 Operating Modes and Flowcharts ................................................... 9-30 Master Mode ................................................................................ 9-37 Master Mode Operation ........................................................... 9-37 Master Wraparound Mode........................................................ 9-38
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Paragraph Number 9.5.5.2 9.5.5.2.1 9.5.5.2.2 Title Page Number
Slave Mode .................................................................................. 9-39 Description of Slave Operation ................................................. 9-39 Slave Wraparound Mode .......................................................... 9-41 Section 10 IEEE 1149.1 Test Access Port
10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.6
Overview ............................................................................................. 10-1 Tap Controller ..................................................................................... 10-2 Boundary Scan Register ..................................................................... 10-3 Instruction Register ............................................................................. 10-10 EXTEST (000) ................................................................................. 10-11 Sample/Preload (001) ...................................................................... 10-11 BYPASS (X1X, 101) ........................................................................ 10-11 HI-Z (100) ........................................................................................ 10-12 MC68341 Restrictions ......................................................................... 10-12 Non-IEEE 1149.1 Operation................................................................ 10-13 Section 11 Applications
11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.3 11.4
Minimum System Configuration .......................................................... 11-1 Processor Clock Circuitry ................................................................ 11-1 Reset Circuitry ................................................................................. 11-3 SRAM Interface ............................................................................... 11-3 ROM Interface ................................................................................. 11-4 Serial Interface ................................................................................ 11-4 Memory Interface Information ............................................................. 11-5 Using an 8-Bit Boot ROM ................................................................ 11-5 Access Time Calculations................................................................ 11-6 Calculating Frequency-Adjusted Output .......................................... 11-7 Interfacing an 8-Bit Device to 16-Bit Memory Using Single-Address DMA Mode .......................................................... 11-10 Power Consumption Considerations ................................................... 11-10 MC68341V (3.3 V)............................................................................... 11-11
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Paragraph Number Title Section 12 Electrical Characteristics 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 Maximum Ratings ............................................................................... 12-1 Thermal Characteristics ...................................................................... 12-1 Power Considerations ......................................................................... 12-2 AC Electrical Specification Definitions ................................................ 12-2 DC Electrical Specifications ................................................................ 12-5 AC Electrical Specifications Control Timing ........................................ 12-6 AC Timing Specifications .................................................................... 12-7 DMA Module AC Electrical Specifications .......................................... 12-22 Timer Module Electrical Specifications ............................................... 12-24 Serial Module Electrical Specifications ............................................... 12-26 QSPM Electrical Specifications ........................................................... 12-29 IEEE 1149.1 Electrical Specifications ................................................. 12-32 Page Number
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Figure Number 1-1 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 Title Page Number
MC68341 Simplified Block Diagram ............................................................. 1-1 Functional Signal Groups ............................................................................. 2-2 Input Sample Window .................................................................................. 3-3 MC68341 Interface to Various Port Sizes .................................................... 3-9 Long-Word Operand Read Timing from 8-Bit Port ....................................... 3-13 Long-Word Operand Write Timing to 8-Bit Port ........................................... 3-14 Long-Word and Word Read and Write Timing--16-Bit Port......................... 3-15 Fast Termination Timing............................................................................... 3-17 Word Read Cycle Flowchart......................................................................... 3-19 Read Cycle Timing ....................................................................................... 3-20 68000 Word Read Cycle Flowchart ............................................................. 3-21 68000 Read Cycle Timing ............................................................................ 3-23 Word Write Cycle Flowchart ......................................................................... 3-24 M68300 Write Cycle Timing ......................................................................... 3-25 68000 Word Write Cycle Flowchart.............................................................. 3-26 68000 Write Cycle Timing ............................................................................ 3-28 Read-Modify-Write Cycle Timing ................................................................. 3-29 CPU Space Address Encoding .................................................................... 3-31 Breakpoint Operation Flowchart ................................................................... 3-33 Breakpoint Acknowledge Cycle Timing (Opcode Returned) ........................ 3-34 Breakpoint Acknowledge Cycle Timing (Exception Signaled) ...................... 3-35 Interrupt Acknowledge Cycle Flowchart ....................................................... 3-37 Interrupt Acknowledge Cycle Timing............................................................ 3-38 Autovector Operation Timing ....................................................................... 3-40 Bus Error without DSACK ........................................................................... 3-44 Late Bus Error with DSACK ........................................................................ 3-45 Retry Sequence ........................................................................................... 3-46 Late Retry Sequence ................................................................................... 3-47 HALT Timing ................................................................................................. 3-48 Bus Arbitration Flowchart for Single Request .............................................. 3-50 Bus Arbitration Timing Diagram--Idle Bus Case ......................................... 3-51 Bus Arbitration Timing Diagram--Active Bus Case ..................................... 3-51 Bus Arbitration State Diagram ...................................................................... 3-54 Show Cycle Timing Diagram ........................................................................ 3-55
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Figure Number 3-33 3-34 4-1 4-2 4-3 4-4 4-5 4-6 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 Title Page Number
Timing for External Devices Driving Reset .................................................. 3-56 Power-Up Reset Timing Diagram ............................................................... 3-57 SIM41 Module Register Block...................................................................... 4-3 System Configuration and Protection Function ............................................ 4-5 Software Watchdog Block Diagram ............................................................. 4-7 Clock Block Diagram for Crystal and EXTCLK Operation ........................... 4-10 MC68341 Crystal Oscillator ......................................................................... 4-10 Block Diagram for External Clock Operation ............................................... 4-11 CPU32 Block Diagram ................................................................................. 5-3 Loop Mode Instruction Sequence ................................................................ 5-3 User Programming Model ............................................................................ 5-6 Supervisor Programming Model Supplement .............................................. 5-7 Status Register ............................................................................................ 5-8 Instruction Word General Format ................................................................. 5-11 Table Example 1 .......................................................................................... 5-28 Table Example 2 .......................................................................................... 5-29 Table Example 3 .......................................................................................... 5-31 Exception Stack Frame ................................................................................ 5-39 Reset Operation Flowchart .......................................................................... 5-42 Format $0--Four-Word Stack Frame........................................................... 5-58 Format $2--Six-Word Stack Frame ............................................................. 5-58 Internal Transfer Count Register.................................................................. 5-59 Format $C--BERR Stack for Prefetches and Operands ............................. 5-60 Format $C--BERR Stack on MOVEM Operand .......................................... 5-60 Format $C--Four- and Six-Word BERR Stack ............................................ 5-61 In-Circuit Emulator Configuration ................................................................. 5-62 Bus State Analyzer Configuration ................................................................ 5-62 BDM Block Diagram ..................................................................................... 5-63 BDM Command Execution Flowchart .......................................................... 5-66 Debug Serial I/O Block Diagram .................................................................. 5-68 Serial Interface Timing Diagram .................................................................. 5-69 BKPT Timing for Single Bus Cycle .............................................................. 5-70 BKPT Timing for Forcing BDM..................................................................... 5-70 BKPT/DSCLK Logic Diagram....................................................................... 5-70 Command Sequence Diagram..................................................................... 5-73 Functional Model of Instruction Pipeline ...................................................... 5-86 Instruction Pipeline Timing Diagram ............................................................ 5-86 Block Diagram of Independent Resources .................................................. 5-88 Simultaneous Instruction Execution ............................................................. 5-90 Attributed Instruction Times ......................................................................... 5-90
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Figure Number 5-33 5-34 5-35 5-36 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 Title Page Number
Example 1--Instruction Stream ................................................................... 5-93 Example 2--Branch Taken .......................................................................... 5-93 Example 2--Branch Not Taken.................................................................... 5-94 Example 3--Branch Negative Tail ............................................................... 5-94 DMA Block Diagram ..................................................................................... 6-1 Single-Address Transfers............................................................................. 6-3 Dual-Address Transfer ................................................................................. 6-3 DMA External Connections to Serial Module ............................................... 6-7 Single-Address Read Timing (External Burst).............................................. 6-9 Single-Address Read Timing (Cycle Steal) .................................................. 6-10 Single-Address Write Timing (External Burst) .............................................. 6-11 Single-Address Write Timing (Cycle Steal) .................................................. 6-12 Dual-Address Read Timing (External Burst-Source Requesting) ................ 6-14 Dual-Address Read Timing (Cycle Steal-Source Requesting)..................... 6-15 Dual-Address Write Timing (External Burst-Destination Requesting) .......... 6-17 Dual-Address Write Timing (Cycle Steal-Destination Requesting) .............. 6-18 Fast Termination Option Timing (Cycle Steal) ............................................. 6-22 Fast Termination Option Timing (External Burst-Source Requesting) ........ 6-23 DMA Module Programming Model ............................................................... 6-24 Packing and Unpacking of Operands........................................................... 6-36 M68300 Single Address Read with RDY .................................................... 6-49 M68300 Single Address Write with RDY .................................................... 6-50 M68300 Single Address Read with Delayed DACK and RDY .................. 6-51 M68300 Single Address Write with Delayed DACK and RDY .................. 6-52 68000 Single Address Read with RDY ....................................................... 6-53 68000 Single Address Write with RDY ....................................................... 6-54 68000 Single Address Read with Delayed DACK and RDY ..................... 6-55 68000 Single Address Write with Delayed DACK and RDY ..................... 6-56 68000 Single Address Read with Delayed DACK ...................................... 6-57 Simplified Block Diagram ............................................................................. 7-1 External and Internal Interface Signals ........................................................ 7-5 Baud Rate Generator Block Diagram........................................................... 7-8 Transmitter and Receiver Functional Diagram............................................. 7-9 Transmitter Timing Diagram ......................................................................... 7-10 Receiver Timing Diagram............................................................................. 7-12 Looping Modes Functional Diagram............................................................. 7-15 Multidrop Mode Timing Diagram .................................................................. 7-16 Serial Module Programming Model Programming Model ............................ 7-19 Serial Module Programming Flowchart ....................................................... 7-43
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Figure Number 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 Title Page Number
Simplified Block Diagram ............................................................................. 8-1 Timer Functional Diagram ............................................................................ 8-3 External and Internal Interface Signals ........................................................ 8-4 Input Capture/Output Compare Mode.......................................................... 8-6 Square-Wave Generator Mode .................................................................... 8-8 Variable Duty-Cycle Square-Wave Generator Mode ................................... 8-9 Variable-Width Single-Shot Pulse Generator Mode..................................... 8-11 Pulse-Width Measurement Mode ................................................................. 8-12 Period Measurement Mode .......................................................................... 8-13 Event Count Mode ....................................................................................... 8-14 Timer Module Programming Model .............................................................. 8-17 QSPM Block Diagram .................................................................................. 9-1 QSPM Memory Map .................................................................................... 9-2 QSPI Submodule Diagram........................................................................... 9-16 Organization of the QSPI RAM .................................................................... 9-27 Command RAM............................................................................................ 9-28 Flowchart of QSPI Initialization Operation ................................................... 9-31 Flowchart of QSPI Master Operation ........................................................... 9-32 Flowchart of QSPI Slave Operation ............................................................. 9-35 Test Access Port Block Diagram ................................................................. 10-2 TAP Controller State Machine ..................................................................... 10-3 Output Latch Cell (O.Latch) ......................................................................... 10-7 Input Pin Cell (I.Pin) ..................................................................................... 10-8 Active-High Output Control Cell (IO.Ctl1)..................................................... 10-8 Active-Low Output Control Cell (IO.Ctl0) ..................................................... 10-9 Bidirectional Data Cell (IO.Cell) ................................................................... 10-9 General Arrangement for Bidirectional Pins................................................. 10-10 Bypass Register ........................................................................................... 10-12 Minimum System Configuration Block Diagram ........................................... 11-1 Sample Crystal Circuit ................................................................................. 11-2 Statek Corporation Crystal Circuit ................................................................ 11-2 XFC and VCCSYN Capacitor Connections.................................................. 11-3 SRAM Interface ............................................................................................ 11-4 ROM Interface.............................................................................................. 11-4 Serial Interface ............................................................................................. 11-5 External Circuitry for 8-Bit Boot ROM .......................................................... 11-5 8-bit Boot ROM Timing ................................................................................ 11-6 Access Time Computation Diagram ............................................................ 11-6 Signal Relationships to CLKOUT ................................................................. 11-7
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Figure Number Title Page Number
11-12 Signal Width Specifications .......................................................................... 11-8 11-13 Skew between Two Outputs......................................................................... 11-9 11-14 Circuitry for Interfacing 8-Bit Device to 16-Bit Memory in Single-Address DMA Mode................................................................... 11-10 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 12-24 12-25 12-26 12-27 12-28 12-29 12-30 Drive Levels and Test Points for AC Specifications ..................................... 12-4 M68300 Read Cycle Timing Diagram .......................................................... 12-10 M68300 Write Cycle Timing Diagram .......................................................... 12-11 68000 Three-Clock Read Cycle Timing Diagram Using Internal DSACK1 .. 12-12 68000 Three-Clock Write Cycle Timing Diagram Using Internal DSACK1 .. 12-13 68000 Four-Clock Read Cycle Timing Diagram ........................................... 12-14 68000 Four-Clock 16-Bit Write Timing Diagram........................................... 12-15 M68300 Fast Termination Read Cycle Timing Diagram .............................. 12-16 M68300 Fast Termination Write Cycle Timing Diagram............................... 12-17 Bus Arbitation Timing--Active Bus Case ..................................................... 12-18 Bus Arbitration Timing--Idle Bus Case ........................................................ 12-19 Show Cycle Timing Diagram ........................................................................ 12-19 IACK Cycle Timing Diagram......................................................................... 12-20 Background Debug Mode Serial Port Timing ............................................... 12-21 Background Debug Mode FREEZE Timing ................................................. 12-21 DMA Signal Timing Diagram ........................................................................ 12-22 DMA Enhancements Timing Diagram .......................................................... 12-23 Timer Module Clock Signal Timing Diagram ................................................ 12-24 Timer Module Signal Timing Diagram .......................................................... 12-25 Serial Module General Timing Diagram ....................................................... 12-27 Serial Module Asynchronous Mode Timing (X1) .......................................... 12-27 Serial Module Asynchronous Mode Timing (SCLK-16X) ............................ 12-28 Serial Module Synchronous Mode Timing Diagram ..................................... 12-28 QSPI Timing Master, CPHA 0 ...................................................................... 12-30 QSPI Timing Master, CPHA 1 ...................................................................... 12-30 QSPI Timing Slave, CPHA 0 ........................................................................ 12-31 QSPI Timing Slave, CPHA 1 ........................................................................ 12-31 Test Clock Input Timing Diagram ................................................................. 12-32 Boundary Scan Timing Diagram .................................................................. 12-33 Test Access Port Timing Diagram ................................................................ 12-33
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LIST OF TABLES
Table Number 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 3-1 3-2 3-3 3-4 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 Title Page Number
Bus Signal Summary ................................................................................... 2-3 CPU32 Serial Port........................................................................................ 2-4 Serial Module ............................................................................................... 2-4 Queued Serial Module ................................................................................. 2-4 DMA Module ................................................................................................ 2-4 Timer Module ............................................................................................... 2-5 IEEE 1149.1 ................................................................................................. 2-5 Power, Clock, and Control ........................................................................... 2-5 Data Strobe Control of Data Bus ................................................................. 2-7 SIZx Signal Encoding ................................................................................... 2-8 Address Space Encoding ............................................................................. 2-8 DSACK Encoding ....................................................................................... 2-9 SIZx Signal Encoding ................................................................................... 3-4 Address Space Encoding ............................................................................. 3-5 DSACK Encoding ....................................................................................... 3-8 DSACK , BERR , and HALT Assertion Results ............................................ 3-42 Clock Operating Modes................................................................................ 4-9 System Frequencies from 32.768-kHz Reference ....................................... 4-13 Clock Control Signals ................................................................................... 4-15 Port B Pin Assignment Register................................................................... 4-17 Port A Pin Assignment Register................................................................... 4-17 Port B Pin Assignment Register................................................................... 4-18 SHENx Control Bits ...................................................................................... 4-24 Deriving Software Watchdog Timeout ......................................................... 4-27 BMTx Encoding ............................................................................................ 4-27 PIRQL Encoding .......................................................................................... 4-28 DDx Encoding .............................................................................................. 4-34 PSx Encoding............................................................................................... 4-34 RIRQL Encoding .......................................................................................... 4-40
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Table Number 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 Title Page Number
Instruction Set .............................................................................................. 5-9 Instruction Set Summary .............................................................................. 5-14 Condition Code Computations ..................................................................... 5-18 Data Movement Operations ......................................................................... 5-19 Integer Arithmetic Operations ...................................................................... 5-21 Logic Operations .......................................................................................... 5-22 Shift and Rotate Operations ......................................................................... 5-23 Bit Manipulation Operations ......................................................................... 5-23 Binary-Coded Decimal Operations............................................................... 5-24 Program Control Operations ........................................................................ 5-24 System Control Operations .......................................................................... 5-26 Condition Tests ............................................................................................ 5-27 Standard Usage Entries ............................................................................... 5-28 Compressed Table Entries........................................................................... 5-30 8-Bit Independent ......................................................................................... 5-31 Exception Vector Assignments .................................................................... 5-37 Exception Priority Groups ............................................................................ 5-40 Tracing Control ............................................................................................. 5-47 BDM Source Summary ................................................................................ 5-64 Polling the BDM Entry Source ...................................................................... 5-65 CPU Generated Message Encoding ............................................................ 5-67 Size Field Encoding ..................................................................................... 5-71 BDM Command Summary ........................................................................... 5-74 Register Field for RSREG and WSREG....................................................... 5-76 SSIZEx Encoding ......................................................................................... 6-27 DSIZEx Encoding ......................................................................................... 6-27 REQx Encoding............................................................................................ 6-28 BBx Encoding and Bus Bandwidth............................................................... 6-28 Address Space Encoding ............................................................................. 6-31 FRZx Control Bits ......................................................................................... 6-33 RCSx Control Bits ........................................................................................ 7-21 TCSx Control Bits......................................................................................... 7-22 MISCx Control Bits ....................................................................................... 7-23 TCx Control Bits ........................................................................................... 7-24 RCx Control Bits ........................................................................................... 7-25 FRZx Control Bits ......................................................................................... 7-31 PMx and PT Control Bits .............................................................................. 7-34 B/Cx Control Bits .......................................................................................... 7-34 CMx Control Bits .......................................................................................... 7-35 SBx Control Bits ........................................................................................... 7-36
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Table Number 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9.8 9-9 10-1 10-2 10-3 11-1 11-2 Title Page Number 8-16 8-18 8-20 8-21 8-21 8-21
OCx Encoding .............................................................................................. FRZx Control Bits ......................................................................................... IEx Encoding ................................................................................................ POT Encoding.............................................................................................. MODEx Encoding......................................................................................... OCx Encoding ..............................................................................................
QSPM Pin Summary .................................................................................... 9-4 QSPM Register Summary ............................................................................ 9-5 Bit/Field Quick Reference Guide.................................................................. 9-6 QSPM Global Registers ............................................................................... 9-8 QSPM Pin Control Registers ....................................................................... 9-11 External Pin Inputs/Outputs to the QSPI...................................................... 9-17 QSPI Registers ............................................................................................ 9-17 Bits per Transfer if Command Control Bit BITSE = 1 ................................... 9-19 Examples of SCK Frequencies .................................................................... 9-20 Boundary Scan Control Bits ......................................................................... 10-4 Boundary Scan Bit Definitions ..................................................................... 10-5 Instructions................................................................................................... 10-10 Memory Access Times at 16.78 MHz .......................................................... 11-7 Typical Electrical Characteristics ................................................................. 11-11
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SECTION 1 DEVICE OVERVIEW
The MC68341 is a member of the M68300 family of integrated processors designed specifically for the compact disc-interactive (CD-I) market. It improves on the feature set of the MC68340 for a more complete and cost effective integrated system solution to CD-I's specific needs. The MC68341 contains a 68020-based CPU32, a two channel DMA controller, two serial channels, a timer, and a queued serial peripheral interface. The 68341's system integration module (SIM41) contains clock circuitry, system protection, external bus interface, timers, and additional chip selects. New to the SIM is the real time clock and an MC68000 bus interface. The MC68000 bus interface is dynamically selectable to give a glueless interface to peripherals and memory designed for the MC68000 while allowing higher performance transfers using the standard 68300 bus interface. Complete code compatibility with the MC68000 affords the designer access to a broad base of established real-time kernels, operating systems, languages, applications, and development tools--many oriented towards embedded control. As a low voltage part, the MC68341V can operate with a 3.3-V power supply and is particularly useful for battery applications. MC68341 is used throughout this document to refer to both the low voltage and standard 5-V parts since both are functionally equivalent. Figure 1-1 illustrates a block diagram of the MC68341.
SYSTEM INTEGRATION MODULE (SIM41) TIMER TWO-CHANNEL DMA CONTROLLER SYSTEM PROTECTION CLOCK SYNTHESIZER CPU32 (68000-BASED PROCESSOR) INTERMODULE BUS EXTERNAL BUS INTERFACE BUS ARBITRATION QUEUED SERIAL PERIPHERAL INTERFACE TWO-CHANNEL SERIAL I/O 16-BIT DATA BUS REAL TIME CLOCK 32-BIT ADDRESS BUS
IEEE 1149.1 TEST
Figure 1-1. MC68341 Simplified Block Diagram
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MC68341 FEATURES
The primary features of the MC68341 are as follows: * High Performance CPU32 Core Processor -- Upward Object-Code Compatible with MC68000 and MC68010 -- Additional 32-Bit MC68020 Instructions and Addressing Modes -- Fast Two-Clock Register Instructions * High-Speed Dual DMA Controllers for Low-Latency Transfers -- 50-Mbyte/Sec Sustained Transfer Rate -- Dual or Single Address Transfers -- 8-, 16-, or 32-Bit Transfers * Counter/Timer -- 16-Bit Timer with 8-Bit Prescaler -- Multi-mode Operation -- 80 nS Resolution * Dual Serial Communication Ports -- Synchronous or Asynchronous Operation -- 3-Mbit/Sec Sustained Transfer Rate -- Modem Control -- Baud Rate Generation -- 68681/261 Compatible * Queued Serial Peripheral Interface (QSPI) -- Communications with Slow Peripherals without Tying Up the CPU -- Queued Transmit and Receive Buffers -- Programmable for Master or Slave SPI Operation * System Integration Module for Flexible and Cost-Effective System Interface -- 32-Bit Address Bus; 16-Bit Data Bus with Dynamic Bus Sizing -- System Protection, Reset, and Configuration Control -- Periodic Interrupt/System Timer -- Chip-Select, Wait State Generation, Bus Watchdog -- Interrupt Controller -- IEEE 1149.1 Boundary Scan (JTAG) -- Dual 8-Bit Parallel Ports -- Real Time Clock -- Time and Date with Leap Year Correction -- Programmable Alarm for Interrupt or External Output -- Calibration Register Eliminates Need for Trim Capacitor -- Battery Backup Capability * Power Management -- 5 V or 3.3 V Operation -- Fully Static HCMOS Technology -- Programmable Clock Synthesizer for Full Frequency Control -- Power-Down/Low Power Stop Capabilities -- Idle Modules Can Be Individually Powered Down * 0-16 or 25 MHz Operation * 160-Pin Plastic Quad Flat Pack (QFP)
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CENTRAL PROCESSING UNIT
The CPU32 is a powerful central processor that supervises system function, makes decisions, manipulates data, and directs I/O. A special debugging mode simplifies processor emulation during system debug.
CPU32
The CPU32 is a 68000-based microprocessor that can execute most 32-bit operations in two clock periods. Additional instructions enhance lookup table interpolation and power consumption control. In addition to performing basic instruction execution, the CPU32 provides a sophisticated background debug port for non-invasive instrumentation in the software development and debug environments.
On-Chip Peripherals
To improve total system throughput and reduce part count, board size, and cost of system implementation, the M68300 family integrates on-chip, intelligent peripheral modules, and typical glue logic. These functions on the MC68341 include the SIM41, a DMA controller, a serial module, a queued serial peripheral interface, and a timer. The IMB is the backbone of the MC68341, and is similar to traditional external buses with address, data, clock, interrupt, arbitration, and handshake signals. Because bus masters (like the CPU32 and DMA), peripherals, and the SIM41 are on the same processor, the IMB ensures that communication between these modules is fully synchronized and that arbitration and interrupts can be handled in parallel with data transfers, greatly improving system performance. Internal accesses across the IMB can be monitored from outside of the processor.
System Integration Module
The MC68341 system integration module (SIM41) handles a wide array of functions, eliminating the need for much of the glue logic which typically supports the microprocessor and its interface with peripherals and external memory. The SIM41 includes: * External Bus Interface--Transfers information between the CPU32 or DMA controller and external memory or peripherals by providing up to 32 address lines and 16 data lines. Both the 68300 bus interface and the original MC68000 bus interface are provided. * System Configuration and Protection--Achieves maximum system protection by providing various monitors and timers to prevent system lockup, recover from catastrophic failure, exit infinite loops, provide refresh, etc. * Clock Synthesizer--Generates the clock signals used by all internal operations as well as a clock output used by external devices. * Chip Select and Wait State Generation--Offers eight programmable chip selects which provide signals to enable external memory and peripheral circuits and create all external handshaking and timing signals. Up to six wait states can be automatically inserted.
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* Interrupt Control--Provides up to seven discrete interrupt inputs for external devices. * IEEE 1149.1 Test Access Port (JTAG)--Aids in system diagnostics by providing dedicated, user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability. * Real Time Clock--The real time clock can be sustained on a separate power supply for battery backup. This simple counter is driven by 32.768 KHz clock for low power consumption. The real time clock counts seconds, minutes, hours, days, day of the week, date of the month, and year with leap year compensation. The real time clock has internal interrupt generation capability and includes a programmable output pin, which can provide an interrupt or other output signal based upon an alarm or time matching function. Software calibration eliminates the need for an external trim capacitor.
Queued Serial Peripheral Interface (QSPI) Module
The QSPI eases peripheral expansion or interprocessor communications. This function allows interface to and control of other integrated controllers (such as, MC6805 or MC68HC11 family devices) and peripherals (such as, LCD drivers, A/D-D/A converters, digital signal processors, EEPROM). The QSPI can handle up to 16 serial transfers of 8 to 16 bits each or transmit a stream of data up to 256 bits long without CPU intervention, because of a small RAM in the QSPI. A special wrap-around mode allows the QSPI to continuously sample a serial peripheral, automatically updating the QSPI RAM for efficient interfacing to serial analog-to-digital converters.
Timer Module
The timer consists of a 16-bit countdown counter with an 8-bit countdown prescaler for a composite 24-bit resolution. The finest resolution of the timer is 80 ns with a 25-MHz system clock (125 ns @ 16.78 MHz). The programmable timer operating modes are input capture, output compare, square-wave generation, variable duty-cycle square-wave generation, variable-width single-shot pulse generation, event counting, period measurement, and pulse-width measurement.
POWER CONSUMPTION MANAGEMENT
The MC68341 is very power efficient due to its advanced 0.8- HCMOS process technology and its static logic design. The resulting power consumption is typically 500 mW in full operation--far less than the comparable discrete component implementation the MC68341 can replace. For applications employing reduced voltage operation, selection of the MC68341V, which requires only a 3.3-V power supply, reduces current consumption by 40-60% in all modes of operation (as well as reducing noise emissions).
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COMPACT DISC-INTERACTIVE
The MC68341 was designed to meet the needs of many markets, including compact discinteractive (CD-I). CD-I is an standard for a publishing medium that will bring multimedia to a broad general audience--the consumer. CD-I players combine television and stereo systems as output devices, with interactive control using a TV remote-control-like device to provide a multimedia experience selected from software titles contained in compressed form on standard compact discs. The on-chip real-time clock eliminates the need for a separate chip to keep time-of-day. The 68000 bus interface simplifies the use of existing CD-DA and CD-I peripherals and ASICs that were designed for use with the 68000. The highly integrated MC68341 is ideal as the central processor for CD-I players. It provides the M68000 microprocessor code compatibility and DMA functions required by the CD-I Green Book specification as well as many other useful on-chip functions for a very cost-effective solution. The extra demands of full-motion video CD-I systems make the best use of the MC68341 high performance. The MC68341 is CD-I compliant and has been CD-I qualified. With its low voltage operation, the MC68341V is the only practical choice for portable CD-I.
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SECTION 2 SIGNAL DESCRIPTIONS
This section contains brief descriptions of the MC68341 input and output signals in their functional groups as shown in Figure 2-1.
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A31/PORT A7/IACK7 A30/PORT A6/IACK6 A29/PORT A5/IACK5 A28/PORT A4/IACK4 A27/PORT A3/IACK3 A26/PORT A2/IACK2 A25/PORT A1/IACK1 A24/PORT A0
BKPT/DSCLK FREEZE IPIPE/DSO IFETCH/DSI
TCK TMS TDI TDO
PORT A
SCLK X2 X1
TEST A23-A0 D15-D0 FC2-FC0 FC3/DTC RESET BERR HALT AS DS R/W SIZ1 SIZ0 DSACK1 DSACK0 68KAS UDS LDS UWE LWE RMC/RTCOUT BR BG BGACK BSW CPU32 CORE TWO-CHANNEL SERIAL I/O
RxDA TxDA CTSA RxDB TxDB CTSB
EXTERNAL BUS INTERFACE
OUTPUT PORT SYSTEM INTEGRATION MODULE
TxRDYA/OP6 RxRDYA/FFULLA/OP4 RTSB/OP1 RTSA/OP0
IMB
BUS ARBITRATION CLOCK
TWO-CHANNEL DMA CONTROLLER
TIMER MODULE
QUEUED SERIAL MODULE
MISO MOSI PCS1 PCS0 QSCLK
EXTCLK EXTAL
XTAL
CS7 CS6 CS5 CS4 CS3 CS2 CS1
CLKOUT XFC DREQ1 DACK1 DONE1 DREQ2 DACK2 DONE2
IRQ7/PORT B7 IRQ6/PORT B6 IRQ5/PORT B5 IRQ4/PORT B4 IRQ3/PORT B3 IRQ2/PORT B2 IRQ1/PORT B1 CS0/AVEC MODCK/PORT B0
PORT B
Figure 2-1. Functional Signal Groups
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TGATE/RDY1 TIN/RDY2 TOUT
CHIP SELECTS
2.1 SIGNAL INDEX
The input and output signals for the MC68341 are listed in Table 2-1 through 2-8. The name, mnemonic, and brief functional description are presented. For more detail on each signal, refer to the signal paragraph. Guaranteed timing specifications for the signals listed in the following tables can be found in Section 12 Electrical Characteristics. Table 2-1. Bus Signal Summary
Signal Name Address Bus Address Bus/Port A7-A0/ Interrupt Acknowledge7-1 Data Bus Function Code 3/ DTC, Function Code 2-0 Chip Select 7-1 Interrupt Request Level/ Port B7-B1 Chip Select 0/Autovector Bus Request Bus Grant Bus Grant Acknowledge Data and Size Acknowledge Read-Modify-Write Cycle/ Real-Time Clock Out Address Strobe Data Strobe M68000 Address Strobe Upper Data Strobe Lower Data Strobe Upper Write Enable Lower Write Enable Size Read/Write Reset Halt Bus Error Mnemonic A23-A0 A31-A24/ IACK7-1 D15-D0 FC3/DTC FC2-FC0 CS7-CS1 IRQ7-1/ B7-B1 CS0/AVEC BR BG BGACK DSACK1, DSACK0 RMC/RTCOUT AS DS 68KAS UDS LDS UWE LWE SIZ1, SIZ0 R/ W RESET HALT BERR Input/ Output Out Out/I/O/ Out I/O Out Out Out In, I/O Out/In In Out In In Out Out Out Out Out Out Out Out Out Out I/O I/O In Three-State During Bus Arbitration Yes Yes Yes Yes Yes Yes - - - No - - Yes/No Yes Yes Yes Yes Yes Yes Yes Yes Yes No No -
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Table 2-2. CPU32 Serial Port
Signal Name Instruction Fetch/ Development Serial In Instruction Pipe/ Development Serial Out Breakpoint/Development Serial Clock Freeze Mnemonic IFETCH /DSI IPIPE/DSO BKPT/DSCLK FREEZE Input/ Output Out/In Out/Out In/-- Out
Table 2-3. Serial Module
Signal Name Receive Data Transmit Data Clear-to-Send Request-to-Send/OP1, OP0 Serial Crystal Oscillator Serial Clock Transmitter Ready/OP6 Receiver Ready/FIFO Full/OP4 Mnemonic RxDB, RxDA TxDB, TxDA CTSB, CTSA RTSB, RTSA X1, X2 SCLK TRDYA RRDYA Input/ Output In Out In Out/Out In In Out/Out Out/Out/ Out
Table 2-4. Queued Serial Module
Signal Name QSPI Peripheral Chip Slect QSPI Serial Clock Master-In Slave-Out Master-Out Slave-In Mnemonic PCS1, PCS0 QSCLK MISO MOSI Input/ Output I/O In I/O I/O
Table 2-5. DMA Module
Signal Name DMA Request DMA Acknowledge DMA Done DMA RDY1/Timer Gate DMA RDY2/Timer Input DTC/FC3 Mnemonic DREQ2, DREQ1 DACK2 DACK1 DONE2, DONE1 TGATE, RDY1 TIN, RDY2 TIN, RDY2 Input/ Output In Out I/O In In In
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Table 2-6. Timer Module
Signal Name Timer Gate/DMA RDY1 Timer Input/DMA RDY2 Timer Output Mnemonic TGATE, RDY1 TIN, RDY2 TOUT Input/ Output In In Out
Table 2-7. IEEE 1149.1
Signal Name Test Clock Test Mode Select Test Data In Test Data Out Mnemonic TCK TMS TDI TDO Input/ Output In In In Out
Table 2-8. Power, Clock, and Control
Signal Name Clock Mode Select/ Port B0 Battery Switch Battery Power In System Power Supply and Ground System Clock Crystal Oscillator External Clock External Filter Capacitor Mnemonic MODCK/Port B0 BSW VBATT VCC , GND CLKOUT EXTAL, XTAL EXTCLK XFC In -- Out In, Out In In Input/ Output In/I/O
NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false.
2.2 BUS SIGNALS
The MC68341 can interface using either a 68000 family bus or an MC68341 Family bus. Many of the signals are common to both bus types. Refer to Section 3 Bus Operation for more information on the two types of buses.
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2.2.1 Address Bus
The address bus signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MC68341 places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. The address bus consists of the following two groups. Refer to Section 3 Bus Operation for information on the address bus and its relationship to bus operation. 2.2.1.1 Address Bus (A23-A0). These three-state outputs (along with A31-A24) provide the address for the current bus cycle, except in the CPU address space. 2.2.1.2 Address Bus (A31-A24). These pins can be programmed as the most significant eight address bits, port A parallel I/O, or interrupt acknowledge signals. These pins can be used for more than one of their multiplexed functions as long as the external demultiplexing circuit properly resolves interaction between the different functions. A31-A24 These pins can function as the most significant eight address bits. Port A7-A0 These eight pins can serve as a dedicated parallel I/O port. See Section 4 System Integration Module for more information on programming these pins.
IACK7-IACK1
The MC68341 asserts one of these pins to indicate the level of an external interrupt during an interrupt acknowledge cycle. Peripherals can use the IACK signals instead of monitoring the address bus and function codes to determine that an interrupt acknowledge cycle is in progress and to obtain the current interrupt level.
2.2.2 Address Strobe (AS)
AS is an output timing signal for MC68300 cycles that indicates the validity of both an address on the address bus and many control signals. AS is asserted approximately onehalf clock cycle after the beginning of a bus cycle.
2.2.3 M68000 Address Strobe (AS68K )
AS68K is an output timing signal for MC68000 cycles that indicates that the information on the address bus is a valid address.
2.2.4 Data Bus (D15-D0)
This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68341. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68341 on the last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68341 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle.
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2.2.5 Data Strobe (DS)
DS is an output timing signal for M68300 transfers that applies to the data bus. For a read cycle, the MC68341 asserts DS and AS simultaneously to signal the external device to place data on the bus. For a write cycle, DS signals to the external device that the data to be written is valid. The MC68341 asserts DS approximately one clock cycle after the assertion of AS during a write cycle.
2.2.6 Upper And Lower Data Strobes (UDS , LDS)
These three-state signals and R/W control the flow of data on the data bus for M68000 transfers. Table 2-9 lists the combinations of these signals and the corresponding data on the bus. UDS and LDS assert with AS68K for read cycles, and one clock after AS for write cycles. The equations of the data strobes are as follows: UDS = A0 LDS = A0 x SIZ1 x SIZ0 Table 2-9. Data Strobe Control of Data Bus
UDS
Low High Low Low
LDS
Low Low High Low
R/ W High High High Low
D15-D8 Valid Data Bits 15-8 No Valid Data Valid Data Bits 15-8 Valid Data Bits 15-8
D7-D0 Valid Data Bits 7-0 Valid Data Bits 7-0 No Valid Data Valid Data Bits 7-0
2.2.7 Byte Write Enable (UWE,
LWE)
On a write cycle to a 16-bit port, these active-low output signals indicate when the upper or lower eight bits of the data bus contain valid data. The upper write enable (UWE ) indicates that the upper eight bits of the data bus contain valid data during a write cycle. The lower write enable (LWE ) indicates that the lower eight bits of the data bus contain valid data during a write cycle. UWE and LWE assert with DS for an MC68300 write and with UDS/LDS for a 68000 write cycle. The equations of the byte write enables are as follows: UWE = R/W + AS + A0 LWE = R/W + AS + (A0 x SIZ0)
2.2.8 Read/Write (R/W)
This active-high output signal is driven by the bus master to indicate the direction of a data transfer on the bus. A logic one indicates a read from a slave device; a logic zero indicates a write to a slave device.
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2.2.9 Transfer Size (SIZ1, SIZ0)
These output signals are driven by the bus master to indicate the number of operand bytes remaining to be transferred in the current bus cycle as noted in Table 2-10. Table 2-10. SIZx Signal Encoding
SIZ1 0 1 1 0 SIZ0 1 0 1 0 Transfer Size Byte Word Three Byte Long Word
2.2.10 Function Codes (FC3-FC0)
These signals are outputs that indicate one of 16 address spaces to which the address applies. Fifteen of these spaces are designated as either user or supervisor, program or data, and normal or direct memory access (DMA) spaces. One other address space is designated as CPU space to allow the CPU32 to acquire specific control information not normally associated with read or write bus cycles. The function code signals are valid while AS is asserted. See Table 2-11 for more information. Table 2-11. Address Space Encoding
Function Code Bits 3 0 0 0 0 0 0 0 0 1 2 0 0 0 0 1 1 1 1 x 1 0 0 1 1 0 0 1 1 x 0 0 1 0 1 0 1 0 1 x Address Spaces Reserved (Motorola) User Data Space User Program Space Reserved (User ) Reserved (Motorola) Supervisor Data Space Supervisor Program Space CPU Space DMA Space
2.2.11 Chip Selects
(CS7--CS1, CS0/AVEC)
The chip select output signals (CS7-CS1) enable peripherals at programmed addresses. These signals are inactive high (not high impedance) after reset. CS0 is the chip select for a boot ROM containing the reset vector and initialization program. It functions as the boot chip select immediately after reset. AVEC requests an automatic vector during an interrupt acknowledge cycle.
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2.2.12 Interrupt Request Level (IRQ7 -- IRQ1)
These pins can be programmed to be either prioritized interrupt request lines or port B parallel I/O.
IRQ7 - IRQ1
IRQ7, the highest priority, is nonmaskable. IRQ6-IRQ1 are internally maskable interrupts. Refer to Section 5 CPU32 for more information on interrupt request lines. Port B7 - B1 These pins can be used as port B parallel I/O. Refer to Section 4 System Integration Module for more information on parallel I/O signals.
2.3 BUS CONTROL SIGNALS
These signals control the bus transfer operations of the MC68341. Refer to Section 3 Bus Operation for more information on these signals.
2.3.1 Data and Size Acknowledge (DSACK1, DSACK0)
These two active-low input signals allow asynchronous data transfers and dynamic data bus sizing between the MC68341 and external devices as listed in Table 2-12. During bus cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol. During a read cycle, this signals the MC68341 to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate. Table 2-12. DSACK Encoding
DSACK1
1 1 0 0
DSACK0
1 0 1 0
Result Insert Wait States in Current Bus Cycle Complete Cycle--Data Bus Port Size Is 8 Bits Complete Cycle--Data Bus Port Size Is 16 Bits Reserved--Defaults to 16-Bit Port Size. Can Be Used for 32-Bit DMA Cycles
2.4 BUS ARBITRATION SIGNALS
The following signals are the bus arbitration control signals used to determine the bus master. Refer to Section 3 Bus Operation for more information on these signals.
2.4.1 Bus Request (BR)
This active-low input signal indicates that an external device needs to become the bus master.
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2.4.2 Bus Grant (BG )
Assertion of this active-low output signal indicates that the MC68341 has relinquished the bus.
2.4.3 Bus Grant Acknowledge
(BGACK)
Assertion of this active-low input indicates that an external device has become the bus master.
2.4.4 Read-Modify-Write Cycle (RMC /RTCOUT)
RMC is an output signal that identifies the bus cycle as part of an indivisible read-modifywrite operation. It remains asserted during all bus cycles of the read-modify-write operation to indicate that bus ownership cannot be transferred. RTCOUT is an output signal from the real-time clock in the SIM41.
2.5 EXCEPTION CONTROL SIGNALS
These signals are used by the MC68341 to recover from an exception.
2.5.1 Reset (RESET)
This active-low, open-drain, bidirectional signal is used to initiate a system reset. An external reset signal (as well as a reset from the SIM41) resets the MC68341 and all external devices. A reset signal from the CPU32 (asserted as part of the RESET instruction) resets external devices; the internal state of the CPU32 is not affected. The on-chip modules are reset, except for the SIM41. However, the module configuration register for each on-chip module is not altered. When asserted by the MC68341, this signal is guaranteed to be asserted for a minimum of 512 clock cycles. Refer to Section 3 Bus Operation for a description of bus reset operation and Section 5 CPU32 for information about the reset exception.
2.5.2 Halt (HALT)
This active-low, open-drain, bidirectional signal is asserted to suspend external bus activity, to request a retry when used with BERR , or to perform a single-step operation. As an output, HALT indicates a double bus fault by the CPU32. Refer to Section 3 Bus Operation for a description of the effects of HALT on bus operation.
2.5.3 Bus Error (BERR)
This active-low input signal indicates that an invalid bus operation is being attempted or, when used with HALT, that the processor should retry the current cycle. Refer to Section 3 Bus Operation for a description of the effects of BERR on bus operation.
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2.6 CLOCK SIGNALS
These signals are used by the MC68341 for controlling or generating the system clocks. See Section 4 System Integration Module for more information on the various clocking methods and frequencies.
2.6.1 System Clock (CLKOUT)
This output signal is the system clock output and is used as the bus timing reference by external devices. CLKOUT can be varied in frequency or slowed in low power stop mode to conserve power.
2.6.2 Crystal Oscillator (EXTAL, XTAL)
These two pins are the connections for an external crystal to the internal oscillator circuit.
2.6.3 External Clock (EXTCLK)
This pin used to connect an external clcok source. This input is divided by two until the Vbit in the SYNCR is set.
2.6.4 External Filter Capacitor (XFC)
This pin is used to add an external capacitor to the filter circuit of the phase-locked loop. The capacitor should be connected between XFC and VCCSYN.
2.6.5 Clock Mode Select (MODCK, Port B0)
This pin selects the source of the internal system clock during reset. After reset, it can be programmed to be port B parallel I/O. MODCK The state of this active-high input signal during reset selects the source of the internal system clock. If MODCK is high during reset, the internal voltage-controlled oscillator (VCO) furnishes the system clock in crystal mode. If MODCK is low during reset, an external clock source at the EXTCLK pin furnishes the system clock output in external clock mode. Port B0 This pin can be used as a port B parallel I/O.
2.7 INSTRUMENTATION AND EMULATION SIGNALS
These signals are used for test or software debugging. See Section 5 CPU32 for more information on these signals and background debug mode.
2.7.1 Instruction Fetch (IFETCH / DSI)
This pin functions as IFETCH in normal operation and as DSI in background debug mode.
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IFETCH
This active-low output signal indicates when the CPU32 is performing an instruction word prefetch and when the instruction pipeline has been flushed. DSI This development serial input signal helps to provide serial communications for background debug mode.
2.7.2 Instruction Pipe
(IPIPE/DSO )
This pin functions as IPIPE in normal operation and as DSO in background debug mode.
IPIPE
This active-low output signal is used to track movement of words through the instruction pipeline. DSO This development serial output signal helps to provide serial communications for background debug mode.
2.7.3 Breakpoint (BKPT /DSCLK)
This pin functions as BKPT in normal operation and as DSCLK in background debug mode.
BKPT
This active-low input signal is used to signal a hardware breakpoint to the CPU32. DSCLK This development serial clock input helps to provide serial communications for background debug mode.
2.7.4 Freeze (FREEZE)
Assertion of this active-high output signal indicates that the CPU32 has acknowledged a breakpoint and has initiated background mode operation.
2.8 DMA MODULE SIGNALS
The following signals are used by the direct memory access (DMA) controller module to provide external handshake for either a source or destination. See Section 6 DMA Module for additional information on these signals.
2.8.1 DMA Request (DREQ2, DREQ1)
This active-low input is asserted by a peripheral device to request an operand transfer between that peripheral and memory. The assertion of DREQ starts the DMA process.
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The assertion level in external burst mode is level sensitive; in external cycle steal mode, it is falling-edge sensitive.
2.8.2 DMA Acknowledge
(DACK2, DACK1)
DACK is asserted by the DMA to signal to a peripheral that an operand is being transferred in response to a previous transfer request. A delayed version of DACK is provided to allow operation with differing speed memories. The delayed form of DACK2 and DACK1 can be selected by setting bits 4 and 5 in the PPARC (See Section 6 DMA Controller Module).
2.8.3 DMA Done (DONE2, DONE1 )
This active-low output signal is asserted by the DMA or a peripheral device during any DMA bus cycle to indicate that the last data transfer is being performed. DONE is an active input in any mode. As an output, it is only active in external request mode. An external pullup resistor is required even during operation in the internal request mode.
2.8.4 Data Transfer Complete (DTC )
This active-low bidirectional signal is asserted on all bus cycles (DMA and CPU initiated) as an extra signal in standard bus timing. DTC is multiplexed with FC3, and is selected by setting PPARC bit 3.
2.8.5 DMA Ready (RDY2 , RDY1)
These active-low bidirectional signal is only asserted on DMA single-address transfers to indicate that the device has supplied data or is ready to receive data from memory. RDY2 is multiplexed with TIN, and RDY1 is multiplexed with TGATE. RDY2 is selected by setting PPARC bit 0, and RDY1 is selected by setting PPARC bit 1.
2.9 SERIAL MODULE SIGNALS
The following signals are used by the serial module for data and clock signals. See Section 7 Serial Module for more information on these signals.
2.9.1 Serial Crystal Oscillator (X2, X1)
These pins furnish the connection to a crystal or external clock, which must be supplied when using the baud rate generator. An external clock can be connected to the X1 pin; X2 is left floating in this case.
2.9.2 Serial External Clock Input (SCLK)
This input can be used as the external clock input for channel A or channel B, bypassing the baud rate generator.
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2.9.3 Receive Data (RxDA, RxDB)
These signals are the receiver serial data input for each channel. Data received on this signal is sampled on the rising edge of the clock source, with the least significant bit received first.
2.9.4 Transmit Data (TxDA, TxDB)
These signals are the transmitter serial data output for each channel. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal at the falling edge of the clock source, with the least significant bit transmitted first.
2.9.5 Clear to Send (CTSA, CTSB)
These active-low signals can be programmed as the clear-to-send inputs for each channel.
2.9.6 Request to Send (RTSA/OP0, RTSB / OP1)
These active-low signals can be programmed as request-to-send outputs or used as discrete outputs.
RTSB, RTSA
When used for this function, these signals function as the request-to-send outputs. OP1, OP0 When used for this function, these outputs are controlled by the value of bit 1 and bit 0, respectively, in the output port data registers.
2.9.7 Transmitter Ready
(TRDYA / OP6)
This active-low output can be programmed as the channel A transmitter ready status indicator or used as a discrete output.
TRDYA
When used for this function, this signal reflects the complement of the status of bit 2 of the channel A status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character. OP6 When used for this function, this output is controlled by bit 6 in the output port data registers.
2.9.8 Receiver Ready (RRDYA / FFULLA/
OP4)
This active-low output signal can be programmed as the channel A receiver ready, channel A FIFO full indicator, or a dedicated parallel output.
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RRDYA
When used for this function, this signal reflects the complement of the status of bit 1 of the interrupt status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver contains a character.
FFULLA
When used for this function, this signal reflects the complement of the status of bit 1 of the interrupt status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver FIFO is full. OP4 When used for this function, this output is controlled by bit 4 in the output port data registers.
2.10 QUEUED SERIAL MODULE SIGNALS
The following external signals are used by the queued serial peripheral module. See Section 9 QSPM for additional information on these signals.
2.10.1 Master In Slave Out (MISO)
This bidirectional signal can be the serial data input to the QSPI when the QSPI is the master device, or the the serial data output when using an external master.
2.10.2 Master Out Slave In (MOSI)
This bidirectional signal can be the serial data input to the QSPI when using an external master, or the the serial data output when the QSPI is the master device.
2.10.3 QSPI Serial Clock (QSCLK)
This input is the external clock input for the QSPI.
2.10.4 QSPI Peripheral Chip Select (PCS1, PCS0 )
These output signals are the chip selects for the QSPI.
2.11 TIMER SIGNALS
The following external signals are used by the timer modules. See Section 8 Timer Modules for additional information on these signals.
2.11.1 Timer Gate (TGATE 2 )
This active-low input can be programmed to enable and disable the counters and prescalers. TGATE can also be programmed as a simple input.
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2.11.2 Timer Input (TIN)
This input can be programmed as a clock that causes events to occur in the counters and prescalers.
2.11.3 Timer Output (TOUT)
This output drives the various output waveforms generated by the timers.
2.12 TEST SIGNALS
The following signals are used with the on-board test logic defined by the IEEE 1149.1 standard. See Section 10 IEEE 1149.1 Test Access Port for more information on the use of these signals.
2.12.1 Test Clock (TCK)
This input provides a clock for on-board test logic defined by the IEEE 1149.1 standard.
2.12.2 Test Mode Select (TMS)
This input controls test mode operations for on-board test logic defined by the IEEE 1149.1 standard.
2.12.3 Test Data In (TDI)
This input is used for serial test instructions and test data for on-board test logic defined by the IEEE 1149.1 standard.
2.12.4 Test Data Out (TDO)
This output is used for serial test instructions and test data for on-board test logic defined by the IEEE 1149.1 standard.
2.13 REAL TIME CLOCK SIGNALS 2.13.1 Battery Switch (BSW)
This signal determines whether the entire chip is powered from V CC or only the real-time clock is powered from VBATT or VCC. See Section 4 System Integration Module for more information.
2.13.2 Battery Voltage (VBATT)
This pin supplies power to maintain the real-time clock when the rest of the chip is powered down. See Section 4 System Integration Module for more information.
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2.13.3 Real Time Clock Output (RMC/RTCOUT )
RTCOUT is an output signal that is selected by setting PPARC bit 2. The function is defined by RCR bits 3 and 4.
2.14 SYSTEM POWER AND GROUND (V CC AND GND)
These pins provide system power and ground to the MC68341. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression.
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SECTION 3 BUS OPERATION
This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and reset operation. Operation of the external bus is the same whether the MC68341 or an external device is the bus master; the names and descriptions of bus cycles are from the viewpoint of the bus master. For exact timing specifications, refer to Section 12 Electrical Characteristics. The MC68341 architecture supports byte, word, and long-word operands allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the SIZ1/SIZ0 outputs and DSACK1/DSACK0 inputs. The MC68341 requires word and longword operands to be located in memory on word boundaries. The only type of transfer that can be performed to an odd address is a single-byte transfer, referred to as an odd-byte transfer. For an 8-bit port, multiple bus cycles may be required for an operand transfer due to either misalignment or a word or long-word operand. The MC68341 also supports basic MC68000 bus interface timing compatibility, in addition to the normal M68300 bus interface timing used by other members of the M68300 family such as the MC68332 and MC68340. This 68000 bus support allows ASICs and other custom logic developed for MC68000-style buses to more easily migrate to the MC68341. In this section, reference to 68000 bus timing refers to bus cycle timing used by the MC68000, MC68EC000, MC68HC000, MC68HC001, MC68008, and MC68010.
3.1 68000 BUS MODE
The MC68341 bus interface is dynamically selectable between M68300 and 68000 bus timing, and is individually controlled for each chip select by programming the Bus Select Register (BSR) in the SIM41. Accesses which match a chip select configured for 68000 bus timing cause an 68000 bus access. All other accesses use normal M68300 bus cycle signals and timing. NOTE Bus cycle examples in this section show normal M68300 bus cycle timing unless specifically noted as an 68000 bus cycle. The three strobe signals AS68K , UDS , and LDS are dedicated for 68000 bus cycles. These signals assert only for 68000 bus cycles, while AS and DS assert only for M68300 bus cycles. The timing of shared signals CS, UWE, and LWE is modified depending on
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selection of the bus cycle type. All other bus interface signals retain the same timing and functionality between the two bus timing modes. The dual nature of the MC68341 bus interface can result in 68000 bus functionality which is not supported by the original MC68000. Designs which are intended to provide reverse compatibility to the MC68000 should not utilize this superset functionality. The following list notes differences between the 68000 bus timing implemented on the MC68341 and bus timing on the MC68000. * Address strobe AS68K negates between the read and write cycles of a read-modifywrite operation. * R/W transitions with address timing instead of with address strobe, and does not negate between writes. * On write cycles, the data bus is driven 1/2 clock sooner (during S2 rather than S3). * DSACK and BERR can be recognized on the falling edge of state S2 (one clock earlier than on the MC68000), allowing a three clock 68000 bus cycle. * Data strobes and write enables are asserted for aproximately one-half clock for a three-clock write cycle. * 68000 chip selects can be programmed for zero wait-state (three clock bus cycles) internal termination. Programming a 68000 chip select for fast termination (two clock bus cycles) results in undefined strobe timing. * The MC68341 recognizes late bus error and late retry on 68000 accesses. * The MC68341 supports dynamic bus sizing on 68000 accesses, allowing both 8-bit (DSACK0 termination) and 16-bit ( DSACK1 termination) port sizes. For an 8-bit port, UDS and LDS must be combined externally to obtain a single 68000 data strobe signal, since DS does not assert for 68000 bus accesses. * 68000 chip selects are programmed with AS68K timing instead of UDS /LDS . These selects contain the byte address information of UDS /LDS . * Upper and lower write enables (UWE and LWE) are provided to support a glueless interface to external SRAM. * DACK asserts with AS timing for both M68300 and 68000 bus cycles.
3.2 BUS TRANSFER SIGNALS
The bus transfers information between the MC68341 and external memory or a peripheral device. External devices can accept or provide 8 bits or 16 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is defined as the port width. The MC68341 contains an address bus that specifies the address for the transfer and a data bus that transfers the data. Control signals indicate the beginning and type of the cycle as well as the address space and size of the transfer. The selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity of the address and provide timing information for the data. Both asynchronous and synchronous operation is possible for any port width.
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In asynchronous operation, the bus and control input signals are internally synchronized to the MC68341 clock, introducing a delay. This delay is the time required for the MC68341 to sample an input signal, synchronize the input to the internal clocks, and determine whether it is high or low. In synchronous mode, the bus and control input signals must be timed to setup and hold times. Since no synchronization is needed, bus cycles can be completed in three clock cycles in this mode. Additionally, using the fast-termination option of the chip select signals, two-clock operation is possible. Furthermore, for all inputs, the MC68341 latches the level of the input during a sample window around the falling edge of the clock signal. This window is illustrated in Figure 3-1, where t su and t h are the input setup and hold times, respectively. To ensure that an input signal is recognized on a specific falling edge of the clock, that input must be stable during the sample window. If an input makes a transition during the window time period, the level recognized by the MC68341 is not predictable; however, the MC68341 always resolves the latched level to either a logic high or low before using it. In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section.
t su th
CLKOUT
EXT
SAMPLE WINDOW
Figure 3-1. Input Sample Window NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false.
3.2.1 Bus Control Signals
The MC68341 initiates a bus cycle by driving the A31-A0, SIZx, FCx, and R/W outputs. At the beginning of a bus cycle, SIZ1 and SIZ0 are driven with FC3-FC0. SIZ1 and SIZ0 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles). Table 3-1 lists the encoding of the SIZx signal. These signals are valid while AS or AS68K is asserted. The R/W signal determines the
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direction of the transfer during a bus cycle. Driven at the beginning of a bus cycle, R/W is valid while AS or AS68K is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for consecutive write cycles. The RMC signal is asserted at the beginning of the first bus cycle of a read-modify-write operation and remains asserted until completion of the final bus cycle of the operation. Table 3-1. SIZx Signal Encoding
SIZ1 0 1 1 0 SIZ0 1 0 1 0 Transfer Size Byte Word Three Bytes Long Word
3.2.2 Function Code Signals
FC3-FC0 are outputs that indicate one of 16 address spaces to which the address applies. Fifteen of these spaces are designated as either user or supervisor, program or data, and normal or direct memory access (DMA) spaces. One other address space is designated as CPU space to allow the CPU32 to acquire specific control information not normally associated with read or write bus cycles. FC3-FC0 are valid while AS or AS68K is asserted. Function codes (see Table 3-2) can be considered as extensions of the 32-bit address that can provide up to 16 different 4-Gbyte address spaces. Function codes are automatically generated by the CPU32 to select address spaces for data and program at both user and supervisor privilege levels, a CPU address space for processor functions, and an alternate master address space. User programs access only their own program and data areas to increase protection of system integrity and can be restricted from accessing other information. The S-bit in the CPU32 status register is set for supervisor accesses and cleared for user accesses to provide differentiation. Refer to 3.5 CPU Space Cycles for more information. Function code FC3 is multiplexed with DTC, and the ability to use FC3 is lost if DTC is selected. If DMA transfers are programmed with FC3 set, this signal can be used externally to distinguish DMA bus activity from CPU accesses.
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Table 3-2. Address Space Encoding
Function Code Bits 3 0 0 0 0 0 0 0 0 1 2 0 0 0 0 1 1 1 1 x 1 0 0 1 1 0 0 1 1 x 0 0 1 0 1 0 1 0 1 x Address Spaces Reserved (Motorola) User Data Space User Program Space Reserved (User ) Reserved (Motorola) Supervisor Data Space Supervisor Program Space CPU Space DMA Space
3.2.3 Address Bus (A31-A0)
These signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MC68341 places the address on the bus at the beginning of a bus cycle. The address is valid while AS or AS68K is asserted.
3.2.4 Address Strobe (AS)
This output timing signal indicates the validity of many control signals and the address on the address bus. AS is asserted for M68300 bus cycles approximately one-half clock cycle after the beginning of a bus cycle. AS remains negated for a 68000 bus cycle.
3.2.5 68000 Address Strobe (AS68K)
AS68K is asserted for 68000 bus cycles approximately one clock cycle after the beginning of a bus cycle. AS68K remains negated for normal M68300 bus cycles.
3.2.6 Data Bus (D15-D0)
This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68341. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68341 on the last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68341 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle, or at the same time as AS68K is asserted.
3.2.7 Data Strobe (DS)
DS is an M68300 output timing signal that applies to the data bus. For an M68300 read cycle, the MC68341 asserts DS and AS simultaneously to signal the external device to place data on the bus. For an M68300 write cycle, DS signals to the external device that the data to be written is valid. The MC68341 asserts DS approximately one clock cycle
MOTOROLA MC68341 USER'S MANUAL 3-5
after the assertion of AS during a write cycle. DS remains negated during 68000 bus cycles.
3.2.8 Upper and Lower Data Strobes (UDS and
LDS)
UDS and LDS are asserted for the active bytes of a 68000 bus cycle, one-half clock later than DS on the corresponding M68300 bus cycle. UDS is asserted to select the upper 8 bits of the data bus (D15-D0) and LDS is asserted for the lower 8 bits (D8-D0). UDS and LDS remain negated for normal M68300 bus cycles.
3.2.9 Upper and Lower Write Enables (UWE and LWE)
On a write cycle to a 16-bit port, these active-low output signals indicate when the upper or lower eight bits of the data bus contain valid data. The upper write enable (UWE ) indicates that the upper eight bits of the data bus contain valid data during a write cycle. The lower write enable (LWE ) indicates that the lower eight bits of the data bus contain valid data during a write cycle. The equations of the byte write enables are as follows: 68300 bus cycle: 68000 bus cycle: UWE = R/W + DS + A0 LWE = R/W + DS + (A0 * SIZ0) UWE = R/W + UDS LWE = R/W + LDS
3.2.10 Data Transfer Complete (DTC)
This active-low output signal indicates the last clock of a normally terminated bus cycle. DTC does not assert for bus cycles terminated with normal bus error or normal retry terminations, but does assert for late bus error and late retry.
3.2.11 Bus Cycle Termination Signals
The following signals can terminate a bus cycle. 3.2.11.1 DATA TRANSFER AND SIZE ACKNOWLEDGE SIGNALS (DSACK1 AND DSACK0). During bus cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol. During a read cycle, this signals the MC68341 to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate. These signals also indicate to the MC68341 the size of the port for the bus cycle just completed (see Table 3-3). Refer to 3.4.1 Read Cycle for timing relationships of DSACK1 and DSACK0. Additionally, the system integration module (SIM41) chip select address mask register can be programmed to internally generate DSACK1 and DSACK0 for external accesses, eliminating logic required to generate these signals. However, if external DSACK signals are returned earlier than indicated by the EDS and DD bits in the chip select address mask register, the cycle will terminate sooner than programmed. Refer to Section 4 System Integration Module for additional information. The SIM41 can alternatively be
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programmed to generate a fast termination cycle, providing a two-cycle external access. Refer to 3.3.6 Fast Termination Cycles for additional information on these cycles. 3.1.11.2 BUS ERROR (BERR ). This signal is also a bus cycle termination indicator and can be used in the absence of DSACK to indicate a bus error condition. BERR can also be asserted in conjunction with DSACK to indicate a bus error condition, provided it meets the appropriate timing described in this section and in Section 12 Electrical Characteristics. Additionally, BERR and HALT can be asserted together to indicate a retry termination. Refer to 3.6 Bus Exception Control Cycles for additional information on the use of these signals. The internal bus monitor can be used to generate an internal bus error signal for internal and internal-to-external transfers. If the bus cycles of an external bus master are to be monitored, external BERR generation must be provided since the internal bus error monitor has no information about transfers initiated by an external bus master. 3.2.11.3 AUTOVECTOR (AVEC).This signal can be used to terminate interrupt acknowledge cycles, indicating that the MC68341 should internally generate a vector (autovector) number to locate an interrupt handler routine. AVEC can be generated either externally or internally by the SIM41 (see Section 4 System Integration Module for additional information). AVEC is ignored during all other bus cycles.
3.3 DATA TRANSFER MECHANISM
The MC68341 supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by DSACK1 and DSACK0. The MC68341 also supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of synchronous cycles controlled by the fast termination capability of the SIM41.
3.3.1 Dynamic Bus Sizing
The MC68341 dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device signals its port size (byte or word) and indicates completion of the bus cycle to the MC68341 through the use of the DSACK inputs. Refer to Table 3-3 for DSACK encoding.
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Table 3-3.
DSACK Encoding
Result
DSACK1
1 (Negated) 1 (Negated) 0 (Asserted) 0 (Asserted)
DSACK0
1 (Negated) 0 (Asserted) 1 (Negated) 0 (Asserted)
Insert Wait States in Current Bus Cycle Complete Cycle--Data Bus Port Size Is 8 Bits Complete Cycle--Data Bus Port Size Is 16 Bits Reserved--Defaults to 16-Bit Port Size Can Be Used for 32-Bit DMA cycles
For example, if the MC68341 is executing an instruction that reads a long-word operand from a 16-bit port, the MC68341 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation from an 8-bit port is similar, but requires four read cycles. The addressed device uses DSACK to indicate the port width. For instance, a 16-bit device always returns DSACK for a 16-bit port (regardless of whether the bus cycle is a byte or word operation). Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 16-bit port must reside on data bus bits 15-0, and an 8-bit port must reside on data bus bits 15-8. This requirement minimizes the number of bus cycles needed to transfer data to 8- and 16-bit ports and ensures that the MC68341 correctly transfers valid data. The MC68341 always attempts to transfer the maximum amount of data on all bus cycles; for a word operation, it always assumes that the port is 16 bits wide when beginning the bus cycle. The bytes of operands are designated as shown in Figure 3-2. The most significant byte of a long-word operand is OP0, and OP3 is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and OP1. The single byte of a byte-length operand is OP0. These designations are used in the figures and descriptions that follow. Figure 3-2 shows the required organization of data ports on the MC68341 bus for both 8- and 16-bit devices. The four bytes shown in Figure 3-2 are connected through the internal data bus and data multiplexer to the external data bus. The data multiplexer establishes the necessary connections for different combinations of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. The positioning of bytes is determined by the SIZ1/SIZ0 and A0 outputs. The SIZ1/SIZ0 outputs indicate the number of bytes to be transferred during the current bus cycle (see Table 3-1). The number of bytes transferred during a read or write bus cycle is equal to or less than the size indicated by the SIZ1/SIZ0 outputs, depending on port width. For example, during the first bus cycle of a long-word transfer to a word port, the size outputs indicate that four bytes are to be transferred although only two bytes are moved on that bus cycle. The address line A0 also affects the operation of the data multiplexer. During an operand transfer, A31-A1 indicate the word base address of that portion of the operand to be
3-8 MC68341 USER'S MANUAL MOTOROLA
accessed, and A0 indicates the byte offset from the base (i.e., either odd or even byte). Figure 3-2 lists the bytes required on the data bus for read cycles. The entries shown as OPn are portions of the requested operand that are read or written during that bus cycle and are defined by SIZ1/SIZ0 and A0 for the bus cycle.
OPERAND 31
OP0 23
OP1 OP0 15
OP2 OP1 OP0 7
OP3 OP2 OP1 OP0 0
Case (a) (b) (c) (d) (e) (f) (g)
Transfer Case Byte to Byte Byte to Word (Even) Byte to Word (Odd) Word to Byte (Aligned) Word to Word (Aligned) Long Word to Byte (Aligned) Long Word to Word (Aligned) SIZ1 0 0 0 1 1 0 0 SIZ0 1 1 1 0 0 0 0 A0 X 0 1 0 0 0 0 DSACK1 DSACK0 1 0 0 X 0 X 1 0 0 X 1 0 0 X
D15
Data Bus D8 D7 D0 (OP0) OP0 (OP0) OP0 (OP0) OP0 (OP1) OP0 OP1 OP0 (OP1) OP0 OP0 OP1
NOTES: 1. Operands in parentheses are ignored by the MC68340 during read cycles. 2. A 3-byte to byte transfer does occur as the second byte transfer of a long-word to byte port transfer.
Figure 3-2. MC68341 Interface to Various Port Sizes
3.3.2 Misaligned Operands
In this architecture, the basic operand size is 16 bits. Operand misalignment refers to whether an operand is aligned on a word boundary or overlaps the word boundary, determined by address line A0. When A0 is low, the address is even and is a word and byte boundary. When A0 is high, the address is odd and is a byte boundary only. A byte operand is properly aligned at any address; a word or long-word operand is misaligned at an odd address. At most, each bus cycle can transfer a word of data aligned on a word boundary. If the MC68341 transfers a long-word operand over a 16-bit port, the most significant operand word is transferred on the first bus cycle, and the least significant operand word is transferred on a following bus cycle. The CPU32 restricts all operands (both data and instructions) to be aligned. That is, word and long-word operands must be located on a word or long-word boundary, respectively. The only type of transfer that can be performed to an odd address is a single-byte transfer, referred to as an odd-byte transfer. If a misaligned access is attempted, the CPU32 generates an address error exception, and enters exception processing. Refer to Section 5 CPU32 for more information on exception processing.
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3.3.3 Operand Transfer Cases
The following cases are examples of the allowable alignments of operands to ports. 3.3.3.1 BYTE OPERAND TO 8-BIT PORT, ODD OR EVEN (A0 = X). The MC68341 drives the address bus with the desired address and the SIZx pins to indicate a singlebyte operand.
BYTE OPERAND 7 DATA BUS CYCLE 1
OP0 0 SIZ1 0 SIZ0 1 A0 X DSACK1 DSACK0 1 0
D15 D8 D7 D0 OP0 (OP0)
For a read operation, the slave responds by placing data on bits 15-8 of the data bus, asserting DSACK0 and negating DSACK1 to indicate an 8-bit port. The MC68341 then reads the operand byte from bits 15-8 and ignores bits 7-0. For a write operation, the MC68341 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read. The slave device reads the byte operand from bits 15-8 and places the operand in the specified location. The slave then asserts DSACK0 to terminate the bus cycle. 3.3.3.2 BYTE OPERAND TO 16-BIT PORT, EVEN (A0 = 0). The MC68341 drives the address bus with the desired address and the SIZx pins to indicate a single-byte operand.
BYTE OPERAND 7 DATA BUS CYCLE 1 D15
OP0 0 D8 D7 D0 (OP0) SIZ1 0 SIZ0 1 A0 0 DSACK1 DSACK0 0 X
OP0
For a read operation, the slave responds by placing data on bits 15-8 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68341 then reads the operand byte from bits 15-8 and ignores bits 7-0. For a write operation, the MC68341 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read. The slave device reads the operand from bits 15-8 of the data bus and uses the address to place the operand in the specified location. The slave then asserts DSACK1 to terminate the bus cycle.
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3.3.3.3 BYTE OPERAND TO 16-BIT PORT, ODD (A0 = 1). The MC68341 drives the address bus with the desired address and the SIZx pins to indicate a single-byte operand.
BYTE OPERAND 7 DATA BUS CYCLE 1
OP0 0 SIZ1 0 SIZ0 1 A0 1 DSACK1 DSACK0 0 X
D15 D8 D7 D0 (OP0) OP0
For a read operation, the slave responds by placing data on bits 7-0 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68341 then reads the operand byte from bits 7-0 and ignores bits 15-8. For a write operation, the MC68341 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read. The slave device reads the operand from bits 7-0 of the data bus and uses the address to place the operand in the specified location. The slave then asserts DSACK1 to terminate the bus cycle. 3.3.3.4 WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68341 drives the address bus with the desired address and the SIZx pins to indicate a word operand.
WORD OPERAND 15
OP0 87
OP1 0 SIZ1 1 0 SIZ0 0 1 A0 0 1 DSACK1 DSACK0 1 0 1 0
DATA BUS D15 D8 D7 D0 (OP1) OP0 CYCLE 1 (OP1) OP1 CYCLE 2
For a read operation, the slave responds by placing the most significant byte of the operand on bits 15-8 of the data bus and asserting DSACK0 to indicate an 8-bit port. The MC68341 reads the most significant byte of the operand from bits 15-8 and ignores bits 7-0. The MC68341 then decrements the transfer size counter, increments the address, and reads the least significant byte of the operand from bits 15-8 of the data bus. For a write operation, the MC68341 drives the word operand on bits 15-0 of the data bus. The slave device then reads the most significant byte of the operand from bits 15-8 of the data bus and asserts DSACK0 to indicate that it received the data but is an 8-bit port. The MC68341 then decrements the transfer size counter, increments the address, and writes the least significant byte of the operand to bits 15-8 of the data bus.
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3.3.3.5 WORD OPERAND TO 16-BIT PORT, ALIGNED. The MC68341 drives the address bus with the desired address and the size pins to indicate a word operand.
WORD OPERAND 15
OP0
OP1 0 SIZ1 1 SIZ0 0 A0 0 DSACK1 DSACK0 0 X
D15 D8 D7 D0 DATA BUS CYCLE 1 OP0 OP1
For a read operation, the slave responds by placing the data on bits 15-0 of the data bus and asserting DSACK1 to indicate a 16-bit port. When DSACK1 is asserted, the MC68341 reads the data on the data bus and terminates the cycle. For a write operation, the MC68341 drives the word operand on bits 15-0 of the data bus. The slave device then reads the entire operand from bits 15-0 of the data bus and asserts DSACK1 to terminate the bus cycle. 3.3.3.6 LONG-WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68341 drives the address bus with the desired address and the SIZx pins to indicate a long-word operand.
LONG-WORD OPERAND 31 DATA BUS CYCLE 1 CYCLE 2 CYCLE 3 CYCLE 4 D15
OP0 23
OP1 15
OP2 7
OP3 0 SIZ0 0 1 0 1 A0 0 1 0 1 DSACK1 DSACK0 1 0 1 0 1 0 1 0
OP0 OP1 OP2 OP3
D8 D7 D0 (OP1) (OP1) (OP3) (OP3)
SIZ1 0 1 1 0
For a read operation, shown in Figure 3-3, the slave responds by placing the most significant byte of the operand on bits 15-8 of the data bus and asserting DSACK0 to indicate an 8-bit port. The MC68341 reads the most significant byte of the operand (byte 0) from bits 15-8 and ignores bits 7-0. The MC68341 then decrements the transfer size counter, increments the address, initiates a new cycle, and reads byte 1 of the operand from bits 15-8 of the data bus. The MC68341 repeats the process of decrementing the transfer size counter, incrementing the address, initiating a new cycle, and reading a byte to transfer the remaining two bytes. For a write operation, shown in Figure 3-4, the MC68341 drives the two most significant bytes of the operand on bits 15-0 of the data bus. The slave device then reads only the most significant byte of the operand (byte 0) from bits 15-8 of the data bus and asserts DSACK0 to indicate reception and an 8-bit port. The MC68341 then decrements the transfer size counter, increments the address, and writes byte 1 of the operand to bits 15-8 of the data bus. The MC68341 continues to decrement the transfer size counter, increment the address, and write a byte to transfer the remaining two bytes to the slave device.
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S0 CLKOUT
S2
S4
S0
S2
S4
S0
S2
S4
S0
S2
S4
A31-A0
FC3-FC0
R/W
AS
DS
SIZ0 4 BYTES SIZ1 DSACK0 3 BYTES 2 BYTES 1 BYTE
DSACK1
D15-D8
OP0
OP1
OP2
OP3
D7-D0 BYTE READ BYTE BYTE READ READ LONG-WORD OPERAND READ FROM 8-BIT BUS BYTE READ
Figure 3-3. Long-Word Operand Read Timing from 8-Bit Port
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S0 CLKOUT
S2
S4
S0
S2
S4
S0
S2
S4
S0
S2
S4
A31-A0
FC3-FC0
R/W
AS
DS
SIZ0 4 BYTES SIZ1 3 BYTES 2 BYTES 1 BYTE
DSACK0
DSACK1
D15-D8
OP0
OP1
OP2
OP3
D7-D0
(OP1) WRITE
(OP1) WRITE
(OP3) WRITE
(OP3) WRITE
LONG-WORD OPERAND WRITE TO 8-BIT BUS
Figure 3-4. Long-Word Operand Write Timing to 8-Bit Port 3.3.3.7 LONG-WORD OPERAND TO 16-BIT PORT, ALIGNED. Figure 3-5 shows both long-word and word read and write timing to a 16-bit port.
LONG-WORD OPERAND 31 DATA BUS CYCLE 1 CYCLE 2 D15
OP0 23 D8 D7 OP0 OP2
OP1 15 D0 OP1 OP3
OP2 7 SIZ1 0 1
OP3 0 SIZ0 0 0 A0 0 0 DSACK1 DSACK0 0 X 0 X
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S0 CLKOUT
S2
S4
S0
S2
S4
S0
S2
S4
S0
S2
S4
S0
S2
S4
S0
S2
S4
A31-A0
FC3-FC0
R/W
AS
DS
SIZ0 4 BYTES SIZ1 2 BYTES 2 BYTES 4 BYTES 2 BYTES 2 BYTES
DSACK0
DSACK1
D15-D8
OP0
OP2
OP0
OP0
OP2
OP0
D7-D0
OP1
OP3
OP1
OP1
OP3
OP1 WORD WRITE TO 16-BIT BUS
LONG WORD READ FROM 16-BIT BUS
WORD READ FROM 16-BIT BUS
LONG WORD WRITE TO 16-BIT BUS
Figure 3-5. Long-Word and Word Read and Write Timing--16-Bit Port The MC68341 drives the address bus with the desired address and drives the SIZx pins to indicate a long-word operand. For a read operation, the slave responds by placing the two most significant bytes of the operand on bits 15-0 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68341 reads the two most significant bytes of the operand (bytes 0 and 1) from bits 15-0. The MC68341 then decrements the transfer size counter by 2, increments the address by 2, initiates a new cycle, and reads bytes 2 and 3 of the operand from bits 15-0 of the data bus. For a write operation, the MC68341 drives the two most significant bytes of the operand on bits 15-0 of the data bus. The slave device then reads the two most significant bytes of the operand (bytes 0 and 1) from bits 15-0 of the data bus and asserts DSACK1 to indicate reception and a 16-bit port. The MC68341 then decrements the transfer size counter by 2, increments the address by 2, and writes bytes 2 and 3 of the operand to bits 15-0 of the data bus.
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3.3.4 Bus Operation
The MC68341 bus is asynchronous, allowing external devices connected to the bus to operate at clock frequencies different from the clock for the MC68341. Bus operation uses the handshake lines (AS, DS , DSACK1/DSACK0 , BERR , and HALT) to control data transfers. AS signals a valid address on the address bus, and DS is used as a condition for valid data on a write cycle. Decoding the SIZx outputs and lower address line A0 provides strobes that select the active portion of the data bus. The slave device (memory or peripheral) responds by placing the requested data on the correct portion of the data bus for a read cycle or by latching the data on a write cycle; the slave asserts the DSACK1/ DSACK0 combination that corresponds to the port size to terminate the cycle. Alternatively, the can be programmed to assert the DSACK1/ DSACK0 combination internally and respond for the slave. If no slave responds or the access is invalid, external control logic may assert BERR to abort the bus cycle or BERR with HALT to retry the bus cycle. DSACK can be asserted before the data from a slave device is valid on a read cycle. The length of time that DSACK may precede data must not exceed a specified value in any asynchronous system to ensure that valid data is latched into the MC68341. (See Section 12 Electrical Characteristics for timing parameters.) Note that no maximum time is specified from the assertion of AS to the assertion of DSACK . Although the MC68341 can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK, the MC68341 inserts wait cycles in clock-period increments until DSACK is recognized. BERR and/or HALT can be asserted after DSACK is asserted. BERR and or HALT must be asserted within the time specified after DSACK is asserted in any asynchronous system. If this maximum delay time is violated, the MC68341 may exhibit erratic behavior.
3.3.5 Synchronous Operation with DSACK
Although cycles terminated with DSACK are classified as asynchronous, cycles terminated with DSACK can also operate synchronously in that signals are interpreted relative to clock edges. The devices that use these cycles must synchronize the response to the MC68341 clock (CLKOUT) to be synchronous. Since the devices terminate bus cycles with DSACK , the dynamic bus sizing capabilities of the MC68341 are available. The minimum cycle time for these cycles is also three clocks. To support systems that use the system clock to generate DSACK and other asynchronous inputs, the asynchronous input setup time and the asynchronous input hold time are given. If the setup and hold times are met for the assertion or negation of a signal such as DSACK , the MC68341 is guaranteed to recognize that signal level on that specific falling edge of the system clock. If the assertion of DSACK is recognized on a particular falling edge of the clock, valid data is latched into the MC68341 (for a read cycle) on the next falling clock edge if the data meets the data setup time. In this case, the parameter for asynchronous operation can be ignored. The timing parameters are described in Section 12 Electrical Characteristics. If a system asserts DSACK for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACK (and/or BERR /HALT) until and
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throughout the clock edge that negates AS (with the appropriate asynchronous input hold time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles terminated with DSACK (three clocks per cycle). When BERR (or BERR and HALT) is asserted after DSACK , BERR (and HALT) must meet the appropriate setup time prior to the falling clock edge one clock cycle after DSACK is recognized. This setup time is critical, and the MC68341 may exhibit erratic behavior if it is violated. When operating synchronously, the data-in setup and hold times for synchronous cycles may be used instead of the timing requirements for data relative to DS .
3.3.6 Fast Termination Cycles
With an external device that has a fast access time, the fast termination capability of the chip select circuit can provide a two-clock external bus transfer. Since the chip select circuits are driven from the system clock, the bus cycle termination is inherently synchronized with the system clock. Refer to Section 4 System Integration Module for more information on chip selects. Fast termination can only be used for M68300 bus cycles. To use the fast termination option, an external device should be fast enough to have data ready, within the specified setup time, by the falling edge of S4. Figure 3-6 shows the DSACK timing for a read with two wait states, followed by a fast termination read and write. When using the fast termination option, DS is asserted only in a read cycle, not in a write cycle.
S0 S1 S2 S3 SW SW* SW SW* S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 CLKOUT
AS
DS UWE, LWE
R/W
DSACKx
D15-D0
DTC
TWO WAIT STATES IN READ
FAST TERMINATION READ
FAST TERMINATION WRITE
* DSACKx only internally asserted for fast termination cycles.
Figure 3-6. Fast Termination Timing
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3.4 DATA TRANSFER CYCLES
The transfer of data between the MC68341 and other devices involves the following signals: * Address Bus A31-A0 * Data Bus D15-D0 * Control Signals The address bus and data bus are parallel, nonmultiplexed buses. The bus master moves data on the bus by issuing control signals, and the bus uses a handshake protocol to ensure correct movement of the data. In all bus cycles, the bus master is responsible for de-skewing all signals it issues at both the start and end of the cycle. In addition, the bus master is responsible for de-skewing the acknowledge and data signals from the slave devices. The following paragraphs define read, write, and read-modify-write cycle operations. Each bus cycle is defined as a succession of states that apply to the bus operation. These states are different from the MC68341 states described for the CPU32. The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock frequency. Bus operations are described in terms of external bus states.
3.4.1 M68300 Read Cycle
During a read cycle, the MC68341 receives data from a memory or peripheral device. If the instruction specifies a long-word or word operation, the MC68341 attempts to read two bytes at once. For a byte operation, the MC68341 reads one byte. The section of the data bus from which each byte is read depends on the operand size, address signal A0, and the port size. Refer to 3.3.1 Dynamic Bus Sizing and 3.3.2 Misaligned Operands for more information. Figure 3-7 is a flowchart of a word read cycle. Figure 3-8 is an example of a functional timing diagram of a read bus cycle specified in terms of clock periods.
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BUS MASTER ADDRESS DEVICE 1. 2. 3. 4. 5. SET R/W TO READ DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION CODE ON FC3-FC0 DRIVE SIZE PINS FOR OPERAND SIZE ASSERT AS AND DS
SLAVE
PRESENT DATA 1. DECODE ADDRESS 2. PLACE DATA ON D15-D0 3. DRIVE DSACKx SIGNALS
ACQUIRE DATA 1. LATCH DATA 2. NEGATE AS AND DS
TERMINATE CYCLE 1. REMOVE DATA FROM D15-D0 2. NEGATE DSACKx
START NEXT CYCLE
Figure 3-7. Word Read Cycle Flowchart State 0--The read cycle starts in state 0 (S0). During S0, the MC68341 places a valid address on A31-A0 and valid function codes on FC3-FC0. The function codes select the address space for the cycle. The MC68341 drives R/W high for a read cycle. SIZ1/SIZ0 become valid, indicating the number of bytes requested for transfer. State 1--One-half clock later, in state 1 (S1), the MC68341 asserts AS indicating a valid address on the address bus. The MC68341 also asserts DS during S1. The selected device uses R/W, SIZ1 or SIZ0, A0, and DS to place its information on the data bus. One or both of the bytes (D15-D8 and D7-D0) are selected by SIZ1/SIZ0 and A0. State 2--As long as at least one of the DSACK signals is recognized on the falling edge of S2 (meeting the asynchronous input setup time requirement), data is latched on the falling edge of S4, and the cycle terminates. State 3--If DSACK is not recognized by the start of state 3 (S3), the MC68341 inserts wait states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68341 continues to sample DSACK on the falling edges of the clock until one is recognized. State 4--DTC asserts during S4 to indicate the end of the current bus cycle. At the falling edge of state 4 (S4), the MC68341 latches the incoming data and samples DSACK to get the port size. State 5--The MC68341 negates AS and DS during state 5 (S5), and negates DTC after the rising edge of S5. It holds the address valid during S5 to provide address hold time for memory systems. R/W, SIZ1 and SIZ0, and FC3-FC0 also remain valid throughout S5. The external device keeps its data and DSACK signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and
MOTOROLA MC68341 USER'S MANUAL 3-19
negate DSACK within approximately one clock period after sensing the negation of AS or DS. DSACK signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle.
S0 CLKOUT A31-A2 S2 S4 S0 S2 S4 S0 S2 S4
A1 A0 FC3-FC0
SIZ1 WORD SIZ0 BYTE
R/W
AS
CSx DS
AS68K UDS, LDS UWE, LWE DSACK
DTC D15-D8
OP2
OP3
D7-D0 WORD READ
OP3 BYTE READ BYTE READ
OP3
Figure 3-8. Read Cycle Timing
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MC68341 USER'S MANUAL
MOTOROLA
3.4.2 68000 Read Cycle
During a 68000 read cycle, the 68000 strobes AS68K, UDS , and LDS are asserted instead of AS and DS , with timing compatible with MC68000 bus cycles. Although the dynamic bus sizing capability of the MC68341 allows assertion of either DSACK1 or DSACK0 to terminate the bus cycle as a 16-bit or 8-bit access, UDS and LDS will always assert for a 16-bit bus. UDS and LDS must be combined into a single data strobe externally when used with an 8-bit 68000 bus. Figure 3-9 is a flowchart of a 68000 word read cycle. Figure 3-10 is an example of a functional timing diagram of a 68000 read bus cycle specified in terms of clock periods.
BUS MASTER ADDRESS DEVICE 1. 2. 3. 4. 5. SET R/W TO READ DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION CODE ON FC3-FC0 DRIVE SIZE PINS FOR OPERAND SIZE ASSERT AS68K AND UDS, LDS SLAVE
PRESENT DATA 1. DECODE ADDRESS 2. PLACE DATA ON D15-D0 3. DRIVE DSACKx SIGNALS
ACQUIRE DATA 1. LATCH DATA 2. NEGATE AS68K AND UDS, LDS
TERMINATE CYCLE 1. REMOVE DATA FROM D15-D0 2. NEGATE DSACKx
START NEXT CYCLE
Figure 3-9. 68000 Word Read Cycle Flowchart State 0--The read cycle starts in state 0 (S0). During S0, the MC68341 places a valid address on A31-A0 and valid function codes on FC3-FC0. The function codes select the address space for the cycle. The MC68341 drives R/W high for a read cycle. SIZ1/SIZ0 become valid, indicating the number of bytes requested for transfer. State 1--The MC68341 issues no new control signals during S1. State 2--In state 2 (S2), the MC68341 asserts AS68K indicating a valid address on the address bus. The MC68341 also asserts UDS/LDS during S2. The selected device uses R/W, UDS , and LDS to place its information on the data bus. The upper byte (D15-D8) and lower byte (D7-D0) are selected by assertion of UDS and LDS , respectively. If DSACK is recognized on the falling edge of S2 (meeting the asynchronous input setup time requirement), data is latched on the falling edge of S4, and the cycle terminates as a three clock bus cycle. State 3--If DSACK is not recognized by the start of state 3 (S3), the MC68341 inserts wait states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous
MOTOROLA MC68341 USER'S MANUAL 3-21
input setup and hold times around the end of S2. If wait states are added, the MC68341 continues to sample DSACK on the falling edges of the clock until one is recognized. State 4--DTC asserts during S4 to indicate the end of the current bus cycle. At the falling edge of state 4 (S4), the MC68341 latches the incoming data and samples DSACK to get the port size. State 5--The MC68341 negates AS68K and UDS/LDS during state 5 (S5), and negates DTC after the rising edge of S5. It holds the address valid during S5 to provide address hold time for memory systems. R/W, SIZ1 and SIZ0, and FC3-FC0 also remain valid throughout S5. The external device keeps its data and DSACK signals asserted until it detects the negation of AS68K or UDS/LDS (whichever it detects first). The device must remove its data and negate DSACK within approximately one clock period after sensing the negation of AS68K or UDS/LDS . DSACK signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle.
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S0 CLKOUT A31-A2
S2
S4
S0
S2
S4
S0
S2
S4
A1 A0 FC3-FC0
SIZ1 WORD SIZ0 BYTE
R/W
AS
CSx
DS
DSACK1
DSACK0 D31-D24 OP2
D23-D16
OP3
D15-D8
OP3
D7-D0 WORD READ BYTE READ BYTE READ
OP3
Figure 3-10. 68000 Read Cycle Timing
3.4.3 M68300 Write Cycle
During a write cycle, the MC68341 transfers data to memory or a peripheral device. Figure 3-11 is a flowchart of a word write cycle. Figure 3-12 is an example of a functional timing diagram of a write bus cycle specified in terms of clock periods.
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BUS MASTER ADDRESS DEVICE 1. 2. 3. 4. 5. 6. 7. SET R/W TO WRITE DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION CODE ON FC3-FC0 DRIVE SIZE PINS FOR OPERAND SIZE ASSERT AS PLACE DATA ON D15-D0 ASSERT DS AND UWE/LWE
SLAVE
ACCEPT DATA 1. DECODE ADDRESS 2. LATCH DATA FROM D15-D0 3. ASSERT DSACKx SIGNALS
TERMINATE OUTPUT TRANSFER 1. NEGATE AS, DS, AND UWE/LWE 2. REMOVE DATA FROM D15-D0
TERMINATE CYCLE
1. NEGATE DSACKx START NEXT CYCLE
Figure 3-11 Word Write Cycle Flowchart State 0--The write cycle starts in S0. During S0, the MC68341 places a valid address on A31-A0 and valid function codes on FC3-FC0. The function codes select the address space for the cycle. The MC68341 drives R/W low for a write cycle. SIZ1/SIZ0 become valid, indicating the number of bytes to be transferred. State 1--One-half clock later during S1, the MC68341 asserts AS, indicating a valid address on the address bus. State 2--During S2, the MC68341 places the data to be written onto D15-D0, and samples DSACK at the end of S2. State 3--The MC68341 asserts DS during S3, indicating that data is stable on the data bus. Write enable strobes UWE and LWE for the active bytes of the data bus are also asserted during S3. As long as at least one of the DSACK signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK is not recognized by the start of S3, the MC68341 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68341 continues to sample DSACK on the falling edges of the clock until one is recognized. The selected device uses R/W, SIZ1/SIZ0, and A0 to latch data from the appropriate byte(s) of D15-D8 and D7-D0. SIZ1/SIZ0 and A0 select the bytes of the data bus. If it has not already done so, the device asserts DSACK to signal that it has successfully stored the data. State 4--DTC asserts during S4 to indicate the end of the current bus cycle. State 5--The MC68341 negates AS and DS during S5, and negates DTC after the rising edge of S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/W, SIZ1/SIZ0, and FC3-FC0 also remain valid throughout S5. The
3-24 MC68341 USER'S MANUAL MOTOROLA
external device must keep DSACK asserted until it detects the negation of AS or D S (whichever it detects first). The device must negate DSACK within approximately one clock period after sensing the negation of AS or DS . DSACK signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle.
S0 CLKOUT A31-A2 S2 S4 S0 S2 S4 S0 S2 S4
A1 A0 FC3-FC0
SIZ1 WORD SIZ0 BYTE
R/W
AS
CSx DS
AS68K UDS, LDS UWE LWE
DSACK
DTC D15-D8
OP2
OP3
D7-D0 WORD WRITE
OP3 BYTE WRITE BYTE WRITE
OP3
Figure 3-12. M68300 Write Cycle Timing
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MC68341 USER'S MANUAL
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3.4.4 68000 Write Cycle
During a 68000 write cycle, the 68000 strobes AS68K , UDS , and LDS are asserted instead of AS and DS, with timing compatible with MC68000 bus cycles. Although the dynamic bus sizing capability of the MC68341 allows assertion of either DSACK1 or DSACK0 to terminate the bus cycle as a 16-bit or 8-bit access, UDS and LDS will always assert for a 16-bit bus. U D S and L D S must be combined into a single data strobe externally when used with an 8-bit 68000 bus. Figure 3-13 is a flowchart of a 68000 word write cycle. Figure 3-14 is an example of a functional timing diagram of a 68000 write bus cycle specified in terms of clock periods.
BUS MASTER ADDRESS DEVICE 1. 2. 3. 4. 5. 6. 7. SET R/W TO WRITE DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION CODE ON FC3-FC0 DRIVE SIZE PINS FOR OPERAND SIZE ASSERT AS68K PLACE DATA ON D15-D0 ASSERT UDS/LDS AND UWE/LWE SLAVE
ACCEPT DATA 1. DECODE ADDRESS 2. LATCH DATA FROM D15-D0 3. ASSERT DSACKx SIGNALS
TERMINATE OUTPUT TRANSFER 1. NEGATE AS68K, UDS/LDS AND UWE/LWE 2. REMOVE DATA FROM D15-D0
TERMINATE CYCLE
1. NEGATE DSACKx START NEXT CYCLE
Figure 3-13. 68000 Word Write Cycle Flowchart State 0--The write cycle starts in S0. During S0, the MC68341 places a valid address on A31-A0 and valid function codes on FC3-FC0. The function codes select the address space for the cycle. The MC68341 drives R/W low for a write cycle. SIZ1/SIZ0 become valid, indicating the number of bytes to be transferred. State 1--The MC68341 issues no new control signals during S1. State 2--In S2, the MC68341 asserts AS68K indicating a valid address on the address bus. During S2, the MC68341 places the data to be written onto D15-D0, and samples DSACK at the end of S2. State 3--The MC68341 asserts UDS /LDS after the rising edge of S3, indicating that data is stable on the data bus. Write enable strobes UWE and LWE for the active bytes of the data bus are also asserted after the rising edge of S3. As long as DSACK is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK is not recognized by the start of S3, the MC68341 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are
3-26 MC68341 USER'S MANUAL MOTOROLA
inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68341 continues to sample DSACK on the falling edges of the clock until one is recognized. The selected device uses R/W, UDS , and LDS (or UWE and LWE ) to latch data from the appropriate byte(s) of D15-D8 and D7-D0. If it has not already done so, the device asserts DSACK to signal that it has successfully stored the data. State 4--DTC asserts during S4 to indicate the end of the current bus cycle. State 5--The MC68341 negates AS68K and UDS/LDS during S5, and negates DTC after the rising edge of S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/W , SIZ1/SIZ0, and FC3-FC0 also remain valid throughout S5. The external device must keep DSACK asserted until it detects the negation of AS68K or UDS/LDS (whichever it detects first). The device must negate DSACK within approximately one clock period after sensing the negation of AS68K or UDS/LDS . DSACK signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle.
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MC68341 USER'S MANUAL
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S0 CLKOUT A31-A2
S2
S4
S0
S2
S4
S0
S2
S4
A1 A0 FC3-FC0
SIZ1 WORD SIZ0 BYTE
R/W AS68K
CSx DS
AS
UDS LDS UWE LWE
DSACK
DTC D15-D8
OP2
OP3
D7-D0 WORD WRITE
OP3 BYTE WRITE
OP3 BYTE WRITE
Figure 3-14. 68000 Write Cycle Timing
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3.4.5 Read-Modify-Write Cycle
The read-modify-write cycle performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. In the MC68341, this operation is indivisible, providing semaphore capabilities for multiprocessor systems. During the entire read-modify-write sequence, the MC68341 asserts RMC to indicate that an indivisible operation is occurring. The MC68341 does not issue a B G signal in response to a BR signal during this operation. Figure 3-15 is an example of a functional timing diagram of an M68300 read-modify-write instruction specified in terms of clock periods.
S0 CLK OUT
S2
S4
S0
S2
S4
S0
A31-A30
FC3-FC0
SIZ1-SIZ0
R/W
RMC
AS
DS
DSACKx
D15-D0 READ INDIVISIBLE CYCLE WRITE
Figure 3-15. Read-Modify-Write Cycle Timing State 0--The MC68341 asserts RMC in S0 to identify a read-modify-write cycle. The MC68341 places a valid address on A31-A0 and valid function codes on FC3-FC0. The function codes select the address space for the operation. SIZ1/SIZ0 become valid in S0 to indicate the operand size. The MC68341 drives R/W high for the read cycle. State 1--One-half clock later during S1, the MC68341 asserts A S indicating a valid address on the address bus. The MC68341 also asserts DS during S1.
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MC68341 USER'S MANUAL
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State 2--The selected device uses R/W, SIZ1/SIZ0, A0 , and DS to place information on the data bus. Either or both of the bytes (D15-D8 and D7-D0) are selected by SIZ1/SIZ0 and A0. Concurrently, the selected device may assert DSACK . State 3--As long as at least one of the DSACK signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), data is latched on the next falling edge of the clock, and the cycle terminates. If DSACK is not recognized by the start of S3, the MC68341 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68341 continues to sample the DSACK signals on the falling edges of the clock until one is recognized. State 4--At the end of S4, the MC68341 latches the incoming data. State 5--The MC68341 negates AS and DS during S5. If more than one read cycle is required to read in the operand(s), S0-S5 are repeated for each read cycle. When finished reading, the MC68341 holds the address, R/W, and FC3-FC0 valid in preparation for the write portion of the cycle. The external device keeps its data and DSACK signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove the data and negate DSACK within approximately one clock period after sensing the negation of AS or DS. DSACK signals that remain asserted beyond this limit may be prematurely detected for the next portion of the operation. Idle States--The MC68341 does not assert any new control signals during the idle states, but it may internally begin the modify portion of the cycle at this time. S0-S5 are omitted if no write cycle is required. If a write cycle is required, R/W remains in the read mode until S0 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S2. State 0--The MC68341 drives R/W low for a write cycle. Depending on the write operation to be performed, the address lines may change during S0. State 1--In S1, the MC68341 asserts AS, indicating a valid address on the address bus. State 2--During S2, the MC68341 places the data to be written onto D15-D0. State 3--The MC68341 asserts DS during S3, indicating stable data on the data bus. As long as at least one of the DSACK signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK is not recognized by the start of S3, the MC68341 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68341 continues to sample DSACK on the falling edges of the clock until one is recognized. The selected device uses R/W, DS, SIZ1/SIZ0, and A0 to latch data from the appropriate section(s) of D15-D8 and D7-D0. SIZ1/SIZ0 and A0 select the data bus sections. If it has not already done so, the device asserts DSACK when it has successfully stored the data.
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State 4--The MC68341 issues no new control signals during S4. State 5--The MC68341 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/W and FC3-FC0 also remain valid throughout S5. If more than one write cycle is required, states S0-S5 are repeated for each write cycle. The external device keeps DSACK asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACK within approximately one clock period after sensing the negation of AS or DS.
3.5 CPU SPACE CYCLES
FC3-FC0 select user and supervisor program and data areas. The area selected by FC3- FC0 = $7 is classified as the CPU space. The breakpoint acknowledge, LPSTOP broadcast, module base address register access, and interrupt acknowledge cycles described in the following paragraphs use CPU space. The CPU space type, which is encoded on A19-A16 during a CPU space operation, indicates the function that the MC68341 is performing. On the MC68341, four of the encodings are implemented as shown in Figure 3-16. All unused values are reserved by Motorola for additional CPU space types.
CPU SPACE CYCLES FUNCTION CODE BREAKPOINT ACKNOWLEDGE LOW-POWER STOP BROADCAST MODULE BASE ADDRESS REGISTER ACCESS INTERRUPT ACKNOWLEDGE 3 0 0111 3 0 0111 3 0 011 1 3 0 0111 ADDRESS BUS 19 16 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKPT# T 0 19 16 0 31 00 000 00 0000000111111111111111110 31 19 0 16 0000 000 0000000111111111100000000 31 0 19 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1 CPU SPACE TYPE FIELD
Figure 3-16. CPU Space Address Encoding
3.5.1 Breakpoint Acknowledge Cycle
The breakpoint acknowledge cycle allows external hardware to insert an instruction directly into the instruction pipeline as the program executes. The breakpoint acknowledge cycle is generated by the execution of a breakpoint instruction (BKPT) or the assertion of the BKPT pin. The T-bit state (shown in Figure 3-16) differentiates a software breakpoint cycle (T = 0) from a hardware breakpoint cycle (T = 1).
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MC68341 USER'S MANUAL
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When a BKPT instruction is executed (software breakpoint), the MC68341 performs a word read from CPU space, type 0, at an address corresponding to the breakpoint number (bits [2-0] of the BKPT opcode) on A4-A2, and the T-bit (A1) is cleared. If this bus cycle is terminated with BERR (i.e., no instruction word is available), the MC68341 then performs illegal instruction exception processing. If the bus cycle is terminated by DSACK , the MC68341 uses the data on D15-D0 (for 16-bit ports) or two reads from D15-D8 (for 8-bit ports) to replace the BKPT instruction in the internal instruction pipeline and then begins execution of that instruction. When the CPU32 acknowledges a BKPT pin assertion (hardware breakpoint) with background mode disabled, the CPU32 performs a word read from CPU space, type 0, at an address corresponding to all ones on A4-A2 (BKPT#7), and the T-bit (A1) is set. If this bus cycle is terminated by BERR , the MC68341 performs hardware breakpoint exception processing. If this bus cycle is terminated by DSACK , the MC68341 ignores data on the data bus and continues execution of the next instruction. NOTE The BKPT pin is sampled on the same clock phase as data and is latched with data as it enters the CPU32 pipeline. If BKPT is asserted for only one bus cycle and a pipeline flush occurs before BKPT is detected by the CPU32, BKPT is ignored. To ensure detection of BKPT by the CPU32, BKPT can be asserted until a breakpoint acknowledge cycle is recognized. The breakpoint operation flowchart is shown in Figure 3-17. Figures 3-18 and 3-19 show the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes supplied on the cycle and with an exception signaled, respectively.
3.5.2 LPSTOP Broadcast Cycle
The low power stop (LPSTOP) broadcast cycle is generated by the CPU32 executing the LPSTOP instruction. Since the external bus interface must get a copy of the interrupt mask level from the CPU32, the CPU32 performs a CPU space type 3 write with the mask level encoded on the data bus, as shown in the following figure. The CPU space type 3 cycle waits for the bus to be available, and is shown externally to indicate to external devices that the MC68341 is going into LPSTOP mode. If an external device requires additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT. The SIM41 provides internal DSACK response to this cycle. For more information on how the SIM41 responds to LPSTOP mode, see Section 4 System Integration Module.
15 -- 14 -- 13 -- 12 -- 11 -- 10 -- 9 -- 8 -- 7 -- 6 -- 5 -- 4 -- 3 -- 2 I2 1 I1 0 I0
I2-I0--Interrupt Mask Level The interrupt mask level is encoded on bits 2-0 of the data bus during an LPSTOP broadcast.
3-32 MC68341 USER'S MANUAL MOTOROLA
BREAKPOINT OPERATION FLOW PROCESSOR ACKNOWLEDGE BREAKPOINT IF BREAKPOINT INSTRUCTION EXECUTED: 1. SET R/W TO READ 2. SET FUNCTION CODE TO CPU SPACE 3. PLACE CPU SPACE TYPE 0 ON A19-A16 4. PLACE BREAKPOINT NUMBER ON A2-A4 5. CLEAR T-BIT (A1) 6. SET SIZE TO WORD 7. ASSERT AS AND DS IF BKPT PIN ASSERTED: 1. SET R/W TO READ 2. SET FUNCTION CODE TO CPU SPACE 3. PLACE CPU SPACE TYPE 0 ON A19-A16 4. PLACE ALL ONE'S ON A4-A2 5. SET T-BIT (A-1) TO ONE 6. SET SIZE TO WORD 7. ASSERT AS AND DS
EXTERNAL DEVICE
IF BREAKPOINT INSTRUCTION EXECUTED AND DSACKx IS ASSERTED: 1. LATCH DATA 2. NEGATE AS AND DS 3. GO TO (A) IF BKPT PIN ASSERTED AND DSACKx IS ASSERTED: 1. NEGATE AS AND DS 2. GO TO (A) IF BERR ASSERTED: 1. NEGATE AS AND DS 2. GO TO (B) (A) (B)
IF BREAKPOINT INSTRUCTION EXECUTED: 1. PLACE REPLACEMENT OPCODE ON DATA BUS 2. ASSERT DSACKx -OR1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING IF BKPT PIN ASSERTED: 1. ASSERT DSACKx -OR1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING
1. NEGATE DSACKx or BERR IF BREAKPOINT INSTRUCTION EXECUTED: 1. PLACE LATCHED DATA IN INSTRUCTION PIPELINE 2. CONTINUE PROCESSING IF BKPT PIN ASSERTED: 1. CONTINUE PROCESSING
IF BREAKPOINT INSTRUCTION EXECUTED: 1. INITIATE ILLEGAL INSTRUCTION PROCESSING IF BKPT PIN ASSERTED: 1. INITIATE HARDWARE BREAKPOINT PROCESSING
Figure 3-17. Breakpoint Operation Flowchart
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MC68341 USER'S MANUAL
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S0 CLKOUT
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
S0
A31-A20
A19-A16
BREAKPOINT ENCODING (0000)
A4-A1
BREAKPOINT NUMBER/T-BIT
A15-A5,A0
FC3-FC0
CPU SPACE
SIZ0
SIZ1
AS DS
R/W
DSACKx
D7-D0
D15-D8
BERR
HALT
BKPT FETCHED INSTRUCTION EXECUTION
BREAKPOINT OCCURS
READ
BREAKPOINT ACKNOWLEDGE INSTRUCTION WORD FETCH
Figure 3-18. Breakpoint Acknowledge Cycle Timing (Opcode Returned)
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S0 CLKOUT
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
S0
A31-A20
A19-A16
BREAKPOINT ENCODING (0000)
A4-A1
BREAKPOINT NUMBER/T-BIT
A15-A5, A0
FC3-FC0
CPU SPACE
SIZ0
SIZ1
AS DS
R/W
DSACKx
D7-D0
D15-D8
BERR
HALT
BKPT BREAKPOINT OCCURS READ BREAKPOINT ACKNOWLEDGE BUS ERROR ASSERTED
EXCEPTION STACKING
Figure 3-19. Breakpoint Acknowledge Cycle Timing (Exception Signaled)
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3.5.3 Module Base Address Register Access
All internal module registers, including the SIM41, occupy a single 4-Kbyte block that is relocatable along 4-Kbyte boundaries. The location is fixed by writing the desired base address of the SIM41 block to the module base address register using the MOVES instruction. The module base address register is only accessible in CPU space at address $0003FF00. The SFC or DFC register must indicate CPU space (FC3-FC0 = $7), using the MOVEC instruction, before accessing the module base address register. Refer to Section 4 System Integration Module for additional information on the module base address register.
3.5.4 Interrupt Acknowledge Bus Cycles
The CPU32 makes an interrupt pending in three cases. The first case occurs when a peripheral device signals the CPU32 (with IRQ7-IRQ1) that the device requires service and the internally synchronized value on these signals indicates a higher priority than the interrupt mask in the status register. The second case occurs when a transition has occurred in the case of a level 7 interrupt. A recognized level 7 interrupt must be removed for one clock cycle before a second level 7 can be recognized. The third case occurs if, upon returning from servicing a level 7 interrupt, the request level stays at 7 and the processor mask level changes from 7 to a lower level, a second level 7 is recognized. The CPU32 takes an interrupt exception for a pending interrupt within one instruction boundary (after processing any other pending exception with a higher priority). The following paragraphs describe the types of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing. 3.5.4.1 INTERRUPT ACKNOWLEDGE CYCLE--TERMINATED NORMALLY. When the CPU32 processes an interrupt exception, it performs an interrupt acknowledge cycle to obtain the number of the vector that contains the starting location of the interrupt service routine. Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use. The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices that cannot supply a vector number will use the autovector cycle described in 3.5.4.2 Autovector Interrupt Acknowledge Cycle.
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The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in 3.4.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences are as follows: 1. FC3-FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space. 2. A3, A2, and A1 are set to the interrupt request level, and the IACK strobe corresponding to the current interrupt level is asserted. (Either the function codes and address signals or the IACK strobes can be monitored to determine that an interrupt acknowledge cycle is in progress and the current interrupt level.) 3. The CPU32 space type field (A19-A16) is set to $F (interrupt acknowledge). 4. Other address signals (A31-A20, A15-A4, and A0) are set to one. 5. The SIZ0/SIZ1 and R/W signals are driven to indicate a single-byte read cycle. The responding device places the vector number on the least significant byte of its data port (for an 8-bit port, the vector number must be on D15-D8; for a 16-bit port, the vector must be on D7-D0) during the interrupt acknowledge cycle. The cycle is then terminated normally with DSACK. Figure 3-20 is a flowchart of the interrupt acknowledge cycle; Figure 3-21 shows the timing for an interrupt acknowledge cycle terminated with DSACK .
INTERRUPTING DEVICE MC68340 GRANT INTERRUPT
REQUEST INTERRUPT
PROVIDE VECTOR NUMBER 1. PLACE VECTOR NUMBER ON LEAST SIGNIFICANT BYTE OF DATA BUS 2. ASSERT DSACKx (OR AVEC IF NO VECTOR NUMBER)
1. SYNCHRONIZE IRQ7-IRQ1 2. COMPARE IRQ1-IRQ7 TO MASK LEVEL AND WAIT FOR INSTRUCTION TO COMPLETE 3. PLACE INTERRUPT LEVEL ON A3-A1; TYPE FIELD (A19-A16) = $F 4. SET R/W TO READ 5. SET FC3-FC0 TO 0111 6. DRIVE SIZE PINS TO INDICATE A ONE-BYTE TRANSFER 7. ASSERT AS AND DS 8. ASSERT THE CORRESPONDING IACKx STROBE.
ACQUIRE VECTOR NUMBER 1. LATCH VECTOR NUMBER 2. NEGATE DS AND AS
RELEASE 1. NEGATE DSACKx
START NEXT CYCLE
Figure 3-20. Interrupt Acknowledge Cycle Flowchart
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S0 CLKOUT
S2
S4
S0
0-2 CLOCKS*
S1 S2
S4
S0
S2
A31-A4
A3-A1
INTERRUPT LEVEL
A0
FC3-FC0
CPU SPACE
SIZ0
1 BYTE
SIZ1
R/W
AS
DS VECTOR FROM 16-BIT PORT DSACKx VECTOR FROM 8-BIT PORT D7-D0
D15-D8
IRQ7-IRQ1
IACK7-IACK1
READ CYCLE
INTERNAL ARBITRATION IACK CYCLE
WRITE STACK
*Internal Arbitration may take between 0-2 clock cycles.
Figure 3-21. Interrupt Acknowledge Cycle Timing 3.5.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting device cannot supply a vector number, it requests an automatically generated vector (autovector). Instead of placing a vector number on the data bus and asserting DSACK, the device asserts AVEC to terminate the cycle. If the DSACK signals are asserted during an interrupt acknowledge cycle terminated by AVEC, the DSACK signals and data
3-38 MC68341 USER'S MANUAL MOTOROLA
will be ignored if AVEC is asserted before or at the same time as the DSACK signals. The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When AVEC is asserted instead of DSACK during an interrupt acknowledge cycle, the MC68341 ignores the state of the data bus and internally generates the vector number (the sum of the interrupt level plus 24 ($18)). AVEC is multiplexed with CS0 . The FIRQ bit in the SIM41 module configuration register controls whether the AVEC /CS0 pin is used as an autovector input or as CS0 (refer to Section 4 System Integration Module for additional information). AVEC is only sampled during an interrupt acknowledge cycle. During all other cycles, AVEC is ignored. Additionally, AVEC can be internally generated for external devices by programming the autovector register. Seven distinct autovectors can be used, corresponding to the seven levels of interrupt available with signals IRQ7 -IRQ1. Figure 3-22 shows the timing for an autovector operation. 3.5.4.3 SPURIOUS INTERRUPT CYCLE. Requested interrupts, whether internal or external, are arbitrated internally. When no internal module (including the SIM41, which responds for external requests) responds during an interrupt acknowledge cycle by arbitrating for the interrupt acknowledge cycle internally, the spurious interrupt monitor generates an internal bus error signal to terminate the vector acquisition. The MC68341 automatically generates the spurious interrupt vector number (24) instead of the interrupt vector number in this case. When an external device does not respond to an interrupt acknowledge cycle with AVEC or DSACK , a bus monitor must assert BERR , which results in the CPU32 taking the spurious interrupt vector. If HALT is also asserted, the MC68341 retries the interrupt acknowledge cycle instead of using the spurious interrupt vector.
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S0 CLKOUT
S2
S4
S0
0-2 CLOCKS*
S1 S2
S4
S0
S2
A31-A4
A3-A1
INTERRUPT LEVEL
A0
FC3-FC0
CPU SPACE
SIZ0
1 BYTE
SIZ1
R/W
AS
DS
DSACKx
D15-D0
AVEC
IRQ7-IRQ1 IACK7-IACK1 CYCLE READ INTERNAL ARBITRATION IACK CYCLE * Internal Arbitration may take between 0-2 clocks. WRITE STACK
Figure 3-22 Autovector Operation Timing
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3.6 BUS EXCEPTION CONTROL CYCLES
The bus architecture requires assertion of DSACK from an external device to signal that a bus cycle is complete. Neither DSACK nor AVEC is asserted in the following cases: * DSACK /AVEC is programmed to respond internally. * The external device does not respond. * Various other application-dependent errors occur. The MC68341 provides BERR when no device responds by asserting DSACK /AVEC within an appropriate period of time after the MC68341 asserts AS. This mechanism allows the cycle to terminate and the MC68341 to enter exception processing for the error condition. HALT is also used for bus exception control. This signal can be asserted by an external device for debugging purposes to cause single bus cycle operation, or, in combination with BERR , a retry of a bus cycle in error. To properly control termination of a bus cycle for a retry or a bus error condition, DSACK, BERR , and HALT can be asserted and negated with the rising edge of the MC68341 clock. This assures that when two signals are asserted simultaneously, the required setup and hold time for both is met for the same falling edge of the MC68341 clock. This or an equivalent precaution should be designed into the external circuitry to provide these signals. Alternatively, the internal bus monitor could be used. The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to DSACK assertion as follows (case numbers refer to Table 3-4): * Normal Termination: DSACK is asserted; BERR and HALT remain negated (case 1). * Halt Termination: HALT is asserted at the same time as or before DSACKx, and BERR remains negated (case 2). * Bus Error Termination: BERR is asserted in lieu of, at the same time as, or before DSACK (case 3) or after DSACK (case 4), and HALT remains negated; BERR is negated at the same time as or after DSACK . * Retry Termination: HALT and BERR are asserted in lieu of, at the same time as, or before DSACK (case 5) or after DSACK (case 6); BERR is negated at the same time as or after DSACK , and HALT may be negated at the same time as or after BERR . Table 3-4 lists various combinations of control signal sequences and the resulting bus cycle terminations. To ensure predictable operation, BERR and HALT should be negated according to the specifications given in Section 12 Electrical Characteristics. DSACK BERR , and HALT may be negated after AS . If DSACK or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated address space. The timer asserts BERR after timeout (case 3).
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EXAMPLE B: A system uses error detection and correction on RAM contents. The designer may: 1. Delay DSACK until data is verified and assert BERR and HALT simultaneously to indicate to the MC68341 to automatically retry the error cycle (case 5), or if data is valid, assert DSACK (case 1). 2. Delay DSACK until data is verified and assert BERR with or without DSACK if data is in error (case 3). This initiates exception processing for software handling of the condition. 3. Return DSACK prior to data verification; if data is invalid, BERR is asserted on the next clock cycle (case 4). This initiates exception processing for software handling of the condition. 4. Return DSACK prior to data verification; if data is invalid, assert BERR and HALT on the next clock cycle (case 6). The memory controller can then correct the RAM prior to or during the automatic retry. Table 3-4.
DSACK, BERR , and HALT Assertion Results
Asserted on Rising Edge of State
Case Num 1
Control Signal DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT
N A NA NA A NA A/S NA/A A NA A NA NA NA/A A A/S A NA NA
N+2 S NA X S NA S X S X X A NA X S S X A A
Result Normal cycle terminate and continue.
2
Normal cycle terminate and halt; continue when HALT negated. Terminate and take bus error exception, possibly deferred. Terminate and take bus error exception, possibly deferred. Terminate and retry when HALT negated.
3
4
5
6
Terminate and retry when HALT negated.
NOTES: N-- A-- NA -- X-- S--
Number of the current even bus state (e.g., S2, S4, etc.) Signal is asserted in this bus state Signal is not asserted in this state Don't care Signal was asserted in previous state and remains asserted in this state
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3.6.1 Bus Errors
BERR can be used to abort the bus cycle and the instruction being executed. BERR takes precedence over DSACK provided it meets the timing constraints described in Section 12 Electrical Characteristics. If BERR does not meet these constraints, it may cause unpredictable operation of the MC68341. If BERR remains asserted into the next bus cycle, it may cause incorrect operation of that cycle. When BERR is issued to terminate a bus cycle, the MC68341 can enter exception processing immediately following the bus cycle, or it can defer processing the exception. The instruction prefetch mechanism requests instruction words from the bus controller before it is ready to execute them. If a bus error occurs on an instruction fetch, the MC68341 does not take the exception until it attempts to use that instruction word. Should an intervening instruction cause a branch or should a task switch occur, the bus error exception does not occur. The bus error condition is recognized during a bus cycle in any of the following cases: * DSACK and HALT are negated, and BERR is asserted. * HALT and BERR are negated, and DSACK is asserted. BERR is then asserted within one clock cycle (HALT remains negated). * BERR and HALT are asserted simultaneously, indicating a retry . When the MC68341 recognizes a bus error condition, it terminates the current bus cycle in the normal way. Figure 3-23 shows the timing of a bus error for the case in which DSACK is not asserted. Figure 3-24 shows the timing for a bus error that is asserted after DSACK . Exceptions are taken in both cases. Refer to Section 5 CPU32 for details of bus error exception processing. In the second case, in which BERR is asserted after DSACK is asserted, BERR must be asserted within the time specified for purely asynchronous operation, or it must be asserted and remain stable during the sample window around the next falling edge of the clock after DSACK is recognized. If BERR is not stable at this time, the MC68341 may exhibit erratic behavior. BERR has priority over DSACK. In this case, data may be present on the bus, but it may not be valid. This sequence can be used by systems that have memory error detection and correction logic and by external cache memories.
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S0 CLKOUT
S2
SW
SW
S4
S0
S2
S4
A31-A0
FC3-FC0
R/W
AS
DS
DSACKx BERR
DTC
D15-D0
READ CYCLE WITH BUS ERROR
INTERNAL PROCESSING
STACK WRITE
Figure 3-23. Bus Error without DSACK
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S0
CLKOUT
S2
S4
S0
S2
S4
A31-A0
FC3-FC0
R/W
AS
DS
DSACKx
BERR
DTC
D15-D0 WRITE CYCLE
INTERNAL PROCESSING
STACK WRITE
Figure 3-24. Late Bus Error with
DSACK
3.6.2 Retry Operation
When both BERR and HALT are asserted by an external device during a bus cycle, the MC68341 enters the retry sequence shown in Figure 3-25. A delayed retry, which is similar to the delayed BERR signal described previously, can also occur (see Figure 326). The MC68341 terminates the bus cycle, places the control signals in their inactive state, and does not begin another bus cycle until the BERR and HALT signals are negated by external logic. After a synchronization delay, the MC68341 retries the previous cycle using the same access information (address, function code, size, etc.). BERR should be negated before S2 of the retried cycle to ensure correct operation of the retried cycle.
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S0 CLKOUT
S2
SW
SW
S4
S0
S2
S4
A31-A0
FC3-FC0
R/W
AS
DS
DSACKx
BERR
HALT
DTC D15-D0 DATA IGNORED READ CYCLE WITH RETRY HALT READ RERUN
Figure 3-25. Retry Sequence The MC68341 retries any read or write cycle of a read-modify-write operation separately; RMC remains asserted during the entire retry sequence. Asserting BR along with BERR and HALT provides a relinquish and retry operation. The MC68341 does not relinquish the bus during a read-modify-write operation. Any device that requires the MC68341 to give up the bus and retry a bus cycle during a read-modify-write cycle must assert only BERR and BR ( HALT must not be included). The bus error handler software should examine the read-modify-write bit in the special status word (see Section 5 CPU32) and take the appropriate action to resolve this type of fault when it occurs.
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S0 CLKOUT
S2
S4
S0
S2
S4
A31-A0
FC3-FC0
R/W
AS
DS
DSACKx
BERR
HALT DTC
D15-D10 WRITE CYCLE HALT WRITE RERUN
Figure 3-26. Late Retry Sequence
3.6.3 Halt Operation
When HALT is asserted and BERR is not asserted, the MC68341 halts external bus activity at the next bus cycle boundary (see Figure 3-27). HALT by itself does not terminate a bus cycle. Negating and reasserting HALT in accordance with the correct timing requirements provides a single-step (bus cycle to bus cycle) operation. Since HALT affects external bus cycles only, a program that does not require use of the external bus may continue executing. The single-cycle mode allows the user to proceed through (and debug) external MC68341 operations, one bus cycle at a time. Since the occurrence of a bus error while HALT is asserted causes a retry operation, the user must anticipate retry cycles while debugging in the single-cycle mode. The single-step operation and the software trace capability allow the system debugger to trace single bus cycles, single instructions, or changes in program flow. When the MC68341 completes a bus cycle with HALT asserted, D15-D0 is placed in the high-impedance state, and bus control signals are negated (not high-impedance state); the A31-A0, FCx, SIZx, and R/W signals remain in the same state. The halt operation has no effect on bus arbitration (see 3.7 Bus Arbitration). When bus arbitration occurs while the MC68341 is halted, the address and control signals are also placed in the highimpedance state. Once bus mastership is returned to the MC68341, if HALT is still
MOTOROLA MC68341 USER'S MANUAL 3-47
asserted, the A31-A0, FCx, SIZx, and R/W signals are again driven to their previous states. The MC68341 does not service interrupt requests while it is halted.
S0 CLKOUT
S2
S4
S0
S2
S4
S0
A31-A0
FC3-FC0
R/W
AS
DS
DSACKx
D15-D10
HALT
BR
BG
BGACK READ HALT (ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) READ
Figure 3-27.
HALT Timing
3.6.4 Double Bus Fault
A double bus fault results when a bus error or an address error occurs during the exception processing sequence for any of the following: * A previous bus error * A previous address error * A reset For example, the MC68341 attempts to stack several words containing information about the state of the machine while processing a bus error exception. If a bus error exception
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occurs during the stacking operation, the second error is considered a double bus fault. When a double bus fault occurs, the MC68341 halts and asserts HALT. Only a reset operation can restart a halted MC68341. However, bus arbitration can still occur (see 3.7 Bus Arbitration). A second bus error or address error that occurs after exception processing has completed (during the execution of the exception handler routine or later) does not cause a double bus fault. A bus cycle that is retried does not constitute a bus error or contribute to a double bus fault. The MC68341 continues to retry the same bus cycle as long as the external hardware requests it. Reset can also be generated internally by the halt monitor (see Section 5 CPU32).
3.7 BUS ARBITRATION
The bus design of the MC68341 provides for a single bus master at any one time, either the MC68341 or an external device. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus, but not the MC68341 internal bus. Bus arbitration is the protocol by which an external device becomes bus master; the bus controller in the MC68341 manages the bus arbitration signals so that the MC68341 has the lowest priority. External devices that need to obtain the bus must assert the bus arbitration signals in the sequences described in the following paragraphs. Systems having several devices that can become bus master require external circuitry to assign priorities to the devices so that, when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes bus master first. The sequence of the protocol is as follows: 1. An external device asserts BR. 2. The MC68341 asserts BG to indicate that the bus is available. 3. The external device asserts BGACK to indicate that it has assumed bus mastership. NOTE The MC68341 does not place CS3-CS0 in a high-impedance state after reset or when the bus is granted to an external master. BR may be issued any time during a bus cycle or between cycles. BG is asserted in response to BR. To guarantee operand coherency, BG is only asserted at the end of an operand transfer. Additionally, BG is not asserted until the end of a read-modify-write operation (when RMC is negated) in response to a BR signal. When the requesting device receives BG and more than one external device can be bus master, the requesting device should begin whatever arbitration is required. When the external device assumes bus mastership, it asserts BGACK and maintains BGACK during the entire bus cycle (or cycles) for which it is bus master. The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure: 1) it must have received BG through the arbitration process, and 2) BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus.
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Figure 3-28 is a flowchart showing bus arbitration for a single device. This technique allows processing of bus requests during data transfer cycles. Refer to Figures 3-29 and 3-30 for bus arbitration timing diagrams. BR is negated at the time that BGACK is asserted. This type of operation applies to a system consisting of the MC68341 and one device capable of bus mastership. In a system having a number of devices capable of bus mastership, BR from each device can be wireORed to the MC68341. In such a system, more than one bus request could be asserted simultaneously. BG is negated a few clock cycles after the transition of BGACK. However, if bus requests are still pending after the negation of BG , the MC68341 asserts another BG within a few clock cycles after it was negated. This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished using the bus. The following paragraphs provide additional information about the three steps in the arbitration process. Bus arbitration requests are recognized during normal processing, HALT assertion, and a CPU32 halt caused by a double bus fault.
PROCESSOR REQUESTING DEVICE REQUEST THE BUS GRANT BUS ARBITRATION 1. ASSERT BG ACKNOWLEDGE BUS MASTERSHIP 1. EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2. NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3. NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER 4. BUS MASTER NEGATES BR 1. ASSERT BR
TERMINATE ARBITRATION 1. NEGATE BG (AND WAIT FOR BGACK TO BE NEGATED)
OPERATE AS BUS MASTER 1. PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PROCESSOR USES
RELEASE BUS MASTERSHIP RE-ARBITRATE OR RESUME PROCESSOR OPERATION 1. NEGATE BGACK
Figure 3-28. Bus Arbitration Flowchart for Single Request
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CLKOUT
A31-A0
D15-D0
AS
BR
BG
BGACK
Figure 3-29. Bus Arbitration Timing Diagram--Idle Bus Case
S0 CLKOUT
S1
S2
S3
S4
S5
A31-A0
D15-D0
AS
DS
R/W
DSACK0, DSACK1 BR
BG
BGACK
Figure 3-30. Bus Arbitration Timing Diagram--Active Bus Case
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3.7.1 Bus Request
External devices capable of becoming bus masters request the bus by asserting BR. This signal can be wire-ORed to indicate to the MC68341 that some external device requires control of the bus. The MC68341 is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started). If no BGACK is received while the BR is active, the MC68341 remains bus master once BR is negated. This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise or if an external device determines that it no longer requires use of the bus before it has been granted mastership.
3.7.2 Bus Grant
The MC68341 supports operand coherency; thus, if an operand transfer requires multiple bus cycles, the MC68341 does not release the bus until the entire transfer is complete. Therefore, assertion of BG is subject to the following constraints: * The minimum time for BG assertion after BR is asserted depends on internal synchronization (see Section 12 Electrical Characteristics). * During an external operand transfer, the MC68341 does not assert BG until after the last cycle of the transfer (determined by SIZx and DSACK). * During an external operand transfer, the MC68341 does not assert BG as long as RMC is asserted. * If the show cycle bits SHEN1-SHEN0 = 01, the MC68341 does not assert BG to an external master. Externally, the BG signal can be routed through a daisy-chained network or a priorityencoded network. The MC68341 is not affected by the method of arbitration as long as the protocol is obeyed.
3.7.3 Bus Grant Acknowledge
An external device cannot request and be granted the external bus while another device is the active bus master. A device that asserts BGACK remains the bus master until it negates BGACK . BGACK should not be negated until all required bus cycles are completed. Bus mastership is terminated at the negation of BGACK. Once an external device receives the bus and asserts BGACK , it should negate BR. If BR remains asserted after BGACK is asserted, the MC68341 assumes that another device is requesting the bus and prepares to issue another BG .
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3.7.4 Bus Arbitration Control
The bus arbitration control unit in the MC68341 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68341 are internally synchronized in a maximum of two cycles of the clock. As shown in Figure 3-31 input signals labeled R and A are internally synchronized versions of BR and BGACK respectively. The BG output is labeled G, and the internal high-impedance control signal is labeled T. If T is true, the address, data, and control buses are placed in the highimpedance state after the next rising edge following the negation of AS and RMC. All signals are shown in positive logic (active high) regardless of their true active voltage level. The state machine shown in Figure 3-31 does not have a state 1 or state 4. State changes occur on the next rising edge of the clock after the internal signal is valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The bus control signals (controlled by T) are driven by the MC68341 immediately following a state change, when bus mastership is returned to the MC68341. State 0, in which G and T are both negated, is the state of the bus arbiter while the MC68341 is bus master. R and A keep the arbiter in state 0 as long as they are both negated. The MC68341 does not allow arbitration of the external bus during the RMC sequence. For the duration of this sequence, the MC68341 ignores the BR input. If mastership of the bus is required during an RMC operation, BERR must be used to abort the RMC sequence.
3.7.5 Show Cycles
The MC68341 can perform data transfers with its internal modules without using the external bus, but, when debugging, it is desirable to have address and data information appear on the external bus. These external bus cycles, called show cycles, are distinguished by the fact that AS is not asserted externally. DS is used to signal address strobe timing in show cycles. After reset, show cycles are disabled and must be enabled by writing to the SHEN bits in the module configuration register (see 4.3.2.1 Module Configuration Register (MCR)). When show cycles are disabled, the A31-A0, FCx, SIZx, and R/W signals continue to reflect internal bus activity. However, AS and DS are not asserted externally, and the external data bus remains in a high-impedance state. When show cycles are enabled, DS indicates address strobe timing and the external data bus contains data. The following paragraphs are a state-by-state description of show cycles, and Figure 3-32 illustrates a show cycle timing diagram. Refer to Section 12 Electrical Characteristics for specific timing information.
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RA + B
GTV AB STATE 0 RA
RAB RA
RA
G TV STATE 3
R+A G TV STATE 2 R A +A
G TV R STATE 5 R
RA RA G TV STATE 6
RA
R - BUS REQUEST A - BUS GRANT ACKNOWLEDGE B - BUS CYCLE IN PROGRESS
G - BUS GRANT T - THREE-STATE SIGNAL TO BUS CONTROL V - BUS AVAILABLE TO BUS CONTROL
Figure 3-31. Bus Arbitration State Diagram
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State 0--During state 0, the A31-A0 and FCx become valid, R/W is driven to indicate a show read or write cycle, and the SIZx pins indicate the number of bytes to transfer. During a read, the addressed peripheral is driving the data bus, and the user must take care to avoid bus conflicts. State 41--One-half clock cycle later, DS (rather than A S) is asserted to indicate that address information is valid. State 42--No action occurs in state 42. The bus controller remains in state 42 (wait states will be inserted) until the internal read cycle is complete. State 43--When DS is negated, show data is valid on the next falling edge of the system clock. The external data bus drivers are enabled so that data becomes valid on the external bus as soon as it is available on the internal bus. State 0--The A31-A0, FCx, R/W , and SIZx pins change to begin the next cycle. Data from the preceding cycle is valid through state 0.
S0 CLKOUT A31-A0, FC2-FC0, SIZ1-SIZ0 R/W S41 S42 S43 S0 S1 S2
AS, CS
DS
D15-D0
BKPT SHOW CYCLE START OF EXTERNAL CYCLE
Figure 3-32. Show Cycle Timing Diagram
3.8 RESET OPERATION
The MC68341 has reset control logic to determine the cause of reset, synchronize it if necessary, and assert the appropriate reset lines. The reset control logic can independently drive three different lines: 1. EXTRST (external reset) drives the external RESET pin. 2. CLKRST (clock reset) resets the clock module. 3. INTRST (internal reset) goes to all other internal circuits.
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Synchronous reset sources are not asserted until the end of the current bus cycle, whether or not RMC is asserted. The internal bus monitor is automatically enabled for synchronous resets; therefore, if the current bus cycle does not terminate normally, the bus monitor terminates it. Only single-byte or word transfers are guaranteed valid for synchronous resets. An external or clock reset is a synchronous reset source. Asynchronous reset sources indicate a catastrophic failure, and the reset controller logic immediately resets the system. Resetting the MC68341 causes any bus cycle in progress to terminate as if DSACK or B E R R had been asserted. In addition, the MC68341 appropriately initializes registers for a reset exception. Asynchronous reset sources include power-up, software watchdog, double bus fault resets, and execution of the RESET instruction. If an external device drives RESET low, RESET should be asserted for at least 590 clock periods to ensure that the MC68341 resets. The reset control logic holds reset asserted internally until the external RESET is released. When the reset control logic detects that external RESET is no longer being driven, it drives both internal and external reset low for an additional 512 cycles to guarantee this length of reset to the entire system. Figure 3-33 shows the RESET timing.
1 CLOCK
RESET 590 CLOCK 512 CLOCK
PULLED EXTERNAL
DRIVEN BY MC68340
Figure 3-33. Timing for External Devices Driving
RESET
If reset is asserted from any other source, the reset control logic asserts RESET for 328 input clock periods plus 512 output clock periods, and until the source of reset is negated. After any internal reset occurs, a 14-cycle rise time is allowed before testing for the presence of an external reset. If no external reset is detected, the CPU32 begins its vector fetch. Figure 3-34 is a timing diagram of the power-up reset operation, showing the relationships between RESET, V CC , and bus signals. During the reset period, the entire bus threestates except for non-three-statable signals, which are driven to their inactive state. Once RESET negates, all control signals are driven to their inactive state, the data bus is in read mode, and the address bus is driven. After this, the first bus cycle for RESET exception processing begins.
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CLKOUT
VCO LOCK VCC RESET
328 x TCLKIN
512 x TCLKOUT
14 CLOCKS
BUS CYCLES BUS STATE UNKNOWN NOTES: 1. Internal start-up time. 2. SSP read here. 3. PC read here. 4. First instruction fetched here.
ADDRESS AND CONTROL SIGNALS THREE-STATED
1
2
3
4
Figure 3-34. Power-Up Reset Timing Diagram When a RESET instruction is executed, the MC68341 drives the RESET signal for 512 clock cycles. The SIM41 registers and the module control registers in each internal peripheral module (DMA, timers, and serial modules) are not affected. All other peripheral module registers are reset the same as for a hardware reset. The external devices connected to the RESET signal are reset at the completion of the RESET instruction.
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SECTION 4 SYSTEM INTEGRATION MODULE
The MC68341 system integration module (SIM41) consists of several functions that control the system start-up, initialization, configuration, and the external bus with a minimum of external devices. It also provides the IEEE 1149.1 boundary scan capabilities. The SIM41 includes the following functions: * System Configuration and Protection * Clock Synthesizer * Real-Time Clock * Chip Selects and Wait States * 68300/68000 External Bus Interface * Bus Arbitration * Dynamic Bus Sizing * IEEE 1149.1 Test Access Port
4.1 MODULE OVERVIEW
The SIM41 has similar features to the SIM in the MC68330 and MC68340. The periodic interrupt timer, double bus fault monitor, software watchdog, and spurious interrupt monitor are identical. However, many of the other features in the SIM differ in their use and details. The system configuration and protection function controls system configuration and provides various monitors and timers, including the internal bus monitor, double bus fault monitor, spurious interrupt monitor, software watchdog timer, and the periodic interrupt timer. The clock synthesizer generates the clock signals used by the SIM41 and the other onchip modules, as well as CLKOUT used by external devices. The real-time clock function has internal interrupt generation capability, and a programmable output pin that can provide an interrupt on an alarm or time-matching function. The programmable chip select function provides eight chip select signals that can enable external memory and peripheral circuits, providing all handshaking and timing signals. Each chip select signal has an associated base address register and an address mask register that contain the programmable characteristics of that chip select. Up to six wait
MOTOROLA MC68341 USER'S MANUAL 4-1
states can be programmed by setting bits in the address mask register and base address register. The 68300/68000 external bus interface (EBI) handles the transfer of information between the internal CPU32 and memory, peripherals, or other processing elements in the external address space. See Section 3 Bus Operation for further information. The MC68341 dynamically interprets the port size of an addressed device during each bus cycle in 68300 bus mode, allowing operand transfers to or from 8-, 16-, and 32-bit ports. The device signals its port size and indicates completion of the bus cycle through the use of the DSACK inputs. Dynamic bus sizing allows a programmer to write code that is not bus-width specific. For a discussion on dynamic bus sizing, see Section 3 Bus Operation. The MC68341 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to the development of this standard under the sponsorship of the IEEE Test Technology Committee and Joint Test Action Group (JTAG). The MC68341 implementation supports circuit-board test strategies based on this standard. Refer to Section 10 IEEE 1149.1 Test Access Port for additional information.
4.2 MODULE OPERATION
The following paragraphs describe the operation of the module base address register, system configuration and protection, clock synthesizer, chip select functions, and the external bus interface. NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false.
4.2.1 Module Base Address Register Operation
The module base address register (MBAR) controls the location of all internal module registers (see 4.3.1 Module Base Address Register (MBAR)). The address stored in this register is the base address (starting location) for all internal registers. All internal module registers are contained in a single 4-Kbyte block (see Figure 4-1) that is relocatable along 4-Kbyte boundaries. The location of the internal registers is fixed by writing the desired base address of the 4-Kbyte block to the MBAR using the MOVES instruction to address $0003FF00 in CPU space. The source function code (SFC) and destination function code (DFC) registers contain the address space values (FC3-FC0) for the read or write operand of the MOVES
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instruction (see Section 5 CPU32 or M68000PM/AD, Programmer's Reference Manual). Therefore, the SFC or DFC register must indicate CPU space (FC3-FC0 = $7), using the MOVEC instruction, before accessing MBAR. The offset from the base address is shown above each register diagram.
$FFFFFFFF
$XXXXXFFF MC68341 RELOCATABLE MODULE BLOCK QSPM $XXXXX000 DMA
$FFF $94F $800 $7BF $780 $721 SERIAL $700 $63F TIMER $600
MBAR ($0003FF00 FC=0111) RAM (TYPICAL) $00000000 NOTE: $XXXXX is the value contained in the MBAR bits BA31-BA12.
$0CF SIM 41 $000
Figure 4-1. SIM41 Module Register Block
4.2.2 System Configuration and Protection Operation
The SIM41 allows the user to control certain features of system configuration by writing bits in the module configuration register (MCR). This register also contains read-only status bits that show the state of the SIM41. All M68000 family members are designed to provide maximum system safeguards. As an extension of the family, the MC68341 promotes the same basic concepts of safeguarded design present in all M68000 members. In addition, many functions that normally must be provided by external circuits are incorporated in this device. The following features are provided in the system configuration and protection function: SIM41 Module Configuration The SIM41 allows the user to configure the system to the particular requirements. The functions include control of FREEZE and show cycle operation, the function of the CS signals, the access privilege of the supervisor/user registers, the level of interrupt arbitration, and automatic vectoring for external interrupts.
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Reset Status The reset status register provides the user with information on the cause of the most recent reset. The possible causes of reset include: external, power-up, software watchdog, double bus fault, loss of clock, and RESET instruction. Internal Bus Monitor The SIM41 provides an internal bus monitor to monitor the DSACK response time for all internal bus accesses. An option allows the monitoring of external bus accesses. For external bus accesses, four selectable response times are provided to allow for variations in response speed of memory and peripherals used in the system. A bus error signal is asserted internally if the DSACK response limit is exceeded. BERR is not asserted externally. This monitor can be disabled for external bus cycles only. Double Bus Fault Monitor The double bus fault monitor causes a reset to occur if the internal HALT is asserted by the CPU32, indicating a double bus fault. A double bus fault results when a bus or address error occurs during the exception processing sequence for a previous bus or address error, a reset, or while the CPU32 is loading information from a bus error stack frame during an RTE instruction. This function can be disabled. See Section 3 Bus Operation for more information. Spurious Interrupt Monitor If no interrupt arbitration occurs during an interrupt acknowledge (IACK) cycle, the bus error signal is asserted internally. This function cannot be disabled. Software Watchdog The software watchdog asserts reset or a level 7 interrupt (as selected by the system protection and control register) if the software fails to service the software watchdog for a designated period of time (i.e., because it is trapped in a loop or lost). There are eight selectable timeout periods. This function can be disabled. Periodic Interrupt Timer The SIM41 provides a timer to generate periodic interrupts. The periodic interrupt time period can vary from 122 s to 15.94 s (with a 32.768-kHz crystal used to generate the system clock). This function can be disabled. Figure 4-2 shows a block diagram of the system configuration and protection function.
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MODULE CONFIGURATION
RESET STATUS
DOUBLE BUS FAULT MONITOR
HALT RESET REQUEST
BUS MONITOR
BERR
SPURIOUS INTERRUPT MONITOR
CLOCK 29 PRESCALER
SOFTWARE WATCHDOG
SOFTWARE RESET REQUEST or IRQ7
PERIODIC INTERRUPT TIMER
IRQ7-IRQ1
Figure 4-2. System Configuration and Protection Function 4.2.2.1 SYSTEM CONFIGURATION. Aspects of the system configuration are controlled by the MCR and the autovector register (AVR). The configuration of port B is controlled by the combination of the AVEC bit in the MCR and the port B pin assignment register (PPARB). Port B pins can function as dedicated I/O lines or interrupts. For debug purposes, internal bus accesses can be shown on the external bus. This function is called show cycles. The SHEN1, SHEN0 bits in the MCR control show cycles. Bus arbitration can be either enabled or disabled during show cycles. Arbitration for servicing interrupts is controlled by the value programmed into the interrupt arbitration (IARB) field of the MCR. Each module that generates interrupts, including the SIM41, has an IARB field. The value of the IARB field allows arbitration during an IACK cycle among modules that simultaneously generate the same interrupt level. No two modules should share the same IARB value. The IARB must contain a value other than $0 for all modules that can generate interrupts; interrupts with IARB = 0 are discarded as extraneous. The SIM41 arbitrates for both its own interrupts and externally generated interrupts.
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There are eight arbitration levels for access to the intermodule bus (IMB). The SIM41 is fixed at the highest level (above the programmable level 7), and the CPU32 is fixed at the lowest level (below level 0). The direct memory access (DMA) module is the only other module that can become bus master and arbitrate for the bus. It must be initialized with a level other than 0 or 7. The AVR contains bits that correspond to external interrupt levels that require an autovector response. The SIM41 supports up to seven discrete external interrupt requests. If the bit corresponding to an interrupt level is set in the AVR, the SIM41 returns an autovector in response to the IACK cycle servicing that external interrupt request. Otherwise, external circuitry must either return an interrupt vector or assert the external AVEC signal. 4.2.2.2 INTERNAL BUS MONITOR. The internal bus monitor continually checks for the bus cycle termination response time by checking the DSACK , BERR , and HALT status or the AVEC status during an IACK cycle. The monitor initiates a bus error if the response time is excessive. The bus monitor feature cannot be disabled for internal accesses to an internal module. The internal bus monitor cannot check the DSACK response on the external bus unless the MC68341 is the bus master. The BME bit in the system protection control register (SYPCR) enables the internal bus monitor for internal-to-external bus cycles. If the system contains external bus masters whose bus cycles must be monitored, an external bus monitor must be implemented. In this case, the internal-to-external bus monitor option must be disabled. The bus cycle termination response time is measured in clock cycles, and the maximumallowable response time is programmable. The bus monitor response time period ranges from 64 to 512 system clocks (see Table 4-9). These options are provided to allow for different response times of peripherals that might be used in the system. 4.2.2.3 DOUBLE BUS FAULT MONITOR. A double bus fault is caused by a bus error or address error during the exception processing sequence. The double bus fault monitor responds to an assertion of HALT on the internal bus. Refer to Section 3 Bus Operation for more information. The DBF bit in the reset status register (RSR) indicates that the last reset was caused by the double bus fault monitor. The double bus fault monitor reset can be enabled by the DBFE bit in the SYPCR. 4.2.2.4 SPURIOUS INTERRUPT MONITOR. The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an IACK cycle. Normally, during an IACK cycle, one or more internal modules recognize that the CPU32 is responding to interrupt request(s) and arbitrate for the privilege of returning a vector or asserting AVEC. (The SIM41 reports and arbitrates for externally generated interrupts.) This feature cannot be disabled. 4.2.2.5 SOFTWARE WATCHDOG. The SIM41 provides a software watchdog option to prevent system lock-up in case the software becomes trapped in loops with no controlled exit. Once enabled by the SWE bit in the SYPCR, the software watchdog requires a special service sequence to be executed on a periodic basis. If this periodic servicing action does not occur, the software watchdog times out and issues a reset or a level 7
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interrupt (as programmed by the SWRI bit in the SYPCR). The address of the interrupt service routine for the software watchdog interrupt is stored in the software interrupt vector register (SWIV). Figure 4-3 shows a block diagram of the software watchdog as well as the clock control circuits for the periodic interrupt timer. The watchdog clock rate is determined by the SWP bit in the periodic interrupt timer register (PITR) and the SWT bits in the SYPCR. See Table 4-8 for a list of watchdog timeout periods. The software watchdog service sequence consists of the following steps: 1) write $55 to the software service register (SWSR) and 2) write $AA to the SWSR. Both writes must occur in the order listed prior to the watchdog timeout, but any number of instructions or accesses to the SWSR can be executed between the two writes.
PITR SWP PTP FREEZE CLOCK MUX PRECLK RESET SWCLK 15 STAGE DIVIDER CHAIN (215 ) PITCLK . .4 MODULUS COUNTER PIT INTERRUPT
EXTAL EXTCLK MODCK LPSTOP
CLOCK DISABLE
PRESCALER (2 9 )
29
2 11
213
215
Figure 4-3. Software Watchdog Block Diagram 4.2.2.6 PERIODIC INTERRUPT TIMER. The periodic interrupt timer consists of an 8-bit modulus counter that is loaded with the value contained in the PITR (see Figure 4-3). The modulus counter is clocked by a signal derived from the EXTAL input pin unless an external frequency source from the EXTCLK pin is used. When an external frequency source is used (MODCK low during reset), the default state of the prescaler control bits (SWP and PTP) in the PITR should be changed to enable both prescalers. Either clock source (EXTAL or EXTCLK or either divided by 512) is divided by 4 before driving the modulus counter (PITCLK). When the modulus counter value reaches zero, an interrupt is generated. The level of the generated interrupt is programmed into the PIRQL bits in the periodic interrupt control register (PICR). During the IACK cycle, the SIM41 places the periodic interrupt vector, programmed into the PIV bits in the PICR, onto the internal bus. The value of bits 7-0 in the PITR is then loaded again into the modulus counter, and the counting process starts over. If a new value is written to the PITR, this value is loaded into the modulus counter when the current count is completed.
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4.2.2.6.1 Periodic Timer Period Calculation. The period of the periodic timer can be calculated using the following equation: PITR count value EXTAL (or EXTCLK) frequency/prescaler value 22
periodic interrupt timer period
=
Solving the equation using a crystal frequency of 32.768-kHz with the prescaler disabled gives: PITR count value 32768/1 22 PITR count value 8192
periodic interrupt timer period
=
periodic interrupt timer period
=
This gives a range from 122 s, with a PITR value of $01 (00000001 binary), to 31.128 ms, with a PITR value of $FF (11111111 binary). Solving the equation with the prescaler enabled (PTP=1 in the PITR) gives the following values: PITR count value 32768/512 22 PITR count value 16
periodic interrupt timer period
=
periodic interrupt timer period
=
This gives a range from 62.5 ms, with a PITR value of $01, to 15.94 s, with a PITR value of $FF. For fast calculation of periodic timer period using a 32.768-kHz crystal, the following equations can be used: With prescaler disabled: programmable interrupt timer period With prescaler enabled: programmable interrupt timer period = PITR (62.5 ms) = PITR (122 s)
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4.2.2.6.2 Using the Periodic Timer as a Real-Time Clock. The periodic interrupt timer can be used as a real-time clock interrupt by setting it up to generate an interrupt with a one-second period. Rearranging the periodic timer period equation to solve for the desired count value: PITR count value = (PIT period) (EXTAL (or EXTCLK) frequency) (Prescaler value) (2 2) (1) (32768) (512) (2 2) 16 (decimal)
PITR count value
=
PITR count value
=
Therefore, when using a 32.768-kHz crystal, the PITR should be loaded with a value of $10 with the prescaler enabled to generate interrupts at a one-second rate. 4.2.2.7 SIMULTANEOUS INTERRUPTS BY SOURCES IN THE SIM41. If multiple interrupt sources at the same interrupt level are simultaneously asserted in the SIM41, it will prioritize and service the interrupts in the following order: 1) software watchdog, 2) periodic interrupt timer, 3) RTC alarm, and 4) external interrupts.
4.2.3 Clock Synthesizer Operation
The clock synthesizer can operate with either an external crystal or an external oscillator for reference, using the internal phase-locked loop (PLL) and voltage-controlled oscillator (VCO), or an external clock can directly drive the external clock input (EXTCLK) at the operating frequency. For RTC operation, 32.768 kHz crystal operation must be used. The four modes of clock operation are listed in Table 4-1. Table 4-1. Clock Operating Modes
Mode Description External crystal used with the on-chip PLL and VCO to generate a system clock and CLKOUT of programmable rates. The desired operating frequency is driven into EXTCLK resulting in a system clock and CLKOUT of the same frequency, not tightly coupled. The desired operating frequency is driven into EXTCLK, resulting in a system clock and CLKOUT of the same frequency, with a tight skew between input and output signals. Upon input signal loss for either clock mode using the PLL, operation continues at approximately one-half operating speed (affected by the value of the X-bit in the SYNCR). MODCK VCCSYN Reset Operating Value Value 1 0 VCC 0V
Crystal Mode External Clock Mode without PLL
External Clock Mode with PLL
0
VCC
Limp Mode
X
VCC
4.2.3.1 CRYSTAL MODE. In crystal mode (see Figure 4-4), the clock synthesizer can operate from the on-chip PLL and VCO, using a parallel resonant crystal connected between the EXTAL and XTAL pins. An external oscillator can also be connected to EXTCLK as a reference frequency source, as shown in Figure 4-5. A 32.768-kHz watch crystal provides an inexpensive reference, but the reference crystal or external oscillator
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frequency can be any frequency in the range specified in Section 12 Electrical Characteristics. When using crystal mode, the system clock frequency is programmable (using the W, X, Y, and Z bits in the SYNCR) over the range specified in Section 12 Electrical Characteristics (see Table 4-2.).
32.768 kHz VCCSYN XFC1 0.1 F MODCK XFC SEL VCO CLKOUT PHASE COMPARE LOW-PASS FILTER /2 /2 1 /2 0 SEL MUX MUX 1 MODULUS DIVIDER SEL 6 V FEEDBACK DIVIDER 0 /4 /8 X Z MUX 1 0 SEL /8 MUX 1 0 SEL V CCSYN 0.01 F 0.1 F
10 M EXTAL CRYSTAL OSCILLATOR XTAL
330 K
20 pF
10 pF
1 0
MUX EXTCLK
Y
W
1: Must be low-leakage capacitor.
Figure 4-4. Clock Block Diagram for Crystal and EXTCLK Operation
60 k
EXTAL
XTAL
60 k
.
Figure 4-5. MC68341 Crystal Oscillator A separate power pin (VCCSYN ) is used to provide increased noise immunity for the clock circuits. The oscillator Crystal Oscillators always powered if any power is present. If VCCSYN is at V CC it is used. If V CCSYN is at 0V, V CC is used. If BSW is asserted, V BAT is used. The source for VCCSYN should be a quiet power supply with adequate external bypass capacitors placed as close as possible to the V CCSYN pin to ensure a stable operating frequency. Figure 4-4 shows typical values for the bypass and PLL external
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capacitors. The crystal manufacturer's documentation should be consulted for specific recommendations for external components. 4.2.3.2 EXTERNAL CLOCK MODE. To use an external clock source (see Figure 4-6), the operating clock frequency can be driven directly into the EXTCLK pin. The V-bit in the SYNCR allows running the VCO at either the same speed or half the speed of the external clock. This approach results in a system clock and CLKOUT that are the same as the input signal frequency, but not tightly coupled to it. The external clock frequency can optionally be divided by two using the V-bit in SYNCR. To enable this mode, MODCK must be held low during reset, and VCCSYN held at 0 V while the chip is in operation.
VCCSYN EXTERNAL CLOCK XFC 1 0.1 F
EXTAL
XTAL
XFC PIN
VCCSYN
.01 F
CRYSTAL OSCILLATOR 1 MUX 0
1 MUX 0
PHASE COMPARATOR
LOW-PASS FILTER
VCO
EXTCLK
/2
MODCK
V FEEDBACK DIVIDER
CLOCK CONTROL SYSTEM CLOCK NOTES: 1. Must be low-leakage capacitor. CLKOUT
Figure 4-6. Block Diagram for External Clock Operation Alternatively, an external clock signal can be directly driven into EXTCLK using the onchip PLL. To enable this mode, MODCK must be held low during reset, and V CCSYN should be connected to a quiet V CC source. (See Table 4-1). In external clock mode, the V, W, X, Y, and Z bits in the SYNCR can program the system frequency over the range specified in Section 12 Electrical Characteristics. 4.2.3.3 LIMP MODE. If an input signal loss for either of the clock modes using the PLL occurs, chip operation can continue in limp mode with the VCO running at approximately one-half the operating speed (affected by the value of the X-bit in the SYNCR), using an internal voltage reference. The SLIMP bit in the SYNCR indicates that a loss of input
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signal reference has been detected. The RSTEN bit in the SYNCR controls whether an input signal loss causes a system reset or causes the device to operate in limp mode. The SLOCK bit in the SYNCR indicates when the VCO has locked onto the desired frequency or if an external clock is being used. 4.2.3.1 PHASE COMPARATOR AND FILTER. The phase comparator takes the output of the frequency divider and compares it to an external input signal reference. The result of this compare is low-pass filtered and used to control the VCO. The comparator also detects when the external crystal or oscillator stops running to initiate the limp mode for the system clock. The PLL requires an external low-leakage filter capacitor, typically in the range from 0.01 to 0.1 F, connected between the XFC and VCCSYN pins. The XFC capacitor should provide 50-M insulation but should not be electrolytic. Smaller values of the external filter capacitor provide a faster response time for the PLL, and larger values provide greater frequency stability. For external clock mode without PLL, the XFC pin can be left open. 4.2.3.2 FREQUENCY DIVIDER. The frequency divider circuits divide the VCO frequency down to the reference frequency for the phase comparator. The frequency divider consists of 1) a 2-bit prescaler controlled by the W-bit in the SYNCR and 2) a 6-bit modulo downcounter controlled by the Y-bits in the SYNCR. The frequency of CLKOUT can additionally be divided by 2 with the X-bit in SYNCR and divided by 8 with the Z-bit in SYNCR. Several factors are important to the design of the system clock. The resulting system clock frequency must be within the limits specified for the device. The frequency of the system clock is given by the following two equations: FSYSTEM = FCRYSTAL [2(2W+X+3Z-1)] X (Y+1) The maximum VCO frequency limit must also be observed. The VCO frequency is given by the following equation: FVCO = FCRYSTAL[(2) (4+2W)] X (Y+1) = F SYSTEM[2(5-X-3Z) ] The VCO upper frequency limit must be considered when programming the SYNCR. Both the system clock and VCO frequency limits are given in Section 12 Electrical Characteristics. Table 4-2 lists some frequencies available from various combinations of SYNCR bits with a reference frequency of 32.768-KHz.
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Table 4-2. System Frequencies from 32.768-kHz Reference
CLKOUT(kHz) 1 W = 02 Z=0 Y2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 X=0 16 33 49 66 82 98 115 131 147 164 180 197 213 229 246 262 279 295 311 328 344 360 377 393 410 426 442 459 475 492 508 524 X=1 33 66 98 131 164 197 229 262 295 328 360 393 426 459 492 524 557 590 623 655 688 721 754 786 819 852 885 918 950 983 1016 1049 Z=1 X=0 131 262 393 524 655 786 918 1049 1180 1311 1442 1573 1704 1835 1966 2097 2228 2359 2490 2621 2753 2884 3015 3146 3277 3408 3539 3670 3801 3932 4063 4194 X=1 262 524 786 1049 1311 1573 1835 2097 2359 2621 2884 3146 3408 3670 3932 4194 4456 4719 4981 5243 5505 5767 6029 6291 6554 6816 7078 7340 7602 7864 8126 8389 VCO (kHz) 1 W = 02 Z=x X=x 524 1049 1573 2097 2621 3146 3670 4194 4719 5243 5767 6291 6816 7340 7864 8389 8913 9437 9961 10486 11010 11534 12059 12583 13107 13631 14156 14680 15204 15729 16253 16777 Z=0 X=0 66 131 197 262 328 393 459 524 590 655 721 786 852 918 983 1049 1114 1180 1245 1311 1376 1442 1507 1573 1638 1704 1769 1835 1901 1966 2032 2097 X=1 1049 2097 3146 4194 5243 6291 7340 8389 9437 10486 11534 12583 13631 14680 15729 16777 17826 18874 19923 20972 22020 23069 24117 25166 26214 27263 28312 29360 30409 31457 32506 33554 CLKOUT (kHz) 1 W = 12 Z=1 X=0 524 1049 1573 2097 2621 3146 3670 4194 4719 5243 5767 6291 6816 7340 7864 8389 8913 9437 9961 10486 11010 11534 12059 12583 13107 13631 14156 14680 15204 15729 16253 16777 X=1 1049 2097 3146 4194 5243 6291 7340 8389 9437 10486 11534 12583 13631 14680 15729 16777 17826 18874 19923 20972 22020 23069 24117 25166 26214 27263 28312 29360 30409 31457 32506 33554 VCO (kHz) 1 W = 12 Z=x X=x 2097 4194 6291 8389 10486 12583 14680 16777 18874 20972 23069 25166 27263 29360 31457 33554 35652 37749 39846 41943 44040 46137 48234 50332 52429 54526 56623 58720 60817 62915 65012 67109
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Table 4-2. System Frequencies from 32.768-kHz Reference (Continued)
CLKOUT (kHz) W=0 Z=0 Y 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 X=0 541 557 573 590 606 623 639 655 672 688 705 721 737 754 770 786 803 819 836 852 868 885 901 918 934 950 967 983 999 1016 1032 1049 X=1 1081 1114 1147 1180 1212 1245 1278 1311 1343 1376 1409 1442 1475 1507 1540 1573 1606 1638 1671 1704 1737 1769 1802 1835 1868 1901 1933 1966 1999 2032 2064 2097 Z=1 X=0 4325 4456 4588 4719 4850 4981 5112 5243 5374 5505 5636 5767 5898 6029 6160 6291 6423 6554 6685 6816 6947 7078 7209 7340 7471 7602 7733 7864 7995 8126 8258 8389 X=1 8651 8913 9175 9437 9699 9961 10224 10486 10748 11010 11272 11534 11796 12059 12321 12583 12845 13107 13369 13631 13894 14156 14418 14680 14942 15204 15466 15729 15991 16253 16515 16777 VCO (kHz) W=0 Z=x X=x 17302 17826 18350 18874 19399 19923 20447 20972 21496 22020 22544 23069 23593 24117 24642 25166 25690 26214 26739 27263 27787 28312 28836 29360 29884 30409 30933 31457 31982 32506 33030 33554 Z=0 X=0 2163 2228 2294 2359 2425 2490 2556 2621 2687 2753 2818 2884 2949 3015 3080 3146 3211 3277 3342 3408 3473 3539 3604 3670 3736 3801 3867 3932 3998 4063 4129 4194 X=1 34603 35652 36700 37749 38797 39846 40894 41943 42992 44040 45089 46137 47186 48234 49283 50332 51380 52429 53477 54526 55575 56623 57672 58720 59769 60817 61866 62915 63963 65012 66060 67109 VCO (kHz) CLKOUT (kHz) W=1 Z=1 X=0 17302 17826 18350 18874 19399 19923 20447 20972 21496 22020 22544 23069 23593 24117 24642 25166 25690 26214 26739 27263 27787 28312 28836 29360 29884 30409 30933 31457 31982 32506 33030 33554 X=1 34603 35652 36700 37749 38797 39846 40894 41943 42992 44040 45089 46137 47186 48234 49283 50332 51380 52429 53477 54526 55575 56623 57672 58720 59769 60817 61866 62915 63963 65012 66060 67109 W=1 Z=x X=x 69206 71303 73400 75497 77595 79692 81789 83886 85983 88080 90178 92275 94372 96469 98566 100663 102760 104858 106955 109052 111149 113246 115343 117441 119538 121635 123732 125829 127926 130023 132121 134218
NOTES: 1. Some W/X/Y/Z bit combinations shown may select a CLKOUT or VCO frequency higher than spec. Refer to Section 11 Electrical Characteristics for CLKOUT and VCO frequency limits. 2. Any change to W or Y results in a change in the VCO frequency - the VCO should be allowed to relock if necessary
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4.2.3.3 CLOCK CONTROL. The clock control circuits determine the source used for both internal and external clocks during special circumstances, such as low-power stop (LPSTOP) execution. Table 4-3 summarizes the clock activity during LPSTOP in crystal mode operation. Any clock in the off state is held low. The STEXT and STSIM bits in the SYNCR control clock activity during LPSTOP. Refer to 4.2.6 Low-Power Stop for additional information. Table 4-3. Clock Control Signals
Control Bits STSIM 0 0 1 1 STEXT 0 1 0 1 Clock Outputs SIMCLK EXTAL EXTAL VCO VCO CLKOUT Off EXTAL Off VCO
NOTE: SIMCLK runs the periodic interrupt RESET and IRQ pin synchronizers in LPSTOP mode.
4.2.4 Chip Select Operation
Typical microprocessor systems require external hardware to provide select signals to external memory and peripherals. The MC68341 integrates these functions on chip to provide the cost, speed, and reliability benefits of a higher level of integration. The chip select function contains register pairs for each external chip select signal. The pair consists of a base address register and an address mask register that define the characteristics of a single chip select. The register pair provides flexibility for a wide variety of chip select functions. There are also two registers associated with each chip select to support 68000 bus operation. The bus select register defines the type of bus cycle for each chip select. The map select register defines the 68000 bus byte peripherals. 4.2.4.1 PROGRAMMABLE FEATURES. The chip select function supports the following programmable features: Eight Programmable Chip Select Circuits All eight chip select circuits are independently programmable from the same list of selectable features. Each chip select circuit has an individual base address register and address mask register that contain the programmed characteristics of that chip select. The base address register selects the starting address for the address block in 256-byte increments. The address mask register specifies the size of the address block range. The base address register V-bit indicates that the register information for that chip select is valid. A global chip select (CS0 ) allows address decode for a boot ROM before system initialization occurs.
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Variable Block Sizes The block size, starting from the specified base address, can vary in size from 256 bytes up to 4 Gbytes in 2n increments. The specified base address must be on a multiple of the block size. The block size is specified in the address mask register. Both 8- and 16-Bit Ports Supported in M68300 Bus Cycle Mode The 8-bit ports are accessible on both odd and even addresses when connected to data bus bits 15-8; the 16-bit ports can be accessed as odd bytes, even bytes, or even words in M68300 bus mode. The port size is specified by the PS bits in the address mask register. Write Protect Capability The WP bit in each base address register can restrict write access to its range of addresses. Fast Termination Option (M68300 Bus Mode Only) Programming the FTE, EDS, and DD bits in the base address register for the fast termination option causes the chip select to terminate the cycle by asserting the internal DSACK early, providing a two-cycle external access in M68300 mode. Internal DSACK Generation for External Accesses with Programmable Wait States DSACK can be generated internally with up to six wait states for a particular device using the EDS and DD bits in the address mask register. Full 32-Bit Address Decode with Address Space Checking The FC bits in the base address register and FCM bits in the address mask register are used to select address spaces for which the chip selects will be asserted. 4.2.4.2 GLOBAL CHIP SELECT OPERATION. Global chip select operation allows address decode for a boot ROM before system initialization occurs. CS0 is the global chip select output, and its operation differs from the other external chip select outputs following reset. When the CPU32 begins fetching after reset, CS0 is asserted for every address until the V-bit is set in the CS0 base address register. NOTE If an access matches multiple chip selects, the lowest numbered chip select will have priority. For example, if CS0 and CS2 "overlap" for a certain range, CS0 will assert when accessing the "overlapped" address range, and CS2 will not. Global chip select provides a 16-bit port with six wait states, which allows a boot ROM to be located in any address space and still provide the stack pointer and program counter values at $00000000 and $00000004, respectively. Global chip select does not provide write protection and responds to all function codes. While CS0 is a global chip select, no other chip select (CS7-CS1) can be used. CS0 operates in this manner until the V-bit is set in the CS0 base address register, which will then allow the use of CS7-CS1. Provided
4-16 MC68341 USER'S MANUAL MOTOROLA
the desired address range is first loaded into the CS0 base address register, CS0 can be programmed to continue decode for a range of addresses after the V-bit is set. After the V-bit is set for CS0 , global chip select can only be restarted with a system reset. After the V-bit is set, the CS0 pin can alternately be used as the AVEC input. The AVEC bit in the MCR controls the function of this pin, as shown in Table 4-4. Table 4-4. Port B Pin Assignment Register
Pin Function Signal CS0 AVEC Bit = 0 CS0 AVEC Bit = 1 AVEC
A system can use an 8-bit boot ROM if an external 8-bit DSACK that responds in five or less wait states is generated. The 8-bit DSACK must respond in five or less wait states so that the global chip select, which responds with six wait states, will not be used. See Section 11 Applications for a detailed discussion.
4.2.5 External Bus Interface Operation
This section describes port A and port B functions. Refer to Section 3 Bus Operation for more information about the EBI. 4.2.5.1 PORT A. Port A pins can be independently programmed to function as either addresses A31-A24, discrete I/O pins, or IACKx pins. The port A pin assignment registers (PPARA1 and PPARA2) control the function of the port A pins as listed in Table 4-5. Upon reset, port A is configured as input pins. If the system uses these signals as addresses, pulldowns should be put on these signals to avoid indeterminate values until the port A registers can be programmed. Table 4-5 Port A Pin Assignment Register
Pin Function Signal A31 A30 A29 A28 A27 A26 A25 A24 PPARA1 = 0 PPARA2 = 0 A31 A30 A29 A28 A27 A26 A25 A24 PPARA1 = 1 PPARA2 = X PORT A7 PORT A6 PORT A5 PORT A4 PORT A3 PORT A2 PORT A1 PORT A0 PPARA1 = 0 PPARA2 = 1 IACK7 IACK6 IACK5 IACK4 IACK3 IACK2 IACK1 --
4.2.5.2 PORT B. Port B pins can be independently programmed to function as IRQ or discrete I/O pins. Selection of a pin function is accomplished by the port B pin assignment register (PPARB). See Table 4-6 for port B selections. By changing the value of the
MOTOROLA MC68341 USER'S MANUAL 4-17
corresponding bits in the PPARB for a particular signal, the port B pins can be configured for different pin functions. Upon reset, port B is configured as IRQ7-IRQ1, MODCK. Table 4-6. Port B Pin Assignment Register
Pin Function Signal IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 PPARB = 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PPARB = 1 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MODCK
NOTE: MODCK has no function after reset.
4.2.6 Low-Power Stop
Executing the LPSTOP instruction provides reduced power consumption when the MC68341 is idle; only the SIM41 remains active. Operation of the SIM41 clock and CLKOUT during LPSTOP is controlled by the STSIM and STEXT bits in the SYNCR (see Table 4-3). LPSTOP disables the clock to the software watchdog in the low state. The software watchdog remains stopped until the LPSTOP mode ends; it begins to run again on the next rising clock edge. NOTE When the CPU32 executes the STOP instruction (as opposed to LPSTOP), the software watchdog continues to run. If the software watchdog is enabled, it issues a reset or interrupt when timeout occurs. The periodic interrupt timer and real time clock do not respond to an LPSTOP instruction; thus, they can be used to exit LPSTOP as long as their interrupt request level is higher than the CPU32 interrupt mask level. To stop the periodic interrupt timer while in LPSTOP, the PITR must be loaded with a zero value before LPSTOP is executed. The bus monitor, double bus fault monitor, and spurious interrupt monitor are all inactive during LPSTOP. The STP bit in the MCR of each on-chip module (DMA, timer, and serial modules) should be set prior to executing the LPSTOP instruction. Setting the STP bit stops all clocks within each of the modules, except for the clock from the IMB. The clock from the IMB remains active to allow the CPU32 access to the MCR of each module. The system clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or until reset. For more information, see the description of the MCR STP bit for each module.
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If an external device requires additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT (see 3.4.2 LPSTOP Broadcast Cycle ).
4.2.7 Freeze
FREEZE is asserted by the CPU32 if a breakpoint is encountered with background mode enabled. Refer to Section 5 CPU32 for more information on the background mode. When FREEZE is asserted, the double bus fault monitor and spurious interrupt monitor continue to operate normally. However, the software watchdog, the periodic interrupt timer and the internal bus monitor will be affected. When FREEZE is asserted, setting the FRZ1 bit in the MCR disables the software watchdog and periodic interrupt timer, and setting the FRZ0 bit in the MCR disables the bus monitor.
4.3 PROGRAMMING MODEL
Figure 4-8 is a programming model (register map) of all registers in the SIM41. For more information about a particular register, refer to the description of the module or function indicated in the right column. The ADDR (address) column indicates the offset of the register from the address stored in the module base address register. The FC (function code) column indicates whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user space (S/U). For the registers discussed in the following pages, the number in the upper right-hand corner indicates the offset of the register from the address stored in the module base address register. The numbers on the top line of the register represent the bit position in the register. The second line contains the mnemonic for the bit. The numbers below the register represent the bit values after a hardware reset. The access privilege is indicated in the lower right-hand corner. NOTE: A CPU32 RESET instruction will not affect any of the SIM41 registers.
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ADDR 000 004 006 008 010 012 014 016 018 01A 01C 01E 020 022 024 026 028 03C 03E 040 042 044 046 048 04A 04C 04E 050 052 054 056 058 05A 05C 05E 060 062 064 066
FC S S S S S/U S/U S S S/U S/U S/U S S S S S S S S S S S S S S S S S S S S S S S S S S S S
15
87 MODULE CONFIGURATION REGISTER (MCR) CLOCK SYNTHESIZER CONTROL REGISTER (SYNCR) AUTOVECTOR REGISTER (AVR) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SW INTERRUPT VECTOR (SWIV) RESET STATUS REGISTER (RSR) PORT A DATA (PORTA) PORT A DATA DIRECTION (DDRA) PORT A PIN ASSIGNMENT 1 (PPRA1) PORT A PIN ASSIGNMENT 2 (PPRA2) PORT B DATA (PORTB) PORT B DATA (PORTB1) PORT B DATA DIRECTION (DDRB) PORT B PIN ASSIGNMENT (PPARB) PROGRAMMABLE INTERRUPT (PIR)
0 SYS PROTECT CLOCK SYS PROTECT EBI EBI EBI EBI EBI EBI EBI EBI EBI SYS PROTECT SYS PROTECT SYS PROTECT SYS PROTECT EBI CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT
SYSTEM PROTECTION CONTROL (SYPCR) PERIODIC INTERRUPT VECTOR (PICR) PERIODIC INTERRUPT TIMING PITR) SOFTWARE SERVICE (SWSR) PORT C PIN ASSIGNMENT (PPARC)
PERIODIC INTERRUPT CONTROL (PICR) SCALE SELECT (SSR) RESERVED RESERVED
BUS SELECT (BSR) MAP SELECT (MSR) ADDRESS MASK 1 CS0 ADDRESS MASK 2 CS0 BASE ADDRESS 1 CS0 BASE ADDRESS 2 CS0 ADDRESS MASK 1 CS1 ADDRESS MASK 2 CS1 BASE ADDRESS 1 CS1 BASE ADDRESS 2 CS1 ADDRESS MASK 1 CS2 ADDRESS MASK 2 CS2 BASE ADDRESS 1 CS2 BASE ADDRESS 2 CS2 ADDRESS MASK 1 CS3 ADDRESS MASK 2 CS3 BASE ADDRESS 1 CS3 BASE ADDRESS 2 CS3 ADDRESS MASK 1 CS4 ADDRESS MASK 2 CS4 BASE ADDRESS 1 CS4 BASE ADDRESS 2 CS4
Figure 4-8. SIM41 Programming Model
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068 06A 06C 06E 070 072 074 076 078 07A 07C 07E 0C0 0C2 0C4 0C6 0C8 0CA 0CE FF
S S S S S S S S S S S S S S/U S/U S/U S/U S/U S/U S MINUTES (MIN) DATE MONTH RTC CONTROL (RCR)
ADDRESS MASK 1 CS5 ADDRESS MASK 2 CS5 BASE ADDRESS 1 CS5 BASE ADDRESS 2 CS5 ADDRESS MASK 1 CS6 ADDRESS MASK 2 CS6 BASE ADDRESS 1 CS6 BASE ADDRESS 2 CS6 ADDRESS MASK 1 CS7 ADDRESS MASK 2 CS7 BASE ADDRESS 1 CS7 BASE ADDRESS 2 CS7 SECONDS (SEC) HOUR YEAR DAY SECONDS ALARM (SECA) HOURS ALARM (HOURA) CALIBRATION (RCCR) RESERVED
CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT RTC RTC RTC RTC RTC RTC RTC
MINUTES ALARM (MINA) DATE ALARM (DATEA) RESERVED
Figure 4-8. SIM41 Programming Model (Continued)
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4.3.1 Module Base Address Register (MBAR)
MBAR 1
31
BA31 RESET: 0
$0003FF00
29
BA29
30
BA30
28
BA28
27
BA27
26
BA26
25
BA25
24
BA24
23
BA23
22
BA22
21
BA21
20
BA20
19
BA19
18
IBA18
17
BA17
16
BA16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPU Space Only MBAR 2
15
BA15 RESET 0
$0003FF02
13
BA13
14
BA14
12
BA12
11
0
10
0
9
AS8
8
AS7
7
AS6
6
AS5
5
AS4
4
AS3
3
AS2
2
AS1
1
AS0
0
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPU Space Only BA31-BA12--Base Address Bits 31-12 The base address field is the upper 20 bits of the MBAR that provides for block starting locations in increments of 4-Kbytes. Bits 11, 10--Reserved AS8-AS0--Address Space Bits 8-0 The address space field allows particular address spaces to be masked, placing the 4K module block into a particular address space(s). If an address space is masked, an access to the register block location in that address space becomes an external access. The module block is not accessed. The address space bits are as follows: AS8--mask DMA Space address space (FC3-FC0 = 1xxx) AS7--mask CPU Space address space (FC3-FC0 = 0111) AS6--mask Supervisor Program address space (FC3-FC0 = 0110) AS5--mask Supervisor Data address space (FC3-FC0 = 0101) AS4--mask Reserved [Motorola] address space (FC3-FC0 = 0100) AS3--mask Reserved [User] address space (FC3-FC0 = 0011) AS2--mask User Program address space (FC3-FC0 = 0010) AS1--mask User Data address space (FC3-FC0 = 0001) AS0--mask Reserved [Motorola] address space (FC3-FC0 = 0000) For each address space bit: 1 = Mask this address space from the internal module selection. The bus cycle goes external. 0 = Decode for the internal module block. V--Valid Bit This bit indicates when the contents of the MBAR are valid. The base address value is not used; therefore, all internal module registers are not accessible until the V-bit is set. 1 = Contents are valid. 0 = Contents are not valid.
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NOTE An access to this register does not affect external space since the cycle is not run externally. Example code for accessing the MBAR is as follows: Register D0 will contain the value of MBAR. MBAR can be read using the following code:
MOVE.L MOVEC.L LEA.L MOVES.L #7,D0 D0,SFC $0003FF00,A0 (A0),D0 load D0 with the CPU space function code load SFC to indicate CPU space load A0 with the address of MBAR lread MBAR
Address $0003FF00 in CPU space (MBAR) will be loaded with the value $FFFFF101. This value will set the base address of the internal registers to $FFFFF000. MBAR can be written to using the following code:
MOVE.L MOVEC.L LEA.L MOVE.L MOVES.L #7,D0 D0,DFC $0003FF00,A0 #$FFFFF101,D0 D0,(A0) load D0 with the CPU space function code load DFC to indicate CPU space load A0 with the address of MBAR base=FFFFF000, AS7=no CPU space, validate write MBAR
4.3.2 System Configuration and Protection Registers
The following paragraphs provide descriptions of the system configuration and protection registers. 4.3.2.1 MODULE CONFIGURATION REGISTER (MCR). The MCR, which controls the SIM41 configuration, can be read or written at any time. MCR
15
0 RESET: 0
$000
14
FRZ1
13
FRZ0
12
AVEC
11
0
10
0
9
SHEN1
8
SHEN0
7
SUPV
6
0
5
0
4
0
3
IARB3
2
IARB2
1
IARB1
0
IARB0
1
1
0
0
0
0
0
1
0
0
0
1
1
1
1
Supervisor Only Bits 15, 11, 10, 6-4--Reserved FRZ1--Freeze Software Enable 1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are disabled, preventing interrupts from occurring during software debug. 0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run. See 4.2.7 Freeze for more information.
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FRZ0--Freeze Bus Monitor Enable 1 = When FREEZE is asserted, the bus monitor is disabled. 0 = When FREEZE is asserted, the bus monitor continues to operate as programmed. AVEC--Automatic Vector Response 1 = Automatic vector response enabled. 0 = Automatic vector response disabled. SHEN1, SHEN0--Show Cycle Enable These two control bits determine what the EBI does with the external bus during internal transfer operations (see Table 4-7). A show cycle allows internal transfers to be externally monitored. The address, data, and control signals (except for AS) are driven externally. DS is used to signal address strobe timing for show cycles. Data is valid on the next falling clock edge after DS is negated. However, data is not driven externally, and AS and DS are not asserted externally for internal accesses unless show cycles are enabled. If external bus arbitration is disabled, the EBI will not recognize an external bus request until arbitration is enabled again. To prevent bus conflicts, external peripherals must not attempt to initiate cycles during show cycles with arbitration disabled. Table 4-7. SHENx Control Bits
SHEN1 0 0 1 SHEN0 0 1 X ACTION Show cycle s disabled, external arbitration enabled Show cycles enabled, external arbitration disabled Show cycles enabled, external arbitration enabled
SUPV--Supervisor/User Data Space The SUPV bit defines the SIM41 registers as either supervisor data space or user (unrestricted) data space. 1 = The SIM41 registers defined as supervisor/user are restricted to supervisor data access (FC3-FC0 = $5). An attempted user-space write is ignored and returns BERR . 0 = The SIM41 registers defined as supervisor/user data are unrestricted (FC2 is a don't care). IARB3-IARB0--Interrupt Arbitration Bits 3-0 These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level. No two modules can share the same IARB value. The reset value of IARB is $F, allowing the SIM41 to arbitrate during an IACK cycle immediately after reset. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). A value of $0 prevents arbitration and causes all SIM41 interrupts, including external interrupts, to be discarded as extraneous.
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4.3.2.2 AUTOVECTOR REGISTER (AVR). The AVR contains bits that correspond to external interrupt levels that require an autovector response. Setting a bit allows the SIM41 to assert an internal AVEC during the IACK cycle in response to the specified interrupt request level. This register can be read and written at any time. AVR
7
AV7 RESET: 0
$006
6
AV6
5
AV5
4
AV4
3
AV3
2
AV2
1
AV1
0
0
0
0
0
0
0
0
0
Supervisor Only NOTE: The IARB field in the MCR must contain a value other than $0 for the SIM41 to autovector for external interrupts. 4.3.2.3 RESET STATUS REGISTER (RSR). The RSR contains a bit for each reset source to the SIM41. A set bit indicates the last type of reset that occurred, and only one bit can be set in the register. The RSR is updated by the reset control logic when the SIM41 comes out of reset. This register can be read at any time; a write has no effect. For more information, see Section 3 Bus Operation. RSR
7
EXT
$007
6
POW
5
SW
4
DBF
3
0
2
LOC
1
SYS
0
0
Supervisor Only EXT--External Reset 1 = The last reset was caused by an external signal driving RESET. POW--Power-Up Reset 1 = The last reset was caused by the power-up reset circuit. SW--Software Watchdog Reset 1 = The last reset was caused by the software watchdog circuit. DBF--Double Bus Fault Monitor Reset 1 = The last reset was caused by the double bus fault monitor. Bits 3, 0--Reserved LOC--Loss of Clock Reset 1 = The last reset was caused by a loss of frequency reference to the clock synthesizer. This reset can only occur if the RSTEN bit in the SYNCR is set and the VCO is enabled.
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SYS--System Reset 1 = The last reset was caused by the CPU32 executing a RESET instruction. The system reset does not load a reset vector or affect any internal CPU32 registers, SIM41 configuration registers, or the MCR in each internal peripheral module (DMA, timers, and serial modules). It will, however, reset external devices and all other registers in the peripheral modules. 4.3.2.4 SOFTWARE INTERRUPT VECTOR REGISTER (SWIV). The SWIV contains the 8-bit vector that is returned by the SIM41 during an IACK cycle in response to an interrupt generated by the software watchdog. This register can be read or written at any time. This register is set to the uninitialized vector, $0F, at reset. SWIV
7
SWIV7 RESET: 0
$020
6
SWIV6
5
SWIV5
4
SWIV4
3
SWIV3
2
SWIV2
1
SWIV1
0
SWIV0
0
0
0
1
1
1
1
Supervisor Only 4.3.2.5 SYSTEM PROTECTION CONTROL REGISTER (SYPCR). The SYPCR controls the system monitors, the prescaler for the software watchdog, and the bus monitor timing. This register can be read at any time, but can be written only once after reset. SYPCR
7
SWE RESET: 0
$021
6 5
SWT1
4
SWT0
3
DBFE
2
BME
1
BMT1
0
BMT0
SWRI
0
0
0
0
0
0
0
Supervisor Only SWE--Software Watchdog Enable 1 = Software watchdog is enabled. 0 = Software watchdog is disabled. See 4.2.2.5 Software Watchdog for more information. SWRI--Software Watchdog Reset/Interrupt Select 1 = Software watchdog causes a system reset. 0 = Software watchdog causes a level 7 interrupt to the CPU32. SWT1, SWT0--Software Watchdog Timing These bits, along with the SWP bit in the PITR, control the divide ratio used to establish the timeout period for the software watchdog. The software watchdog timeout period is given by the following formula: divide count EXTAL frequency
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The software watchdog timeout period, listed in Table 4-8, gives the formula to derive the software watchdog timeout for any clock frequency. The timeout periods are listed for a 32.768-kHz crystal used with the VCO and for a 16.777-MHz external oscillator with divide by one selected by the V-bit of the SYNCR. Table 4-8. Deriving Software Watchdog Timeout
SWP 0 0 0 0 1 1 1 1 NOTE: SWT1 0 0 1 1 0 0 1 1 SWT0 0 1 0 1 0 1 0 1 Software Timeout Period 29/EXTAL Input Frequency 211 /EXTAL Input Frequency 213 /EXTAL Input Frequency 215 /EXTAL Input Frequency 218 /EXTAL Input Frequency 220 /EXTAL Input Frequency 222 /EXTAL Input Frequency 224 /EXTAL Input Frequency 32.768-kHz Crystal Period 15.6 ms 62.5 ms 250 ms 1s 8s 32 s 128 s 512 s 16.777-MHz External Clock Period 30 s 122 s 488 s 1.95 ms 15.6 ms 62.5 ms 250 ms 1s
When the SWP and SWT bit s are modified to select a software timeout other than the default, the software service sequence ($55 followed by $AA written to the software service register) must be performed before the new timeout period takes effect. Refer to 4.2.2.5 Software Watchdog for more information.
DBFE--Double Bus Fault Monitor Enable 1 = Enable double bus fault monitor function. 0 = Disable double bus fault monitor function. For more information, see 4.2.2.3 Double Bus Fault Monitor and Section 5 CPU32. BME--Bus Monitor External Enable 1 = Enable bus monitor function for an internal-to-external bus cycle. 0 = Disable bus monitor function for an internal-to-external bus cycle. For more information see 4.2.2.2 Internal Bus Monitor. BMT1, BMT0--Bus Monitor Timing These bits select the timeout period for the bus monitor (see Table 4-9). Upon reset, the bus monitor is set to 512 system clocks. Table 4-9. BMTx Encoding
BMT1 0 0 1 1 BMT0 0 1 0 1 Bus Monitor Timeout Period 512 system clocks (CLKOUT) 256 system clocks 128 system clocks 64 system clocks
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4.3.2.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the interrupt level and the vector number for the periodic interrupt request. This register can be read or written at any time. Bits 15-11 are unimplemented and always return zero; a write to these bits has no effect. PICR
15
0 RESET: 0
$022
14
0
13
0
12
0
11
0
10
9
8
7
PIV7
6
PIV6
5
PIV5
4
PIV4
3
PIV3
2
PIV2
1
PIV1
0
PIV0
PIRQL2 PIRQL1 PIRQL0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Supervisor Only Bits 15-11--Reserved PIRQL2-PIRQL0--Periodic Interrupt Request Level These bits contain the periodic interrupt request level. Table 4-10 lists which interrupt request level is asserted during an IACK cycle when a periodic interrupt is generated. The periodic timer continues to run when the interrupt is disabled. Table 4-10. PIRQL Encoding
PIRQL2 0 0 0 0 1 1 1 1 PIRQL1 0 0 1 1 0 0 1 1 PIRQL0 0 1 0 1 0 1 0 1 Interrupt Request Level Periodic Interrupt Disabled Interrupt Request Level 1 Interrupt Request Level 2 Interrupt Request Level 3 Interrupt Request Level 4 Interrupt Request Level 5 Interrupt Request Level 6 Interrupt Request Level 7
NOTE: Use caution with a level 7 interrupt encoding due to the SIM41's interrupt servicing order. See 4.2.2.7 Simultaneous Interrupts by Sources in the SIM41 for the servicing order. PIV7-PIV0--Periodic Interrupt Vector Bits 7-0 These bits contain the value of the vector generated during an IACK cycle in response to an interrupt from the periodic timer. When the SIM41 responds to the IACK cycle, the periodic interrupt vector from the PICR is placed on the bus. This vector number is multiplied by four to form the vector offset, which is added to the vector base register to obtain the address of the vector. 4.3.2.7 PERIODIC INTERRUPT TIMER REGISTER (PITR). The PITR contains control for prescaling the software watchdog and periodic timer as well as the count value for the
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periodic timer. This register can be read or written at any time. Bits 15-10 are not implemented and always return zero when read. A write does not affect these bits. PITR
15
0 RESET: 0
$024
14
0
13
0
12
0
11
0
10
0
9
SWP
8
PTP
7
PITR7
6
PITR6
5
PITR5
4
PITR4
3
PITR3
2
PITR2
1
PITR1
0
PITR0
0
0
0
0
0
MODCK MODCK
0
0
0
0
0
0
0
Supervisor Only Bits 15-10--Reserved SWP--Software Watchdog Prescale This bit controls the software watchdog clock source as shown in 4.3.2.5 System Protection Control Register (SYPCR). 1 = Software watchdog clock prescaled by a value of 512. 0 = Software watchdog clock not prescaled. The SWP reset value is the inverse of the MODCK bit state on the rising edge of reset. PTP--Periodic Timer Prescaler Control This bit contains the prescaler control for the periodic timer. 1 = Periodic timer clock prescaled by a value of 512. 0 = Periodic timer clock not prescaled. The PTP reset value is the inverse of the MODCK bit state on the rising edge of reset. PITR7-PITR0--Periodic Interrupt Timer Register Bits 7-0 The remaining bits of the PITR contain the count value for the periodic timer. A zero value turns off the periodic timer. 4.3.2.8 SOFTWARE SERVICE REGISTER (SWSR). The SWSR is the location to which the software watchdog servicing sequence is written. The software watchdog can be enabled or disabled by the SWE bit in the SYPCR. SWSR can be written at any time, but returns all zeros when read. SWSR
7 6 5 4 3 2 1
$027
0
SWSR7 SWSR6 SWSR5 SWSR4 SWSR3 SWSR2 SWSR1 SWSR0 RESET: 0
0
0
0
0
0
0
0
Supervisor Only
4.3.3 Clock Synthesizer Control Register (SYNCR)
The SYNCR can be read or written only in supervisor mode. The reset state of SYNCR produces an operating frequency of 8.39 MHz when the PLL is referenced to a 32.768-
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kHz reference signal. The system frequency is controlled by the frequency control bits in the upper byte of the SYNCR as follows: FSYSTEM = FCRYSTAL [2(2W+X+3Z-1) ] x (Y+1) SYNCR
15
W RESET: 0
$004
14
X
13
Y5
12
Y4
11
Y3
10
Y2
9
Y1
8
Y0
7
Z
6
V
5
0
4
3
2
RSTEN
1
STSIM
0
STEXT
SLIMP SLOCK
0
1
1
1
1
1
1
1
0
0
U
U
0
0
0
U = Unaffected by reset
Supervisor Only
W--Frequency Control Bit This bit controls the prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO frequency by a factor of 4, requiring a time delay for the VCO to relock (see equation for determining system frequency). X--Frequency Control Bit This bit controls a divide-by-two prescaler, which is not in the synthesizer feedback loop. Setting the bit doubles the system clock speed without changing the VCO speed, as specified in the equation for determining system frequency; therefore, no delay is incurred to relock the VCO. Y5-Y0--Frequency Control Bits The Y-bits, with a value from 0-63, control the modulus downcounter in the synthesizer feedback loop, causing it to divide by the value of Y+1 (see the equation for determining system frequency). Changing these bits requires a time delay for the VCO to relock. Z--Frequency Control Bit This bit controls a divide-by-eight. Setting the bit increases the system clock frequency by a factor of eight, without changing the VCO speed. V--Frequency Control Bit This bit controls a divide-by-two on the external clock input (EXTCLK). Clearing the bit allows the VCO to run at half the speed of the external clock. Changing the bit value requires a time delay for the VCO to relock. Bits 5--Reserved Bit 5 is reserved. SLIMP--Limp Mode 1 = A loss of input signal reference has been detected, and the VCO is running at approximately one-half the maximum speed (affected by the X-bit ), determined from an internal voltage reference. 0 = External input signal frequency is at VCO reference.
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MOTOROLA
SLOCK--Synthesizer Lock 1 = VCO has locked onto the desired frequency (or system clock is driven externally). 0 = VCO is enabled, but has not yet locked. RSTEN--Reset Enable 1 = Loss of input signal causes a system reset. 0 = Loss of input signal causes the VCO to operate at a nominal speed without external reference (limp mode), and the device continues to operate at that speed. STSIM--Stop Mode System Integration Clock 1 = When LPSTOP is executed, the SIM41 clock is driven from the VCO. 0 = When LPSTOP is executed, the SIM41 clock is driven from an external crystal or oscillator, and the VCO is turned off to conserve power. STEXT--Stop Mode External Clock 1 = When the LPSTOP instruction is executed, the external clock pin (CLKOUT) is driven from the SIM41 clock as determined by the STSIM bit. 0 = When the LPSTOP instruction is executed, the external clock (CLKOUT) is held low to conserve power. No external clock will be driven in LPSTOP mode.
4.3.4 Chip Select Registers
The following paragraphs provide descriptions of the registers in the chip select function, and an example of how to program the registers. The chip select registers cannot be used until the V-bit in the MBAR is set. 4.3.4.1 BASE ADDRESS REGISTERS. There are eight 32-bit base address registers in the chip select function, one for each chip select signal. Base Address 1
31
BA31 RESET: U
$044, $04C, $054, $05C, $064, $06C, $074, $07C
28
BA28
30
BA30
29
BA29
27
BA27
26
BA26
25
BA25
24
BA24
23
BA23
22
BA22
21
BA21
20
BA20
19
BA19
18
BA18
17
BA17
16
BA16
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Supervisor Only Base Address 2
15
BA15 RESET: U
$046, $04E, $056, $05E, $066, $06E, $076, $07E
12
BA12
14
BA14
13
BA13
11
BA11
10
BA10
9
BA9
8
BA8
7
BFC3
6
BFC2
5
BFC1
4
BFC0
3
WP
2
EDS
1
NCS
0
V
U
U
U
U
U
U
U
U
U
U
U
U
U
0
0
U = Unaffected by reset
Supervisor Only
BA31-BA8--Base Address Bits 31-8 The base address field, the upper 24 bits of each base address register, selects the starting address for the chip select. The specified base address must be on a multiple of
MOTOROLA MC68341 USER'S MANUAL 4-31
the selected block size. The corresponding bits, AM31-AM8, in the address mask register define the size of the block for the chip select. The base address field (and the base function code field) is compared to the address on the address bus to determine if a chip select should be generated. BFC3-BFC0--Base Function Code Bits 3-0 The value programmed into this field causes a chip select to be asserted for a certain address space type. There are nine function code address spaces (see Section 3 Bus Operation) specified as either user or supervisor, program or data, CPU, and DMA. These bits should be used to allow access to one type of address space. If access to more than one type of address space is desired, the FCMx bits should be used in addition to the BFCx bits. To prevent access to CPU space, set the NCS bit. WP--Write Protect This bit can restrict write accesses to the address range in a base address register. An attempt to write to the range of addresses specified in a base address register that has this bit set returns BERR . 1 = Only read accesses are allowed. 0 = Either read or write accesses are allowed. EDS--Extended Delay Select This bit is used in combination with the DD bits in the Address Mask registers to select the number of wait states added before an internal DSACK is supplied. See Table 411. 1 = Extended delay enabled . 0 = Extended delay disabled. NCS--No CPU Space This bit specifies whether or not a chip select will assert on a CPU space access cycle (FC3-FC0 = $7 or $F). If both supervisor data and program accesses are desired, while ignoring CPU space accesses, then this bit should be set. The NCS bit is cleared at reset. 1 = Suppress the chip select on a CPU space access. 0 = Assert the chip select on a CPU space access. V--Valid Bit This bit indicates that the contents of its base address register and address mask register pair are valid. The programmed chip selects do not assert until the V-bit is set. A reset clears the V-bit in each base address register, but does not change any other bits in the base address and address mask registers (CS0 is a special case, see 4.2.4.2 Global Chip Select Operation). 1 = Contents are valid. 0 = Contents are not valid.
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MOTOROLA
4.3.4.2 ADDRESS MASK REGISTERS. There are eight 32-bit address mask registers in the chip select function, one for each chip select signal. Address Mask 1
31
AM31 RESET: U
$040, $048, $050, $058, $060, $068, $070, $078
28
AM28
30
AM30
29
AM29
27
AM27
26
AM26
25
AM25
24
AM24
23
AM23
22
AM22
21
AM21
20
AM20
19
AM19
18
AM18
17
AM17
16
AM16
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Supervisor Only Address Mask 2
15
AM15 RESET: U
$042, $04A, $052, $05A, $062, $06A, $072, $07A
12
AM12
14
AM14
13
AM13
11
AM11
10
AM10
9
AM9
8
AM8
7
FCM3
6
FCM2
5
FCM1
4
FCM0
3
DD1
2
DD0
1
PS1
0
PS0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U = Unaffected by reset
Supervisor Only
AM31-AM8--Address Mask Bits 31-8 The address mask field, the upper 24 bits of each address mask register, defines the chip select block size. The block size is equal to 2n , where n = (number of bits set in the address mask field) + 8. Any set bit masks the corresponding base address register bit (the base address register bit becomes a don't care). By masking the address bits independently, external devices of different size address ranges can be used. Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. This field can be read or written at any time. FCM3-FCM0--Function Code Mask Bits 3-0 This field can be used to mask certain function code bits, allowing more than one address space type to be assigned to a chip select. Any set bit masks the corresponding function code bit. DD1, DD0--DSACK Delay Bits 1 and 0 This field, in combination with the EDS bit determines the number of wait states added before an internal DSACK is returned for that entry. Table 4-11 lists the encoding for the DD and EDS bits. NOTE: The port size field must be programmed for an internal DSACK response for the DDx bits to have significance. If external DSACK signals are returned earlier than indicated by the DDx and EDS bits, the cycle will terminate sooner than programmed.
MOTOROLA
MC68341 USER'S MANUAL
4-33
Table 4-11. DDx Encoding
EDS 0 0 0 0 1 1 1 1 DD1 0 0 1 1 0 0 1 1 DD0 0 1 0 1 0 1 0 1 Response Zero Wait State One Wait State Two Wait States Three Wait States Four Wait State Five Wait State Six Wait States Fast Termination Cycle Duration Three Clocks Four Clocks Five Clocks Six Clocks Seven Clocks Eight Clocks Nine Clocks Two Clocks
PS1, PS0--Port Size Bits 1 and 0 This field determines whether a given chip select responds with DSACK and, if so, what port size is returned. Table 4-12 lists the encoding for the PSx bits. Table 4-12. PSx Encoding
PS1 0 0 1 1 PS0 0 1 0 1 Mode Reserved* 16-Bit Port 8-Bit Port External DSACK Response
*Use only for 32-bit DMA transfers.
To use the external DSACK response, PS1-PS0 = 11 should be selected to suppress internal DSACK generation. The DDx and EDS bits then have no significance. 4.3.4.3 BUS SELECT REGISTER. Each chip select can be programmed to select either M68000 bus or M68300 bus address space using the bus select register. An access that does not address internal resources or match one of the external chip select address spaces defaults to an MC68300 bus access. The chip selects are gated out with AS or 68KAS timing for accesses to M68300 or 68000 bus address spaces respectively. Bus Select Register
15 14 13 12 11 10 9 8 7
BSR7
$03C
6
BSR6
5
BSR5
4
BSR4
3
BSR3
2
BSR2
1
BSR1
0
BSR0
RESERVED RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Supervisor Only Setting a bit in the BSR defines the corresponding chip select to be an M68000 bus access and use 68KAS timing for accesses within the defined address range. This register can be read or written at any time.
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MOTOROLA
4.3.4.4 MAP SELECT REGISTER. The map select register can map byte wide peripherals on the M68000 bus to either the upper or lower half of the data bus (even or odd address space). Map Select Register
15 14 13 12 11 10 9 8 7
MSR7
$03E
6
MSR6
5
MSR5
4
MSR4
3
MSR3
2
MSR2
1
MSR1
0
MSR0
RESERVED RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Supervisor Only Setting a bit in the MSR defines the corresponding CS bit to be a byte-wide peripheral. Even/odd select capability is provided by pairing of chip selects, so the base address for an even/odd pair is specified in the even chip select register (CS2 provides base address and range for CS2 and CS3 if MSR3 is set). The base address and range information is combined with the size and A0 information drive the corresponding chip select pins for an even/odd pair of chip selects. If an access addresses both even and odd bytes, then the corresponding even and odd chip select pins are asserted. The chip select implementation requires that odd byte chip selects used for M68000 byte peripherals be paired with even byte chip selects of similar address, but does not restrict even byte peripheral chip selects. For example, if CS2 is used for an M68000 byte peripheral, but there is no byte peripheral in that address range on the lower half of the data bus, then CS3 can be used as a general purpose chip select for any address range, bus type, or port size. 4.3.4.5 CHIP SELECT REGISTERS PROGRAMMING EXAMPLE. The following listing is an example of programming a chip select at starting address $00040000, for a block size of 256 Kbytes, accessing supervisor and user data spaces with a 16-bit port requiring two wait states. There will be no write protection, no fast termination, and no CPU space accesses. base address 1 = $0004 base address 2 = $0013 address mask 1 = $0003 address mask 2 = $FF49 NOTE If an access matches multiple chip selects, the lowest numbered chip select will have priority. For example, if CS0 and CS2 "overlap" for a certain range, CS0 will assert when accessing the "overlapped" address range, and CS2 will not.
4.3.5 External Bus Interface Control
The following paragraphs describe the registers that control the I/O pins used with the EBI. Refer to the Section 3 Bus Operation for more information about the EBI. For a list of pin numbers used with port A and port B, see the pinout diagram in Section 13
MOTOROLA MC68341 USER'S MANUAL 4-35
Ordering Information and Mechanical Data. Section 2 Signal Descriptions shows a block diagram of the port control circuits. 4.3.5.1 PORT A PIN ASSIGNMENT REGISTER 1 (PPARA1). PPARA1 selects between an address and discrete I/O function for the port A pins. Any set bit defines the corresponding pin to be an I/O pin, controlled by the port A data and data direction registers. Any cleared bit defines the corresponding pin to be an address bit as defined in the following register diagram. Bits set in this register override the configuration setting of PPARA2. The $FF reset value of PPARA1 configures port A as an input port. This register can be read or written at any time. PPARA1
7
PRTA7 (A31) RESET: 1
$015
5
PRTA5 (A29)
6
PRTA6 (A30)
4
PRTA4 (A28)
3
PRTA3 (A27)
2
PRTA2 (A26)
1
PRTA1 (A25)
0
PRTA0 (A24)
1
1
1
1
1
1
1
Supervisor Only 4.3.5.2 PORT A PIN ASSIGNMENT REGISTER 2 (PPARA2). PPARA2 selects between an address and IACK function for the port A pins. Any set bit defines the corresponding pin to be an IACK output pin. Any cleared bit defines the corresponding pin to be an address bit as defined in the register diagram. Any set bits in PPARA1 override the configuration set in PPARA2. Bit 0 has no function in this register because there is no level 0 interrupt. This register can be read or written at any time. PPARA2
7
IACK7 (A31) RESET: 0
$017
5
IACK5 (A29)
6
IACK6 (A30)
4
IACK4 (A28)
3
IACK3 (A27)
2
IACK2 (A26)
1
IACK1 (A25)
0
0
0
0
0
0
0
0
0
Supervisor Only The IACK signals are asserted if a bit in PPARA2 is set and the CPU32 services an external interrupt at the corresponding level. IACK signals have the same timing as address strobes. 4.3.5.3 PORT A DATA DIRECTION REGISTER (DDRA). DDRA controls the direction of the pin drivers when the pins are configured as I/O. Any set bit configures the corresponding pin as an output. Any cleared bit configures the corresponding pin as an input. This register affects only pins configured as discrete I/O. This register can be read or written at any time.
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MC68341 USER'S MANUAL
MOTOROLA
DDRA
7
DD7 RESET: 0
$013
6
DD6
5
DD5
4
DD4
3
DD3
2
DD2
1
DD1
0
DD0
0
0
0
0
0
0
0
Supervisor/User 4.3.5.4 PORT A DATA REGISTER (PORTA). PORTA affects only pins configured as discrete I/O. A write to PORTA is stored in the internal data latch, and if any port A pin is configured as an output, the value stored for that bit is driven on the pin. A read of PORTA returns the value at the pin only if the pin is configured as discrete input. Otherwise, the value read is the value stored in the internal data latch. This register can be read or written at any time. PORTA
7
P7 RESET: U
$011
6 5
P5
4
P4
3
P3
2
P2
1
P1
0
P0
P6
U
U
U
U
U
U
U
Supervisor/User 4.3.5.5 PORT B PIN ASSIGNMENT REGISTER (PPARB). PPARB controls the function of each port B pin. Any set bit defines the corresponding pin to be an IRQ input as defined in Table 4-6. Any cleared bit defines the corresponding pin to be a discrete I/O pin controlled by the port B data and data direction registers. The MODCK signal has no function after reset. PPARB is configured to all ones at reset to provide for MODCK, IRQ7- IRQ1 . This register can be read or written at any time. PPARB
7
PPARB7 (IRQ7) RESET: 1
$01F
6 5
PPARB5 (IRQ5)
4
PPARB4 (IRQ4)
3
PPARB3 (IRQ3)
2
PPARB2 (IRQ2)
1
PPARB1 (IRQ1)
0
PPARB0 (MODCK)
PPARB6 (IRQ6)
1
1
1
1
1
1
1
Supervisor Only 4.3.5.6 PORT B DATA DIRECTION REGISTER (DDRB). DDRB controls the direction of the pin drivers when the pins are configured as I/O. Any set bit configures the corresponding pin as an output; any cleared bit configures the corresponding pin as an input. This register affects only pins configured as discrete I/O. This register can be read or written at any time. DDRB
7
DD7 RESET: 0
$01D
6
DD6
5
DD5
4
DD4
3
DD3
2
DD2
1
DD1
0
DD0
0
0
0
0
0
0
0
Supervisor/User
MOTOROLA
MC68341 USER'S MANUAL
4-37
4.3.5.7 PORT B DATA REGISTER (PORTB, PORTB1). This is a single register that can be accessed at two different addresses. This register affects only those pins configured as discrete I/O. A write is stored in the internal data latch, and if any port B pin is configured as an output, the value stored for that bit is driven on the pin. A read of this register returns the value stored in the register only if the pin is configured as a discrete output. Otherwise, the value read is the value of the pin. This register can be read or written at any time. PORTB, PORTB1
7
P7 RESET: U
$019, 01B
4
P4
6
P6
5
P5
3
P3
2
P2
1
P1
0
P0
U
U
U
U
U
U
U
Supervisor/User 4.3.5.8 PORT C PIN ASSIGNMENT REGISTER (PPARC). The MC68341 has multiplexed functions on several pins that had a dedicated function on the MC68340. Five new signals have been added to the DMA module, and the RTCOUT signal is multiplexed with RMC . These new alternate functions are selected by setting the appropriate bit in PPARC. PPARC
7
TIN RDY2 RESET: 0
$029
6 5 4 3
FC3 DTC
2
RMC RTCOUT
1
0
0
0
TGATE DACK2 DACK1 RDY1 DDACK2 DDACK1
0
0
0
0
0
0
0
Supervisor Only
4.4 REAL TIME CLOCK
The SIM41 includes a real time clock and calendar function (RTC), that counts seconds, minutes, hours, days, day of the week, date of the month, month, and year with leap year compensation. The RTC can generate both an internal interrupt and an external output (RTCOUT) based on an alarm or time matching function. The 32.768kHz oscillator and the RTC can continue to operate from the VBATT power pin when VCC is turned off. In typical applications V BATT is connected to a 3V lithium battery to provide backup of the RTC time function. If the RMC /RTCOUT signal is configured as RTCOUT before VCC is powered down, the output drivers for RTCOUT are also powered from VBATT to allow the alarm output to be seen by other system devices. During initial system debug, or for systems which do not require the time function to be non-volatile, VBATT and BSW can be connected to VCC to eliminate the need for a separate power supply source.
4.4.1 Reset
Hardware RESET does not affect the clock or calendar functions of the RTC. When RESET is asserted, the following occurs:
4-38
MC68341 USER'S MANUAL
MOTOROLA
1. The Alarm Indicator Enable/Clear (AIE/C) bit is cleared. 2. The Alarm Indicator (ALARM) bit is cleared. 3. Interrupt control register (RICR) is cleared.
4.4.2 RTC Interrupt Control Register (RICR)
The RICR contains the interrupt level and the vector number for the RTC alarm interrupt request. RTC Interrupt Control Register
15
0 RESET: 0
$0C0
9
RIRQ1
14
0
13
0
12
0
11
0
10
RIRQ2
8
RIRQ0
7
RIV7
6
RIV6
5
RIV5
4
RIV4
3
RIV3
2
RIV2
1
RIV1
0
RIV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Supervisor Only RIRQ2-RIRQ0--RTC Interrupt Request Level These bits contain the real time clock alarm interrupt request level. Table 4-13 lists the interrupt request level asserted during an IACK cycle when an RTC alarm interrupt occurs. The RTC shares the interrupt arbitration bits with the other sub-modules of the SIM41. The relative priority of the SIM41 interrupt sources is: 1. Watchdog timer 2. Periodic timer 3. RTC alarm interrupt 4. External interrupts Table 4-13. RIRQL Encoding
RIRQ2 0 0 0 0 1 1 1 1 RIRQ1 0 0 1 1 0 0 1 1 RIRQ0 0 1 0 1 0 1 0 1 Interrupt Request Level RTC Interrupt Disabled Interrupt Request Level 1 Interrupt Request Level 2 Interrupt Request Level 3 Interrupt Request Level 4 Interrupt Request Level 5 Interrupt Request Level 6 Interrupt Request Level 7
RIV7-RIV0--RTC Interrupt Vector Bits 7-0 These bits contain the value of the vector generated during an IACK cycle in response to an interrupt from the RTC alarm. When the SIM41 responds to an IACK cycle, the RTC interrupt vector is placed on the bus.
MOTOROLA
MC68341 USER'S MANUAL
4-39
4.4.3 RTC Control/Status Register (RCR)
The RCR contains the control bits for the RTC. RCR
7
WR_ERR RESET: U
$0C8
6
ALARM
5
ERRMUX
4
ROS1
3
ROS0
2
AIE/ C
1
RCK_HT
0
SET
0
0
0
0
0
0
0
Supervisor Only WR_ERR--RTC Write Error Indicator 1 = An error has occurred in the contents of the time registers. 0 = No error in the contents of the time registers. Any illegal combination in the time registers sets this bit, e.g., seconds greater than 59, hours greater than 23, non-BCD data, or day exceeding the maximum for the month selected. ALARM--RTC Alarm Indicator 1 = Alarm has occurred. In alarm indicator latched mode, this bit remains set until AIE/C is cleared. In alarm indicator pulsed mode, this bit clears on reading the RCR. 0 = No alarm condition. ERRMK--RTC Write Error Mask 1 = Enables the interrupt output from the WR_ERR indicator.Masks the interrupt output from the WR_ERR indicator. 0 = Masks the interrupt output from the WR_ERR indicator. ROS1, ROS0--RTC Output Select 00 = Alarm indicator latched. RTCOUT is asserted high when the alarm register matches the time, and negated low by clearing the AIE/C bit. 01 = Alarm indicator pulsed. RTCOUT is asserted high when the alarm register matches the time, and negated low one RTC clock (30.5 S) later. RTCOUT can also be negated by clearing the AIE/C bit. 10 = Square wave. RTCOUT drives a 1.024 KHz square wave (RTC clock / 32) 11 = Alarm indicator latched inverted. RTCOUT is asserted low when the alarm register matches the time, and negated high by clearing the AIE/C bit. AIE/C--Alarm Indicator Enable/Clear 1 = Alarm indicator bit can assert 0 = Alarm indicator bit cannot assert. Clearing this bit clears the alarm condition and negates RTCOUT if programmed as an alarm indicator. RCK_HT--RTC Clock Halt 1 = RTC clock is stopped 0 = RTC clock runs.
4-40 MC68341 USER'S MANUAL MOTOROLA
SET--RTC Initialization 1 = Update cycles are inhibited so that time and calendar bytes can be written without an update occurring. 0 = Update cycle functions normally.
4.4.3 RTC Calibration Control Register (RCCR)
The RCCR contains the calibration data and sign bit for the RTC, used to compensate for crystal frequency error. The calibration circuits add or subtract counts at the divide-by-128 stage in the oscillator divide circuit. Positive value adds counts and speeds up the clock; negative values subtract counts and slow the clock down. RCCR
7
0 RESET: U
$0CF
6 5
RCSN
4
RCD4
3
RCD3
2
RCD2
1
RCD1
0
RCD0
RDCLR
U
U
U
U
U
U
U
Supervisor Only RDCLR--RTC Divider Clear 1 = Clears 15-bit RTC clock divider used to generate the 1Hz seconds clock. 0 = Normal divider operation RCSN--RTC Calibration Sign Bit 1 = Positive calibration (adds to clock count) 0 = Negative calibration (subtracts from clock count) RCD4-RCD0--RTC Calibration Data This bit field contains the value (times 128 clock cycles) to be added to the clock count each hour. RCD4-RCD0--RTC Calibration Data This bit field contains the value (times 128 clock cycles) to be added to the clock count each hour. Valid range is 0 to 31 ($1F hex). Operation with values from $20-3F is undefined. At the start of each hour, the value in the calibration data field RCDx is loaded into a counter. If the count is non-zero, the first minute is either shortened or lengthened by 128 clocks (as indicated by the RCSN sign bit), and the count is decremented. This correction process is repeated each successive minute, until the count is exhausted. Each calibration step has the effect of adding or subtracting 128 oscillator cycles every 117,964,800 (32768Hz x 60 sec/min x 60 min/hr) oscillator cycles, or 1.085 PPM of adjustment per calibration step. The 31 steps positive and negative support a total crystal frequency adjustment range of 33.6 PPM.
MOTOROLA
MC68341 USER'S MANUAL
4-41
The following procedure may be used to calibrate the RTC: 1. Program the 1.024 kHz signal to be output on RTCOUT. a. Set Port C pIn assignment register PPARC bit 2 to a one to select RTCOUT. b. Set RCR bits 4:3 to 1:0 to select square wave output. 2. A 1.024 kHz signal can be observed on the RTCOUT pin. Any deviation from 1.024 kHz indicates the degree and direction of the oscillator error. Measure the RTCOUT frequency and use the following formula, substituting the measured frequency in Hz for M. COM is the resulting compensation value. M -1 1024 COM = 1.085 x 10-6 3. Round COM to the nearest integer. The RCSN sign bit should be zero if COM is positive, one if COM is negative. The RCDx data field should be set to the absolute value of COM, converted to hex. For example, if 1023.9834 Hz is measured on RTCOUT, COM would equal -14.9, or -15 after rounding. Since COM is negative, the RCSN bit should be one. Fifteen equals F hex, so the required RCCR value is 2F. The correctable RTCOUT frequency range is 1024.034 to 1023.966 Hz. The RTCOUT frequency is not affected by the current correction value programmed in the RCCR.
4.4.4 RTC Time of Day Registers
These registers contain the time of day in BCD format. MIN
7
0 RESET: U
$0C2
6
MIN6
5
MIN5
4
MIN4
3
MIN3
2
MIN2
1
MIN1
0
MIN0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write SEC
7
0 RESET: U
$0C3
6
SEC6
5
SEC5
4
SEC4
3
SEC3
2
SEC2
1
SEC1
0
SEC0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write
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MC68341 USER'S MANUAL
MOTOROLA
DATE
7
0 RESET: U
$0C4
6
0
5
DATE5
4
DATE4
3
DATE3
2
DATE2
1
DATE1
0
DATE0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write The date counter is a 6-bit BCD counter with a range of 1 to 31 decimal. The date counter and month counter compensate for leap years. HOUR
7
0 RESET: U
$0C5
6
0
5
HOUR5
4
HOUR4
3
HOUR3
2
HOUR2
1
HOUR1
0
HOUR0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write The hours counter is a 24-hour clock only. MONTH
7
0 RESET: U
$0C6
3
MNT3
6
0
5
0
4
MNT4
2
MNT2
1
MNT1
0
MNT0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write YEAR
7
YR7 RESET: U
$0C7
6
YR6
5
YR5
4
YR4
3
YR3
2
YR2
1
YR1
0
YR0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write DAY
7
0 RESET: U
$0C9
6
0
5
0
4
0
3
0
2
DOW2
1
DOW1
0
DOW0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write The day of the week counter is a 3-bit count-up counter with a range from 0 to 6. The user defines the set value and day-of-week definition for the counter.
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4.4.5 RTC ALARM Registers
These registers contain the time of day alarm registers. Bit 7 of each register is the mask bit for the register, described in Table 4-14. Setting the mask bit in a register makes its match a don't care. The alarm registers are written and read in the same format as the time of day registers. MINA
7
MX RESET: U
$0CA
6
MIN6
5
MIN5
4
MIN4
3
MIN3
2
MIN2
1
MIN1
0
MIN0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write SECA
7
SX RESET: U
$0CB
6
SEC6
5
SEC5
4
SEC4
3
SEC3
2
SEC2
1
SEC1
0
SEC0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write DATEA
7
DX RESET: U
$0CC
6
0
5
DATE5
4
DATE4
3
DATE3
2
DATE2
1
DATE1
0
DATE0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write HOURA
7
HX RESET: U
$0CD
5
HOUR5
6
0
4
HOUR4
3
HOUR3
2
HOUR2
1
HOUR1
0
HOUR0
U
U
U
U
U
U
U
User--Read Only Supervisor--Read and Write
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Table 4-14 Alarm Bit Setting
SECA 1 0 0 0 0 MINA 1 1 0 0 0 HOURA 1 1 1 0 0 DATEA 1 1 1 1 0 Alarm Activated Alarm once per second Alarm when seconds match Alarm when minutes and seconds match Alarm when hours, minutes and seconds match Alarm when date, hours, minutes and seconds match
4.4.6 RTC Power Up Operation
Figure 4-9 is a timing diagram of the power up operation, showing the relationships between RESET, V CC, CLKOUT, and BSW. BSW is sampled as an asynchronous input by CLKOUT. After V CC has reached the minimum spec operating voltage, BSW and RESET must remain asserted for at least four system clock cycles before B S W is negated. Negation of BSW switches the RTC and oscillator power connection from VBATT to either VCCSYN (in crystal mode) or to V CC (in external clock mode). BSW should not remain asserted for extended periods of time when V CC voltage is at or above VBATT .
CLKOUT
VCC BSW RESET
VCC MIN
Figure 4-9. Power-Up Reset Timing
4.4.7 RTC Power Down Operation
Figure 4-10 is a timing diagram of the power down operation, showing the relationships between VCC, CLKOUT, and BSW. BSW must be asserted at least three system clock cycles before VCC has reached the minimum spec operating voltage.
CLKOUT VCC BSW
V CC MIN
Figure 4-10. Power-Down Timing
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4.5 MC68340 INITIALIZATION SEQUENCE
The following paragraphs discuss a suggested method for initializing the MC68341 after power-up.
4.5.1 Startup
RESET is asserted by the MC68341 during the time in which VCC is ramping up, the VCO is locking onto the frequency, and the MC68341 is going through the reset operation. After RESET is negated, four bus cycles are run, with global CS0 being asserted to fetch the 32-bit supervisor stack pointer (SSP) and the 32-bit program counter (PC) from the boot ROM. Until programmed, CS0 is a global, 16-bit port, six-wait-state chip select. CS0 can be programmed to continue decode for a range of addresses after the V-bit is set, provided the desired address range is first loaded into the CS0 base address register. After the V-bit is set for CS0 , global chip select can only be restarted with a system reset. After the SSP and the PC are fetched, the module base address register (MBAR) should be initialized, and the MBAR V-bit should be set (CPU space address $0003FF00) with the desired base address for the internal modules.
4.5.2 SIM41 Module Configuration
The order of the following SIM41 register initializations is not important; however, time can be saved by initializing the SYNCR first to quickly increase to the desired processor operating frequency. The module base address register must be initialized prior to any of following steps. Clock Synthesizer Control Register (SYNCR): * Set frequency control bits (W, X, Y, Z) to specify frequency. * Select action taken during loss of crystal (RSTEN bit): activate a system reset or operate in limp mode. * Select system clock and CLKOUT during LPSTOP (STSIM and STEXT bits). Module Configuration Register (MCR) * If using the software watchdog, periodic interrupt timer, and/or the bus monitor, select action taken when FREEZE is asserted (FRZx bits). * Select AVEC/CS0 configuration (AVEC bit). * Select the access privilege for the supervisor/user registers (SUPV bit). * Select the interrupt arbitration level for the SIM41 (IARBx bits). Autovector Register (AVR) * Select the desired external interrupt levels for internal autovectoring.
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System Protection Control Register (SYPCR) (Note that this register can only be written once after reset.) * Enable the software watchdog, if desired (SWE bit). * If the watchdog is enabled, select whether a system reset or a level 7 interrupt is desired at timeout (SWRI bit). * If the watchdog is enabled, select the timeout period (SWTx bits). * Enable the double bus fault monitor, if desired (DBFE bit). * Enable the external bus monitor, if desired (BME bit). * Select timeout period for bus monitor (BMTx bits). Software Watchdog Interrupt Vector Register (SWIV) * If using the software watchdog, program the vector number for a software watchdog interrupt. Periodic Interrupt Timer Register (PITR) * If using the software watchdog, select whether or not to prescale (SWP bit). * If using the periodic interrupt timer, select whether or not to prescale (PTP bit). * Program the count value for the periodic timer, or program a zero value to turn off the periodic timer (PITRx bits). Periodic Interrupt Control Register (PICR) * If using the periodic timer, program the desired interrupt level for the periodic interrupt timer (PIRQLx bits). * If using the periodic timer, program the vector number for a periodic timer interrupt. Chip Select Base Address and Address Mask Registers * Initialize and set the V-bits in the necessary chip select base address and address mask registers. Following this step, other system resources requiring the CS signals can be accessed. Care must be exercised when changing the address for CS0 . The address of the instruction following the MOVE instruction to the CS0 base address register must match the value of the PC at that time. CS0 must be taken out of global chip select mode by setting the V-bit in the base address register before CS7 -CS1 can be used. Port A and B Registers * Program the desired function of the port A signals (PPARA1 and PPARA2 registers). * Program the desired function of the port B signals (PPARB register).
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4.5.3 SIM41 Example Configuration Code
The following code is an example configuration sequence for the SIM41 module.
*************************************************************************** * MC68341 basic SIM41 register initialization example code: * This code is used to initialize the MC68341's internal SIM41 registers, * providing basic functions for operation. * It includes chip select programming for external devices. * This code would be programmed beginning at offset $0 into ROM which is * relocated to address $60000 by the initialization code. * The SSP_VEC and RST_VEC vectors used to initialize the system stack * pointer and initial PC, respectively, are located at offset $0 after * reset. *************************************************************************** * equates *************************************************************************** SSP_INIT EQU $10000 Stack pointer initial value - top of RAM MBAR EQU $0003FF00 Address of Module Base Address Reg. MODBASE EQU $FFFFF000 Default Module Base address value **************************************** * SIM41 register offsets from MBAR base address MCR EQU $00 SYNCR EQU $04 SYPCR EQU $21 CSAM0 EQU $40 *************************************************************************** * Reset vectors * These two vectors should be located at offset $0 in the boot ROM. *************************************************************************** ORG $60000 SSP_VEC DC.L SSP_INIT Supervisor stack pointer - initial value RST_VEC DC.L INIT340 Reset vector pointing to init code *************************************************************************** * Initialization code *************************************************************************** INIT340 MOVE.W #$2700,SR Init SR - interrupts masked *************************************************************************** * Set up default module base address value MOVEQ.L #7,D0 MBAR is in CPU space MOVEC.L D0,DFC Load DFC to indicate CPU space MOVE.L #MODBASE+$1BB,D0 Allow DMA, supervisor/user data accesses MOVES.L D0,MBAR Write to MBAR ***************************************************************************
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* Set up system protection register: * Software watchdog disabled, double bus fault monitor disabled, bus * monitor BERR after 128 clocks. MOVE.B #6,SYPCR+MODBASE *************************************************************************** * Clock synthesizer control register: * Switch from 8.3 to 16.7 MHZ MOVE.W #$7F80,SYNCR+MODBASE X-bit doubles the default speed *************************************************************************** * Module configuration register: * When FREEZE is asserted, software watchdog and periodic interrupt timer * are disabled, bus monitor is enabled. Show Cycles enabled, external * arbitration enabled. Supervisor/user SIM registers unrestricted, * Interrupt Arbitration at priority $F MOVE.W #$420F,MCR+MODBASE *************************************************************************** * Set up address masks and base addresses for the first 4 chip selects: LEA CSAM0+MODBASE,A0 Point to CS0 addr. mask location. MOVEQ #8-1,D0 Set up loop counter for 2 regs * 4 CSx LEA CSAM0$,A1 Point to init table location. LOOP MOVE.L (A1)+,(A0)+ Init. addr mask and base addr reg DBRA D0,LOOP *************************************************************************** * Data table for chip select initialization *************************************************************************** * CS0 - EPROM - 00060000-0007ffff, 3-wait states, 16-bit, write protect, NCS CSAM0$ DC.L $0001FFFD CSBAR0$ DC.L $0006000B * CS1 - RAM - 00000000-0000ffff, fast termination, NCS CSAM1$ DC.L $0000FFFC CSBAR1$ DC.L $00000007 * CS2 - external device - 00FFE8xx, external termination, NCS CSAM2$ DC.L $000000F3 CSBAR2$ DC.L $00FFE803 * CS3 - secondary memory - 00000000-0003ffff, 1-wait state, 8-bit, NCS CSAM3$ DC.L $0003FFF6 CSBAR3$ DC.L $00000003 * CS4-8 unused. Reset invalidates these registers, so initialization * is not specifically required CS4$ DC.L $0,$0 CS5$ DC.L $0,$0 CS6$ DC.L $0,$0 CS7$ DC.L $0,$0 *************************************************************************** END
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SECTION 5 CPU32
The CPU32, the first-generation instruction processing module of the M68300 family, is based on the industry-standard MC68000 core processor. It has many features of the MC68010 and MC68020 as well as unique features suited for high-performance processor applications. The CPU32 provides a significant performance increase over the MC68000 CPU, yet maintains source-code and binary-code compatibility with the M68000 family.
5.1 OVERVIEW
The CPU32 is designed to interface to the intermodule bus (IMB), allowing interaction with other IMB submodules. In this manner, integrated processors can be developed that contain useful peripherals on chip. This integration provides high-speed accesses among the IMB submodules, increasing system performance. Another advantage of the CPU32 is low power consumption. The CPU32 is implemented in high-speed complementary metal-oxide semiconductor (HCMOS) technology, providing low power use during normal operation. During periods of inactivity, the low-power stop (LPSTOP) instruction can be executed, shutting down the CPU32 and other IMB modules, greatly reducing power consumption. Ease of programming is an important consideration when using an integrated processor. The CPU32 instruction format reflects a predominant register-memory interaction philosophy. All data resources are available to operations that require them. The programming model includes eight multifunction data registers and seven general-purpose addressing registers. The data registers support 8-bit (byte), 16-bit (word), and 32-bit (long-word) operand lengths for all operations. Address manipulation is supported by word and long-word operations. Although the program counter (PC) and stack pointers (SP) are special-purpose registers, they are also available for most data addressing activities. Ease of program checking and diagnosis is enhanced by trace and trap capabilities at the instruction level. As processor applications become more complex and programs become larger, high-level languages (HLLs) will become the system designer's choice in programming languages. HLLs aid in the rapid development of complex algorithms with less error and are readily portable. The CPU32 instruction set efficiently supports HLLs.
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5.1.1 Features
Features of the CPU32 are as follows: * Fully Upward Object-Code Compatible with M68000 Family * Virtual Memory Implementation * Loop Mode of Instruction Execution * Fast Multiply, Divide, and Shift Instructions * Fast Bus Interface with Dynamic Bus Port Sizing * Improved Exception Handling for Embedded Control Applications * Additional Addressing Modes -- Scaled Index -- Address Register Indirect with Base Displacement and Index -- Expanded PC Relative Modes -- 32-Bit Branch Displacements * Instruction Set Additions -- High-Precision Multiply and Divide -- Trap on Condition Codes -- Upper and Lower Bounds Checking * Enhanced Breakpoint Instruction * Trace on Change of Flow * Table Lookup and Interpolate (TBL) Instruction * LPSTOP Instruction * Hardware BKPT Signal, Background Mode * Fully Static Implementation A block diagram of the CPU32 is shown in Figure 5-1. The major blocks depicted operate in a highly independent fashion that maximizes concurrences of operation while managing the essential synchronization of instruction execution and bus operation. The bus controller loads instructions from the data bus into the decode unit. The sequencer and control unit provide overall chip control by managing the internal buses, registers, and functions of the execution unit.
5.1.2 Virtual Memory
A system that supports virtual memory has a limited amount of high-speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device. When the processor attempts to access a location in the virtual memory map that is not resident in physical memory, a page fault occurs. The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. The
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CPU32 uses instruction restart, which requires that only a small portion of the internal machine state be saved. After correcting the page fault, the machine state is restored, and the instruction is refetched and restarted. This process is completely transparent to the application program.
SEQUENCER CONTROL UNIT INSTRUCTION PREFETCH AND DECODE
DATA BUS
16 EXECUTION UNIT 32
BUS CONTROL
BUS CONTROL
ADDRESS BUS
Figure 5-1. CPU32 Block Diagram
5.1.3 Loop Mode Instruction Execution
The CPU32 has several features that provide efficient execution of program loops. One of these features is the DBcc looping primitive instruction. To increase the performance of the CPU32, a loop mode has been added to the processor. The loop mode is used by any single-word instruction that does not change the program flow. Loop mode is implemented in conjunction with the DBcc instruction. Figure 5-2 shows the required form of an instruction loop for the processor to enter loop mode.
ONE-WORD INSTRUCTION
DBcc DBcc DISPLACEMENT $FFFC = 4
Figure 5-2. Loop Mode Instruction Sequence The loop mode is entered when the DBcc instruction is executed and the loop displacement is -4. Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches. The termination
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condition and count are checked after each execution of the data operations of the looped instruction. The CPU32 automatically exits the loop mode during interrupts or other exceptions.
5.1.4 Vector Base Register
The vector base register (VBR) contains the base address of the 1024-byte exception vector table, which consists of 256 exception vectors. Exception vectors contain the memory addresses of routines that begin execution at the completion of exception processing. These routines perform a series of operations appropriate for the corresponding exceptions. Because the exception vectors contain memory addresses, each consists of one long word, except the reset vector. The reset vector consists of two long words: the address used to initialize the supervisor stack pointer (SSP) and the address used to initialize the PC. The address of an interrupt exception vector is derived from an 8-bit vector number and the VBR. The vector numbers for some exceptions are obtained from an external device; other numbers are supplied automatically by the processor. The processor multiplies the vector number by 4 to calculate the vector offset, which is added to the VBR. The sum is the memory address of the vector. All exception vectors are located in supervisor data space, except the reset vector, which is located in supervisor program space. Only the initial reset vector is fixed in the processor's memory map; once initialization is complete, there are no fixed assignments. Since the VBR provides the base address of the vector table, the vector table can be located anywhere in memory; it can even be dynamically relocated for each task that is executed by an operating system. Refer to 5.5 Exception Processing for additional details.
31 VECTOR BASE REGISTER (VBR) 0
5.1.5 Exception Handling
The processing of an exception occurs in four steps, with variations for different exception causes. During the first step, a temporary internal copy of the status register (SR) is made, and the SR is set for exception processing. During the second step, the exception vector is determined. During the third step, the current processor context is saved. During the fourth step, a new context is obtained, and the processor then proceeds with instruction processing. Exception processing saves the most volatile portion of the current context by pushing it on the supervisor stack. This context is organized in a format called the exception stack frame. This information always includes the SR and PC context of the processor when the exception occurred. To support generic handlers, the processor places the vector offset in the exception stack frame. The processor also marks the frame with a frame format. The format field allows the return-from-exception (RTE) instruction to identify what information is on the stack so that it may be properly restored.
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5.1.6 Addressing Modes
Addressing in the CPU32 is register oriented. Most instructions allow the results of the specified operation to be placed either in a register or directly in memory; this flexibility eliminates the need for extra instructions to store register contents in memory. The seven basic addressing modes are as follows: * Register Direct * Register Indirect * Register Indirect with Index * Program Counter Indirect with Displacement * Program Counter Indirect with Index * Absolute * Immediate Included in the register indirect addressing modes are the capabilities to postincrement, predecrement, and offset. The PC relative mode also has index and offset capabilities. In addition to these addressing modes, many instructions implicitly specify the use of the SR, SP and/or PC. Addressing is explained fully in the M68000PM/AD, M68000 Family Programmer's Reference Manual.
5.2 ARCHITECTURE SUMMARY
The CPU32 is upward source- and object-code compatible with the MC68000 and MC68010. It is downward source- and object-code compatible with the MC68020. Within the M68000 family, architectural differences are limited to the supervisory operating state. User state programs can be executed unchanged on upward-compatible devices. The major CPU32 features are as follows: * 32-Bit Internal Data Path and Arithmetic Hardware * 32-Bit Address Bus Supported by 32-Bit Calculations * Rich Instruction Set * Eight 32-Bit General-Purpose Data Registers * Seven 32-Bit General-Purpose Address Registers * Separate User and Supervisor Stack Pointers (USP and SSP) * Separate User and Supervisor Address Spaces * Separate Program and Data Address Spaces * Many Data Types * Flexible Addressing Modes * Full Interrupt Processing * Expansion Capability
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5.2.1 Programming Model
The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels. User programs can only use the registers of the user model. The supervisor programming model, which supplements the user programming model, is used by CPU32 system programmers who wish to protect sensitive operating system functions. The supervisor model is identical to that of MC68010 and later processors. The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit PC, separate 32-bit SSP and USP, a 16-bit SR, two alternate function code registers, and a 32-bit VBR (see Figures 5-3 and 5-4).
31 16 15 87 0 D0 D1 D2 D3 D4 D5 D6 D7 31 16 15 DATA REGISTERS
0 A0 A1 A2 A3 A4 A5 A6 ADDRESS REGISTERS
31
16 15
0 A7 (USP) USER STACK POINTER
31
0 PC 15 87 0 CCR CONDITION CODE REGISTER PROGRAM COUNTER
Figure 5-3. User Programming Model
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31
16 15
0 A7 (SSP) 87 (CCR) 0 SR 0 VBR
SUPERVISOR STACK POINTER
STATUS REGISTER VECTOR BASE REGISTER ALTERNATE FUNCTION CODE REGISTERS
31
31
32
0 SFC DFC
Figure 5-4. Supervisor Programming Model Supplement
5.2.2 Registers
Registers D7-D0 are used as data registers for bit, byte (8-bit), word (16-bit), long-word (32-bit), and quad-word (64-bit) operations. Registers A6 to A0 and the USP and SSP are address registers that may be used as software SPs or base address registers. Register A7 (shown as A7 and A7' in Figures 5-3 and 5-4) is a register designation that applies to the USP in the user privilege level and to the SSP in the supervisor privilege level. In addition, address registers may be used for word and long-word operations. All 16 general-purpose registers (D7-D0, A7-A0) may be used as index registers. The PC contains the address of the next instruction to be executed by the CPU32. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate. The SR (see Figure 5-5) contains condition codes, an interrupt priority mask (three bits), and three control bits. Condition codes reflect the results of a previous operation. The codes are contained in the low byte (CCR) of the SR. The interrupt priority mask determines the level of priority an interrupt must have to be acknowledged. The control bits determine trace mode and privilege level. At user privilege level, only the CCR is available. At supervisor privilege level, software can access the full SR. The VBR contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. Alternate source and destination function code registers (SFC and DFC) contain 3-bit function codes. The CPU32 generates a function code each time it accesses an address. Specific codes are assigned to each type of access. The codes can be used to select eight dedicated 4-Gbyte address spaces. The MOVEC instruction can use registers SFC and DFC to specify the function code of a memory address.
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SYSTEM BYTE 15 T1 14 T0 13 S 12 0 11 0 10 I2 9 I1 8 I0 7 0 6 0
USER BYTE (CONDITION CODE REGISTER) 5 0 4 X EXTEND NEGATIVE 3 N 2 Z 1 V 0 C
TRACE ENABLE
INTERRUPT PRIORITY MASK
SUPERVISOR/USER STATE
ZERO OVERFLOW CARRY
Figure 5-5. Status Register
5.3 INSTRUCTION SET
The following paragaphs describe the CPU32 instruction set. A description of the instruction format, the operands used by the instructions, and a summary of the instructions by category are included. Complete programming information is provided in the M68000PM/AD, M68000 Family Programmer's Reference Manual. The CPU32 instructions include machine functions for all the following operations: * Data Movement * Arithmetic Operations * Logical Operations * Shifts and Rotates * Bit Manipulation * Conditionals and Branches * System Control The large instruction set encompasses a complete range of capabilities and, combined with the enhanced addressing modes, provides a flexible base for program development. The instruction set of the CPU32 is very similar to that of the MC68020 (see Table 5-1). The following M68020 instructions are not implemented on the CPU32: BFxxx -- Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST) -- Compare and Set (Read-Modify-Write Instructions) -- Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc)
CALLM, RTM -- Call Module, Return Module CAS, CAS2 cpxxx
PACK, UNPK -- Pack, Unpack BCD Instructions
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The CPU32 traps on unimplemented instructions or illegal effective addressing modes, allowing user-supplied code to emulate unimplemented capabilities or to define specialpurpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements. Table 5-1. Instruction Set
Mnemonic ABCD ADD ADDA ADDI ADDQ AND ANDI ASL ASR Bcc BCHG BCLR BGND BKPT BRA BSET BSR BTST CHK CHK2 CLR CMP CMPA CMPI CMPM CMP2 DBcc DIVS, DIVSL DIVU, DIVUL EOR EORI EXG EXT, EXTB ILLEGAL JMP JSR LEA LINK LPSTOP LSL, LSR MOVE Description Add Decimal with Extend Add Add Address Add Immediate Add Quick Logical AND Logical AND Immediate Arithmetic Shift Left Arithmetic Shift Right Branch Conditionally (16 Tests) Bit Test and Change Bit Test and Clear Enter Background Mode Breakpoint Branch Always Bit Test and Set Branch to Subroutine Bit Test Check Register against Bounds Check Register against Upper and Lower Bounds Clear Operand Compare Compare Address Compare Immediate Compare Memory Compare Register against Upper and Lower Bounds Test Condition, Decrement and Branch (16 Tests) Signed Divide Unsigned Divide Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend Take Illegal Instruction Trap Jump Jump to Subroutine Load Effective Address Link and Allocate Low-Power Stop Logical Shift Left and Right Move Mnemonic MOVEA MOVE CCR MOVE SR MOVE USP MOVEC MOVEM MOVEP MOVEQ MOVES MULS MULU NBCD NEG NEGX NOP NOT OR ORI PEA RESET ROL, ROR ROXL, ROXR RTD RTE RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TBLS, TBLSN Description Move Address Move Condition Code Register Move to/from Status Register Move User Stack Pointer Move Control Register Move Multiple Registers Move Peripheral Data Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend No Operation Ones Complement Logical Inclusive OR Logical Inclusive OR Immediate Push Effective Address Reset External Devices Rotate Left and Right Rotate with Extend Left and Right Return and Deallocate Return from Exception Return and Restore Return from Subroutine Subtract Decimal with Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Data Register Halves Test and Set Operand Table Lookup and Interpolate, Signed TBLU, TBLUN Table Lookup and Interpolate, Unsigned TRAPcc Trap Conditionally (16 Tests) TRAPV Trap on Overflow TST Test UNLK Unlink
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5.3.1 M68000 Family Compatibility
It is the philosophy of the M68000 Family that all user-mode programs should execute unchanged on a more advanced processor and that supervisor-mode programs and exception handlers should require only minimal alteration. The CPU32 can be thought of as an intermediate member of the M68000 family. Object code from an MC68000 or MC68010 may be executed on the CPU32, and many of the instruction and addressing mode extensions of the MC68020 are also supported. 5.3.1.1 NEW INSTRUCTIONS. Two instructions have been added to the M68000 instruction set for use in embedded control applications: LPSTOP and table lookup and interpolation (TBL). 5.3.1.1.1 Low-Power Stop (LPSTOP). In applications where power consumption is a consideration, the CPU32 can force the device into a low-power standby mode when immediate processing is not required. The low-power mode is entered by executing the LPSTOP instruction. The processor remains in this mode until a user-specified or higher level interrupt or a reset occurs. 5.3.1.1.2 Table Lookup and Interpolate (TBL). To maximize throughput for real-time applications, reference data is often precalculated and stored in memory for quick access. The storage of sufficient data points can require an inordinate amount of memory. The TBL instruction uses linear interpolation to recover intermediate values from a sample of data points, thus conserving memory. When the TBL instruction is executed, the CPU32 looks up two table entries bounding the desired result and performs a linear interpolation between them. Byte, word, and longword operand sizes are supported. The result can be rounded according to a round-tonearest algorithm or returned unrounded along with the fractional portion of the calculated result (byte and word results only). This extra precision can be used to reduce cumulative error in complex calculations. See 5.3.4 Using the TBL Instructions for examples. 5.3.1.2 UNIMPLEMENTED INSTRUCTIONS. The ability to trap on unimplemented instructions allows user-supplied code to emulate unimplemented capabilities or to define special-purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 enhancements. See 5.5.2.8 Illegal or Unimplemented Instructions for more details.
5.3.2 Instruction Format and Notation
All instructions consist of at least one word. Some instructions can have as many as seven words, as shown in Figure 5-6. The first word of the instruction, called the operation word, specifies instruction length and the operation to be performed. The remaining words, called extension words, further specify the instruction and operands. These words may be immediate operands, extensions to the effective address mode specified in the operation word, branch displacements, bit number, special register specifications, trap operands, or argument counts.
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0
OPERATION WORD (ONE WORD, SPECIFIES OPERATION AND MODES) SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS) IMMEDIATE OPERAND OR SOURCE ADDRESS EXTENSION (IF ANY, ONE TO THREE WORDS) DESTINATION EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO THREE WORDS)
Figure 5-6. Instruction Word General Format Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instructions specify an operand location in one of three ways: * Register Specification * Effective Address * Implicit Reference A register field of the instruction contains the number of the register. An effective address field of the instruction contains address mode information. The definition of an instruction implies the use of specific registers.
The register field within an instruction specifies the register to be used. Other fields within the instruction specify whether the register is an address or data register and how it is to be used. The M68000PM/AD, M68000 Family Programmer's Reference Manual, contains detailed register information. Except where noted, the following notation is used in this section: Data Immediate data from an instruction Destination Destination contents Source Source contents Vector Location of exception vector An Any address register (A7-A0) Ax, Ay Address registers used in computation Dn Any data register (D7-D0) Rc Control register (VBR, SFC, DFC) Rn Any address or data register Dh, Dl Data registers, high- and low-order 32 bits of product Dr, Dq Data registers, division remainder, division quotient Dx, Dy Data registers, used in computation Dym, Dyn Data registers, table interpolation values Xn Index register [An] Address extension
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cc d# ea #data label list [...] (...) CCR
PC SP SR SSP USP FC DFC SFC + - / x = > < V ~
Condition code Displacement Example: d16 is a 16-bit displacement Effective address Immediate data; a literal integer Assembly program label List of registers Example: D3-D0 Bits of an operand Examples: [7] is bit 7; [31:24] are bits 31-24 Contents of a referenced location Example: (Rn) refers to the contents of Rn Condition code register (lower byte of SR) X--extend bit N--negative bit Z--zero bit V--overflow bit C--carry bit Program counter Active stack pointer Status register Supervisor stack pointer User stack pointer Function code Destination function code register Source function code register Arithmetic addition or postincrement Arithmetic subtraction or predecrement Arithmetic division or conjunction symbol Arithmetic multiplication Equal to Not equal to Greater than Greater than or equal to Less than Less than or equal to Logical AND Logical OR Logical exclusive OR Invert; operand is logically complemented
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BCD LSW MSW {R/W}
Binary-coded decimal, indicated by subscript Example: Source10 is a BCD source operand. Least significant word Most significant word Read/write indicator
In a description of an operation, a destination operand is placed to the right of source operands and is indicated by an arrow ().
5.3.3 Instruction Summary
The instructions form a set of tools to perform the following operations: Data Movement Integer Arithmetic Logic Shift and Rotate Bit Manipulation Binary-Coded Decimal Arithmetic Program Control System Control
The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development. All CPU32 instructions are summarized in Table 5-2.
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Table 5-2. Instruction Set Summary
Opcode ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ANDI to CCR ANDI to SR Operation Source 10 + Destination10 + X Destination Source + Destination Destination Source + Destination Destination Immediate Data + Destination Destination Immediate Data + Destination Destination Source + Destination + X Destination Source Destination Destination Immediate Data Destination Destination Source CCR CCR If supervisor state the Source SR SR else TRAP Destination Shifted by count Destination Syntax ABCD Dy,Dx ABCD -(Ay),-(Ax) ADD ea,Dn ADD Dn,ea ADDA ea,An ADDI # data, ea ADDQ # data ,ea ADDX Dy,Dx ADDX -(Ay),-(Ax) AND ea, Dn AND Dn,ea ANDI #data, ea ANDI #data,CCR ANDI #data,SR
ASL,ASR
ASd Dx,Dy ASd # data ,Dy ASd ea Bcc label BCHG Dn,ea BCHG # data ,ea BCLR Dn, ea BCLR # data ,ea BGND
Bcc BCHG
If (condition true) then PC + d PC ~(number of Destination) Z; ~(number of Destination) bit number of Destination ~(number of Destination) Z; 0 bit number of Destination If (background mode enabled) then enter background mode else Format/Vector offset -(SSP) PC -(SSP) SR -(SSP) (Vector) PC Run breakpoint acknowledge cycle; TRAP as illegal instruction PC + d PC ~(number of Destination) Z; 1 bit number of Destination SP - 4 SP; PC (SP); PC + d PC - (number of Destination) Z; If Dn < 0 or Dn > Source then TRAP If Rn < lower bound or If Rn > upper bound then TRAP 0 Destination Destination -- Source cc Destination -- Source Destination -- Immediate Data Destination -- Source cc
BCLR BGND
BKPT BRA BSET BSR BTST CHK CHK2
BKPT # data BRA label BSET Dn, ea BSET # data, ea BSR label BTST Dn, ea BTST # data ,ea CHK ea,Dn CHK2 ea,Rn
CLR CMP CMPA CMPI CMPM
CLR ea CMP ea,Dn CMPA ea,An CMPI # data, ea CMPM (Ay)+,(Ax)+
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Table 5-2. Instruction Set Summary (Continued)
Opcode CMP2 Operation Compare Rn < lower-bound or Rn > upper-bound and Set Condition Codes If condition false then (Dn - 1 Dn; If Dn -1 then PC + d PC) Destination/Source Destination CMP2 ea,Rn Syntax
DBcc DIVS DIVSL
DBcc Dn, label DIVS.W ea,Dn DIVS.L ea,Dq DIVS.L ea,Dr:Dq DIVSL.L ea,Dr:Dq DIVU.W ea,Dn DIVU.L ea,Dq DIVU.L ea,Dr:Dq DIVUL.L ea,Dr:Dq EOR Dn, ea EORI # data ,ea EORI # data ,CCR EORI # data ,SR 32/16 16r:16q 32/32 32q 64/32 32r:32q 32/32 32r:32q 32/16 16r:16q 32/32 32q 64/32 32r:32q 32/32 32r:32q
DIVU DIVUL
Destination/Source Destination
EOR EORI EORI to CCR EORI to SR EXG
Source Destination Destination Immediate Data Destination Destination Source CCR CCR If supervisor state the Source SR SR else TRAP Rx Ry
EXG Dx,Dy EXG Ax,Ay EXG Dx,Ay EXG Ay,Dx EXT.W Dn EXT.L Dn EXTB.L Dn ILLEGAL extend byte to word extend word to long word extend byte to long word
EXT EXTB LLEGAL
Destination Sign-Extended Destination
SSP - 2 SSP; Vector Offset (SSP); SSP - 4 SSP; PC (SSP); SSp - 2 SSP; SR (SSP); Illegal Instruction Vector Address PC Destination Address PC SP - 4 SP; PC (SP) Destination Address PC ea An SP - 4 SP; An (SP) SP An, SP + d SP If supervisor state Immediate Data SR Interrupt Mask External Bus Interface (EBI) STOP else TRAP Destination Shifted by count Destination
JMP JSR LEA LINK LPSTOP
JMP ea JSR ea LEA ea,An LINK An,# displacement LPSTOP # data
LSL,LSR
LSd1 Dx,Dy LSd1 # data ,Dy LSd1 ea MOVE ea,ea MOVEA ea,An MOVE CCR, ea
MOVE MOVEA MOVE from CCR
Source Destination Source Destination CCR Destination
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Table 5-2. Instruction Set Summary (Continued)
Opcode MOVE to CCR MOVE from SR Source CCR If supervisor state then SR Destination else TRAP If supervisor state then Source SR else TRAP If supervisor state then USP An or An USP else TRAP If supervisor state then Rc Rn or Rn Rc else TRAP Registers Destination Source Registers Source Destination Immediate Data Destination If supervisor state then Rn Destination [DFC] or Source [SFC] Rn else TRAP Source x Destination Destination Operation MOVE SR, ea Syntax MOVE ea,CCR
MOVE to SR
MOVE ea,SR
MOVE USP
MOVE USP,An MOVE An,USP MOVEC Rc,Rn MOVEC Rn,Rc MOVEM register list, ea MOVEM ea,register list MOVEP Dx,(d,Ay) MOVEP (d,Ay),Dx MOVEQ # data,Dn MOVES Rn, ea MOVES ea,Rn
MOVEC
MOVEM MOVEP MOVEQ MOVES
MULS
MULS.W ea,Dn MULS.L ea,Dl MULS.L ea,Dh:Dl MULU.W ea,Dn MULU.L ea,Dl MULU.L ea,Dh:Dl NBCD ea NEG ea NEGX ea NOP NOT ea OR ea,Dn OR Dn, ea ORI # data ,ea ORI # data ,CCR ORI # data ,SR
16 x 16 32 32 x 32 32 32 x 32 64 16 x 16 32 32 x 32 32 32 x 32 64
MULU
Source x Destination Destination
NBCD NEG NEGX NOP NOT OR ORI ORI to CCR ORI to SR
0 - (Destination10) - X Destination 0 - (Destination) Destination 0 - (Destination) - X Destination None ~Destination Destination Source V Destination Destination Immediate Data V Destination Destination Source V CCR CCR If supervisor state then Source V SR SR else TRAP Sp - 4 SP; ea (SP) If supervisor state then Assert RESET else TRAP Destination Rotated by count Destination
PEA RESET
PEA ea RESET
ROL,ROR
ROd 1 Rx,Dy ROd 1 # data ,Dy ROd 1 ea
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Table 5-2. Instruction Set Summary (Concluded)
Opcode ROXL,ROXR Operation Syntax Destination Rotated with X by count Destination ROXd 1 Rx,Dy ROXd 1 # data ,Dy ROXd 1 ea (SP) PC; SP + 4 + d SP RTD # displacement If supervisor state RTE the (SP) SR; SP + 2 SP; (SP) PC; SP + 4 SP; restore state and deallocate stack according to (SP) else TRAP (SP) CCR; SP + 2 SP; (SP) PC; SP + 4 SP (SP) PC; SP + 4 SP Destination10 - Source 10 - X Destination If Condition True then 1s Destination else 0s Destination If supervisor state then Immediate Data SR; STOP else TRAP Destination - Source Destination Destination - Source Destination Destination - Immediate Data Destination Destination - Immediate Data Destination Destination - Source - X Destination Register [31:16] Register [15:0] Destination Tested Condition Codes; 1 bit 7 of Destination ENTRY(n) + {(ENTRY(n + 1) - ENTRY(n)) x Dx[7:0]} / 256 Dx ENTRY(n) x 256 + {(ENTRY(n + 1) - ENTRY(n)) x Dx [7:0]} Dx ENTRY(n) + {(ENTRY(n + 1) - ENTRY(n)) x Dx[7:0]} / 256 Dx ENTRY(n) x 256 + {(ENTRY(n + 1) - ENTRY(n)) x Dx[7:0]} Dx SSP - 2 SSP; Format/Offset (SSP); SSP - 4 SSP; PC (SSP); SSP - 2 SSP; SR (SSP); Vector Address PC If cc then TRAP RTR RTS SBCD Dx,Dy SBCD -(Ax),-(Ay) Scc ea
RTD RTE
RTR RTS SBCD Scc
STOP
STOP # data
SUB SUBA SUBI SUBQ SUBX SWAP TAS TBLS TBLSN TBLU TBLUN TRAP
SUB ea,Dn SUB Dn, ea SUBA ea,An SUBI # data ,ea SUBQ # data,ea SUBX Dx,Dy SUBX -(Ax),-(Ay) SWAP Dn TAS ea TBLS.size ea, Dx TBLS.size Dym:Dyn, Dx TBLSN. size ea,Dx TBLSN. size Dym:Dyn, Dx TBLU. size ea,Dx TBLU. size Dym:Dyn, Dx TBLUN. size ea,Dx TBLUN. size Dym:Dyn,Dx TRAP # vector
TRAPcc
TRAPcc TRAPcc.W # data TRAPcc.L # data TRAPV TST ea UNLK An
TRAPV TST
If V then TRAP Destination Tested Condition Codes
UNLK An SP; (SP) An; SP + 4 SP NOTE 1: d is direction, L or R.
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5.3.3.1 CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that indicate the result of a processor operation. Table 5-3 lists the effect of each instruction on these bits. The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them. Refer to Table 5-7 as an example. Table 5-3. Condition Code Computations
Operations ABCD ADD, ADDI, ADDQ ADDX X * * * N U * * Z ? * ? V U ? ? C ? ? ? Special Definition C = Decimal Carry Z = Z R ... R0 V = Sm Dm R V S D Rm C = Sm Dm V R Dm V Sm R V = Sm Dm R V S D Rm C = Sm Dm V R Dm V Sm R Z = Z R ... R0
AND, ANDI, EOR, EORI, MOVEQ, MOVE, OR, ORI, CLR, EXT, NOT, TAS, TST CHK CHK2, CMP2
--
*
*
0
0
-- --
* U
U ?
U U
U ? Z = (R = LB) V (R = UB) C = (LB < UB) (IR < LB) V (R > UB) V (UB < LB) (R > UB) (R < LB) V = S Dm R V Sm D Rm C = Sm D V Rm D V Sm Rm V = S Dm R V Sm D Rm C = Sm D V Rm D V Sm Rm Z = Z R ... R0 V = S Dm R V Sm D Rm C = Sm D V Rm D V Sm Rm V = Division Overflow V = Multiplication Overflow C = Decimal Borrow Z = Z R ... R0 V = Dm Rm C = Dm V Rm V = Dm Rm C = Dm V Rm Z = Z R ... R0 V = Dm (Dm - 1 V ... V Dm - r ) V D (Dm - 1 V ... + Dm - r) C = Dm - r + 1 C = Dm - r + 1 C=X C = Dm - r + 1 C = Dr - 1 C=X
SUB, SUBI, SUBQ SUBX
* *
* *
* ?
? ?
? ?
CMP, CMPI, CMPM DIVS, DIVU MULS, MULU SBCD, NBCD NEG NEGX
-- -- -- * * *
* * * U * *
* * * ? * ?
? ? ? U ? ?
? 0 0 ? ? ?
ASL
*
*
*
?
?
ASL (r = 0) LSL, ROXL LSR (r = 0) ROXL (r = 0) ROL ROL (r = 0) ASR, LSR, ROXR ASR, LSR (r = 0) ROXR (r = 0)
-- * -- -- -- -- * -- --
* * * * * * * * *
* * * * * * * * *
0 0 0 0 0 0 0 0 0
0 ? 0 ? ? 0 ? 0 ?
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Table 5-3. Condition Code Computations (Continued)
Operations ROR ROR (r = 0) -- U ? X N Z V = = = = = = = = = Not affected Undefined See special definition General case C Rm Rm ... R0 Boolean AND Boolean OR X -- -- N Z V 0 0 C ? 0 Sm Dm Rm R n r LB UB Rm = = = = = = = = = Source operand MSB Destination operand MSB Result operand MSB Register tested Bit Number Shift count Lower bound Upper bound NOT Rm C = Dr - 1 Special Definition
NOTE : The following notations apply to this table only.
5.3.3.2 DATA MOVEMENT INSTRUCTIONS. The MOVE instruction is the basic means of transferring and storing address and data. MOVE instructions transfer byte, word, and long-word operands from memory to memory, memory to register, register to memory, and register to register. Address movement instructions (MOVE or MOVEA) transfer word and long-word operands and ensure that only valid address manipulations are executed. In addition to the general MOVE instructions, there are several special data movement instructions--move multiple registers (MOVEM), move peripheral data (MOVEP), move quick (MOVEQ), exchange registers (EXG), load effective address (LEA), push effective address (PEA), link stack (LINK), and unlink stack (UNLK). Table 5-4 is a summary of the data movement operations. Table 5-4. Data Movement Operations
Instruction EXG LEA LINK MOVE MOVEA MOVEM MOVEP Operand Syntax Rn, Rn ea, An An, #d ea, ea ea, An list, ea ea, list Dn, (d16, An) (d 16, An), Dn MOVEQ PEA UNLK #data, Dn ea An 8 32 32 32 Operand Size 32 32 16, 32 8, 16, 32 16, 32 32 16, 32 16, 32 32 16, 32 Rn Rn ea An SP - 4 SP, An (SP); SP An, SP + d SP Source Destination Source Destination Listed registers Destination Source Listed registers Dn [31:24] (An + d); Dn [23:16] (An + d + 2); Dn [15:8] (An + d + 4); Dn [7:0] (An + d + 6) (An + d) Dn [31:24]; (An + d + 2) Dn [23:16]; (An + d + 4) Dn [15:8]; (An + d + 6) Dn [7:0] Immediate Data Destination SP - 4 SP; ea SP An SP; (SP) An, SP + 4 SP Operation
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5.3.3.3 INTEGER ARITHMETIC OPERATIONS. The arithmetic operations include the four basic operations of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as arithmetic compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction set includes ADD, CMP, and SUB instructions for both address and data operations with all operand sizes valid for data operations. Address operands consist of 16 or 32 bits. The clear and negate instructions apply to all sizes of data operands. Signed and unsigned MUL and DIV instructions include: * Word multiply to produce a long-word product * Long-word multiply to produce a long-word or quad-word product * Division of a long-word dividend by a word divisor (word quotient and word remainder) * Division of a long-word or quad-word dividend by a long-word divisor (long-word quotient and long-word remainder) A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). Refer to Table 5-5 for a summary of the integer arithmetic operations.
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Table 5-5. Integer Arithmetic Operations
Instruction ADD ADDA ADDI ADDQ ADDX CLR CMP CMPA CMPI CMPM CMP2 DIVS/DIVU DIVSL/DIVUL EXT EXTB MULS/MULU Operand Syntax Dn, ea ea, Dn ea, An #data, ea #data, ea Dn, Dn - (An), - (An) ea ea, Dn ea, An #data, ea (An) +, (An) + ea, Rn ea, Dn ea, Dr:Dq ea, Dq ea, Dr:Dq Dn Dn Dn ea, Dn ea, Dl ea, Dh:Dl ea ea ea, Dn Dn, ea ea, An #data, ea #data, ea Dn, Dn - (An), - (An) ea, Dn Dym:Dyn, Dn ea, Dn Dym:Dyn, Dn Operand Size 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 32/16 16:16 64/32 32:32 32/32 32 32/32 32:32 8 16 16 32 8 32 16 x 16 32 32 x 32 32 32 x 32 64 8, 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 Operation Source + Destination Destination Source + Destination Destination Immediate Data + Destination Destination Immediate Data + Destination Destination Source + Destination + X Destination 0 Destination (Destination - Source), CCR shows results (Destination - Source), CCR shows results (Destination - Immediate Data), CCR shows results (Destination - Source), CCR shows results Lower bound Rn Upper Bound, CCR shows results Destination/Source Destination (signed or unsigned)
Sign Extended Destination Destination Sign Extended Destination Destination Source x Destination Destination (signed or unsigned) 0 - Destination Destination 0 - Destination - X Destination Destination - Source Destination Destination - Source Destination Destination - Immediate Data Destination Destination - Immediate Data Destination Destination - Source - X Destination Dyn - Dym Temp (Temp x Dn [7:0]) Temp (Dym x 256) + Temp Dn Dyn - Dym Temp (Temp x Dn [7:0]) / 256 Temp Dym + Temp Dn
NEG NEGX SUB SUBA SUBI SUBQ SUBX TBLS/TBLU
TBLSN/TBLUN
8, 16, 32
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5.3.3.4 LOGIC INSTRUCTIONS. The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes of immediate data. The test (TST) instruction arithmetically compares the operand with zero, placing the result in the CCR. Table 5-6 summarizes the logical operations. Table 5-6. Logic Operations
Instruction AND ANDI EOR EORI NOT OR ORI TST Operand Syntax ea, Dn Dn, ea #data, ea Dn, ea #data, ea ea ea, Dn Dn, ea #data, ea ea Operand Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 Operation Source Destination Destination Immediate Data Destination Destination Source Destination Destination Immediate Data Destination Destination Destination Destination Source V Destination Destination Immediate Data V Destination Destination Source - 0, to set condition codes
5.3.3.5 SHIFT AND ROTATE INSTRUCTIONS. The arithmetic shift instructions, ASR and ASL, and logical shift instructions, LSR and LSL, provide shift operations in both directions. The ROR, ROL, ROXR, and ROXL instructions perform rotate (circular shift) operations, with and without the extend bit. All shift and rotate operations can be performed on either registers or memory. Register shift and rotate operations shift all operand sizes. The shift count may be specified in the instruction operation word (to shift from 1 to 8 places) or in a register (modulo 64 shift count). Memory shift and rotate operations shift word-length operands one bit position only. The SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/rotate instructions is enhanced so that use of the ROR and ROL instructions with a shift count of eight allows fast byte swapping. Table 5-7 is a summary of the shift and rotate operations.
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Table 5-7. Shift and Rotate Operations
Instruction ASL Operand Syntax Dn, Dn #data, Dn ea Dn, Dn #data, Dn ea Dn, Dn #data, Dn ea Dn, Dn #data, Dn ea Dn, Dn #data, Dn ea Dn, Dn #data, Dn ea Dn, Dn #data, Dn ea Dn, Dn #data, Dn ea Dn Operand Size 8, 16, 32 8, 16, 32 16 8, 16, 32 8, 16, 32 16 8, 16, 32 8, 16, 32 16 8, 16, 32 8, 16, 32 16 8, 16, 32 8, 16, 32 16 8, 16, 32 8, 16, 32 16 8, 16, 32 8, 16, 32 16 8, 16, 32 8, 16, 32 16 16
MSW LSW C 0 X/C X/C
Operation
0
ASR
X/C
LSL
0
LSR
X/C
ROL
C
ROR
C
ROXL
X
ROXR
X
C
SWAP
5.3.3.6 BIT MANIPULATION INSTRUCTIONS. Bit manipulation operations are accomplished using the following instructions: bit test (BTST), bit test and set (BSET), bit test and clear (BCLR), and bit test and change (BCHG). All bit manipulation operations can be performed on either registers or memory. The bit number is specified as immediate data or in a data register. Register operands are 32 bits, and memory operands are 8 bits. Table 5-8 is a summary of bit manipulation instructions. Table 5-8. Bit Manipulation Operations
Instruction BCHG BCLR BSET BTST Operand Syntax Dn, ea #data, ea Dn, ea #data, ea Dn, ea #data, ea Dn, ea #data, ea Operand Size 8, 32 8, 32 8, 32 8, 32 8, 32 8, 32 8, 32 8, 32 Operation ~(bit number of destination) Z bit of destination ~(bit number of destination) Z; 0 bit of destination ~(bit number of destination) Z; 1 bit of destination ~( bit number of destination) Z
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5.3.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five instructions support operations on BCD numbers. The arithmetic operations on packed BCD numbers are add decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with extend (NBCD). Table 5-9 is a summary of the BCD operations. Table 5-9. Binary-Coded Decimal Operations
Instruction ABCD NBCD SBCD Operand Syntax Dn, Dn - (An), - (An) ea Dn, Dn - (An), - (An) Operand Size 8 8 8 8 8 8 Operation Source 10 + Destination10 + X Destination 0 - Destination10 - X Destination Destination10 - Source10 - X Destination
5.3.3.8 PROGRAM CONTROL INSTRUCTIONS. A set of subroutine call and return instructions and conditional and unconditional branch instructions perform program control operations. Table 5-10 summarizes these instructions. Table 5-10. Program Control Operations
Instruction Bcc DBcc Scc Operand Syntax label Dn , label ea Operand Size Conditional 8, 16, 32 16 8 If condition true, then PC + d PC If condition false, then Dn - 1 PC; if Dn (- 1), then PC + d PC If condition true, then destination bits are set to 1; else destination bits are cleared to 0 Unconditional BRA BSR JMP JSR NOP RTD RTR RTS label label ea ea none #d none none 8, 16, 32 8, 16, 32 none none none 16 none none PC + d PC SP - 4 SP; PC (SP); PC + d PC Destination PC SP - 4 SP; PC (SP); destination PC PC + 2 PC Returns (SP) PC; SP + 4 + d SP (SP) CCR; SP + 2 SP; (SP) PC; SP + 4 SP (SP) PC; SP + 4 SP Operation
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To specify conditions for change in program control, condition codes must be substituted for the letters "cc" in conditional program control opcodes. Condition test mnemonics are given below. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. CC -- CS -- EQ -- F -- GE -- GT -- HI -- LE -- Carry clear Carry set Equal False* Greater or equal Greater than High Less or equal LS -- LT -- MI -- NE -- PL -- T -- VC -- VS -- Low or same Less than Minus Not equal Plus True Overflow clear Overflow set
*Not applicable to the Bcc instruction 5.3.3.9 SYSTEM CONTROL INSTRUCTIONS. Privileged instructions, trapping instructions, and instructions that use or modify the CCR provide system control operations. All of these instructions cause the processor to flush the instruction pipeline. Table 5-11 summarizes the instructions. The preceding list of condition tests also applies to the TRAPcc instruction. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes.
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Table 5-11. System Control Operations
Instruction ANDI EORI MOVE MOVEA MOVEC MOVES ORI RESET RTE STOP LPSTOP Operand Syntax #data, SR #data, SR ea, SR SR, ea USP, An An, USP Rc, Rn Rn, Rc Rn, ea ea, Rn #data, SR none none #data #data Operand Size Privileged 16 16 16 16 32 32 32 32 8, 16, 32 16 none none 16 none Immediate Data SR SR Immediate Data SR SR Source SR SR Destination USP An An USP Rc Rn Rn Rc Rn Destination using DFC Source using SFC Rn Immediate Data V SR SR Assert RESET line (SP) SR; SP + 2 SP; (SP) PC; SP + 4 SP; restore stack according to format Immediate Data SR; STOP Immediate Data SR; interrupt mask EBI; STOP If breakpoint cycle acknowledged, then execute returned operation word, else trap as illegal instruction. If background mode enabled, then enter background mode, else format/vector offset - (SSP); PC - (SSP); SR - (SSP); (vector) PC If Dn < 0 or Dn < (ea), then CHK exception If Rn < lower bound or Rn > upper bound, then CHK exception SSP - 2 SSP; vector offset (SSP); SSP - 4 SSP; PC (SSP); SSP - 2 SSP; SR (SSP); llegal instruction vector address PC SSP - 2 SSP; format/vector offset (SSP); SSP - 4 SSP; PC (SSP); SR (SSP); vector address PC If cc true, then TRAP exception If V set, then overflow TRAP exception Immediate Data CCR CCR Immediate Data CCR CCR Source CCR CCR Destination Immediate Data V CCR CCR Operation
Trap Generating BKPT #data none
BGND
none
none
CHK CHK2 ILLEGAL
ea, Dn ea, Rn none
16, 32 8, 16, 32 none
TRAP
#data
none
TRAPcc TRAPV ANDI EORI MOVE ORI
none #data none #data, CCR #data, CCR ea, CCR CCR, ea #data, CCR
none 16, 32 none 8 8 16 16 8
Condition Code Register
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5.3.3.10 CONDITION TESTS. Conditional program control instructions and the TRAPcc instruction execute on the basis of condition tests. A condition test is the evaluation of a logical expression related to the state of the CCR bits. If the result is 1, the condition is true. If the result is 0, the condition is false. For example, the T condition is always true, and the EQ condition is true only if the Z-bit condition code is true. Table 5-12 lists each condition test. Table 5-12. Condition Tests
Mnemonic T F* HI LS CC CS NE EQ VC VS PL MI GE LT GT Condition True False High Low or Same Carry Clear Carry Set Not Equal Equal Overflow Clear Overflow Set Plus Minus Greater or Equal Less Than Greater Than Encoding 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Test 1 0
C*Z C+Z C
C
Z
Z
V
V
N
N N * V + N* V N * V+ N*V N * V * Z+ N * V * Z Z + N * V+ N * V
LE Less or Equal * Not available for the Bcc instruction. * = Boolean AND + = Boolean OR N = Boolean NOT
5.3.4 Using the TBL Instructions
There are four TBL instructions. TBLS returns a signed, rounded byte, word, or long-word result. TBLSN returns a signed, unrounded byte, word, or long-word result. TBLU returns an unsigned, rounded byte, word, or long-word result. TBLUN returns an unsigned, unrounded byte, word, or long-word result. All four instructions support two types of interpolation data: an n-element table stored in memory and a two-element range stored in a pair of data registers. The latter form provides a means of performing surface (3D) interpolation between two previously calculated linear interpolations. The following examples show how to compress tables and use fewer interpolation levels between table entries. Example 1 (see Figure 5-7) demonstrates TBL for a 257-entry table, allowing up to 256 interpolation levels between entries. Example 2 (see Figure 5-8) reduces table length for the same data to four entries. Example 3 (see Figure 5-9) demonstrates use of an 8-bit independent variable with an instruction.
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Two additional examples show how TBLSN can reduce cumulative error when multiple table lookup and interpolation operations are used in a calculation. Example 4 demonstrates addition of the results of three table interpolations. Example 5 illustrates use of TBLSN in surface interpolation. 5.3.4.1 TABLE EXAMPLE 1: STANDARD USAGE. The table consists of 257 word entries. As shown in Figure 5-7, the function is linear within the range 32768 X 49152. Table entries within this range are as given in Table 5-13 . Table 5-13. Standard Usage Entries
Entry Number 128* 162 163 164 165 X-Value 32768 41472 41728 41984 42240 Y-Value 1311 1659 1669 1679 1690
192* 49152 1966 *These values are the end points of the range. All entries between these points fall on the line.
Y
DEPENDENT VARIABLE
16384
32768
49152
65536
X
INDEPENDENT VARIABLE
Figure 5-7. Table Example 1
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The table instruction is executed with the following bit pattern in Dx:
31 NOT USED 16 15 1 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0
Table Entry Offset Dx [8:15] = $A3 = 163 Interpolation Fraction Dx [0:7] = $80 = 128 Using this information, the table instruction calculates dependent variable Y: Y = 1669 + (128 (1679 - 1669)) / 256 = 1674 5.3.4.2 TABLE EXAMPLE 2: COMPRESSED TABLE. In Example 2 (see Figure 5-8), the data from Example 1 has been compressed by limiting the maximum value of the independent variable. Instead of the range 0 X = 65535, X is limited to 0 X 1023. The table has been compressed to only five entries, but up to 256 levels of interpolation are allowed between entries.
Y
DEPENDENT VARIABLE
256
512
786
1024
X
INDEPENDENT VARIABLE
Figure 5-8. Table Example 2 NOTE Extreme table compression with many levels of interpolation is possible only with highly linear functions. The table entries within the range of interest are listed in Table 5-14.
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Table 5-14. Compressed Table Entries
Entry Number 2 3 X-Value 512 786 Y-Value 1311 1966
Since the table is reduced from 257 to 5 entries, independent variable X must be scaled appropriately. In this case the scaling factor is 64, and the scaling is done by a single instruction: LSR.W #6,Dx Thus, Dx now contains the following bit pattern:
31 NOT USED 16 15 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0
Table Entry Offset Dx [8:15] = $02 = 2 Interpolation Fraction Dx [0:7] = $8E = 142 Using this information, the table instruction calculates dependent variable Y: Y = 1331 + (142 (1966 - 1311)) / 256 = 1674 The function chosen for Examples 1 and 2 is linear between data points. If another function had been used, interpolated values might not have been identical. 5.3.4.3 TABLE EXAMPLE 3: 8-BIT INDEPENDENT VARIABLE. This example shows how to use a table instruction within an interpolation subroutine. Independent variable X is calculated as an 8-bit value, allowing 16 levels of interpolation on a 17-entry table. X is passed to the subroutine, which returns an 8-bit result. The subroutine uses the data listed in Table 5-15, based on the function shown in Figure 5-9.
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INDEPENDENT VARIABLE
Y
1024
2048
3072
4096
X
INDEPENDENT VARIABLE
Figure 5-9. Table Example 3 Table 5-15. 8-Bit Independent Variable Entries
X (Subroutine) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X (Instruction) 0 256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 Y 0 16 32 48 64 80 96 112 128 112 96 80 64 48 32 16 0
The first column is the value passed to the subroutine, the second column is the value expected by the table instruction, and the third column is the result returned by the subroutine.
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The following value has been calculated for independent variable X:
31 NOT USED 16 15 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1
Since X is an 8-bit value, the upper four bits are used as a table offset, and the lower four bits are used as an interpolation fraction. The following results are obtained from the subroutine: Table Entry Offset Dx [4:7] = $B = 11 Interpolation Fraction Dx [0:3] = $D = 13 Thus, Y is calculated as follows: Y = 80 + (13 (64 - 80)) / 16 = 67 If the 8-bit value for X were used directly by the table instruction, interpolation would be incorrectly performed between entries 0 and 1. Data must be shifted to the left four places before use: LSL.W #4, Dx The new range for X is 0 X 4096; however, since a left shift fills the least significant digits of the word with zeros, the interpolation fraction can only have one of 16 values. After the shift operation, Dx contains the following value:
31 NOT USED 16 15 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 0
Execution of the table instruction using the new value in Dx yields: Table Entry Offset Dx [8:15] = $0B = 11 Interpolation Fraction Dx [0:7] = $D0 = 208 Thus, Y is calculated as follows: Y = 80 + (208 (64 - 80)) / 256 = 67 5.3.4.4 TABLE EXAMPLE 4: MAINTAINING PRECISION. In this example, three TBL operations are performed and the results are summed. The calculation is done once with the result of each TBL rounded before addition and once with only the final result rounded. Assume that the result of the three interpolations are as follows (a ".'' indicates the binary radix point).
TBL # 1 TBL# 2 TBL # 3 0010 0000 . 0111 0000 0011 1111 . 0111 0000 0000 0001 . 0111 0000
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First, the results of each TBL are rounded with the TBLS round-to-nearest-even algorithm. The following values would be returned by TBLS:
TBL # 1 TBL # 2 TBL # 3 0010 0000 . 0011 1111 . 0000 0001 .
Summing, the following result is obtained:
0010 0011 0000 0110 0000 . 1111 . 0001 . 0000 .
Now, using the same TBL results, the sum is first calculated and then rounded according to the same algorithm:
0010 0011 0000 0110 0000 . 0111 1111 . 0111 0001 . 0111 0001 . 0101 0000 0000 0000 0000
Rounding yields:
0110 0001 .
The second result is preferred. The following code sequence illustrates how addition of a series of table interpolations can be performed without loss of precision in the intermediate results:
L0: TBLSN.B TBLSN.B TBLSN.B ADD.L ADD.L ASR.L BCC.B ADDQ.B L1: . . . ea, Dx ea, Dx ea, Dl Dx, Dm Dm, Dl #8, Dl L1 #1, Dl
Long addition avoids problems with carry Move radix point Fraction MSB in carry
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5.3.4.5 Table Example 5: Surface Interpolations. The various forms of table can be used to perform surface (3D) TBLs. However, since the calculation must be split into a series of 2D TBLs, it is possible to lose precision in the intermediate results. The following code sequence, incorporating both TBLS and TBLSN, eliminates this possibility.
L0: MOVE.W TBLSN.B TBLSN.B TBLS.W ASR.L BCC.B ADDQ.B L1: . . . Dx, Dl ea, Dx ea, Dl Dx:Dl, Dm #8, Dm L1 #1, Dl Copy entry number and fraction number
Surface interpolation, with round Read just the result No round necessary Half round up
Before execution of this code sequence, Dx must contain fraction and entry numbers for the two TBL, and Dm must contain the fraction for surface interpolation. The ea fields in the TBLSN instructions point to consecutive columns in a 3D table. The TBLS size parameter must be word if the TBLSN size parameter is byte, and must be long word if TBLSN is word. Increased size is necessary because a larger number of significant digits is needed to accommodate the scaled fractional results of the 2D TBL.
5.3.5 Nested Subroutine Calls
The LINK instruction pushes an address onto the stack, saves the stack address at which the address is stored, and reserves an area of the stack for use. Using this instruction in a series of subroutine calls will generate a linked list of stack frames. The UNLK instruction removes a stack frame from the end of the list by loading an address into the SP and pulling the value at that address from the stack. When the instruction operand is the address of the link address at the bottom of a stack frame, the effect is to remove the stack frame from both the stack and the linked list.
5.3.6 Pipeline Synchronization with the NOP Instruction
Although the no operation (NOP) instruction performs no visible operation, it does force synchronization of the instruction pipeline, since all previous instructions must complete execution before the NOP begins.
5.4 PROCESSING STATES
This section describes the processing states of the CPU32. It includes a functional description of the bits in the supervisor portion of the SR and an overview of actions taken by the processor in response to exception conditions.
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5.4.1 State Transitions
The processor is always in one of four processing states: normal, background, exception, or halted. When the processor fetches instructions and operands or executes instructions, it is in the normal processing state. The stopped condition, which the processor enters when a STOP or LPSTOP instruction is executed, is a variation of the normal state in which no further bus cycles are generated. Background state is an alternate operational mode used for system debugging. Refer to 5.6 Development Support for more information. Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines, interrupt routines, and other exception handlers. Exception processing includes the stack operations, the exception vector fetch, and the filling of the instruction pipeline caused by an exception. Exception processing ends when execution of an exception handler routine begins. Refer to 5.5 Exception Processing for comprehensive information. A catastrophic system failure occurs if the processor detects a bus error or generates an address error while in the exception processing state. This type of failure halts the processor. For example, if a bus error occurs during exception processing caused by another bus error, the CPU32 assumes that the system is not operational and halts. The halted condition should not be confused with the stopped condition. After the processor executes a STOP or LPSTOP instruction, execution of instructions can resume when a trace, interrupt, or reset exception occurs.
5.4.2 Privilege Levels
To protect system resources, the processor can operate with either of two levels of access--user or supervisor. Supervisor level is more privileged than user level. All instructions are available at the supervisor level, but execution of some instructions is not permitted at the user level. There are separate SPs for each level. The S-bit in the SR indicates privilege level and determines which SP is used for stack operations. The processor identifies each bus access (supervisor or user mode) via function codes to enforce supervisor and user access levels. In a typical system, most programs execute at the user level. User programs can access only their own code and data areas and are restricted from accessing other information. The operating system executes at the supervisor privilege level, has access to all resources, performs the overhead tasks for the user level programs, and coordinates their activities. 5.4.2.1 SUPERVISOR PRIVILEGE LEVEL. If the S-bit in the SR is set, supervisor privilege level applies, and all instructions are executable. The bus cycles generated for instructions executed in supervisor level are normally classified as supervisor references, and the values of the function codes on FC2-FC0 refer to supervisor address spaces.
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All exception processing is performed at the supervisor level. All bus cycles generated during exception processing are supervisor references, and all stack accesses use the SSP. Instructions that have important system effects can only be executed at supervisor level. For instance, user programs are not permitted to execute STOP, LPSTOP, or RESET instructions. To prevent a user program from gaining privileged access, except in a controlled manner, instructions that can alter the S-bit in the SR are privileged. The TRAP #n instruction provides controlled user access to operating system services. 5.4.2.2 USER PRIVILEGE LEVEL. If the S-bit in the SR is cleared, the processor executes instructions at the user privilege level. The bus cycles for an instruction executed at the user privilege level are classified as user references, and the values of the function codes on FC2-FC0 specify user address spaces. While the processor is at the user level, implicit references to the system SP and explicit references to address register seven (A7) refer to the USP. 5.4.2.3 CHANGING PRIVILEGE LEVEL. To change from user privilege level to supervisor privilege level, a condition that causes exception processing must occur. When exception processing begins, the current values in the SR, including the S-bit, are saved on the supervisor stack, and then the S-bit is set to enable supervisor access. Execution continues at supervisor privilege level until exception processing is complete. To return to user access level, a system routine must execute one of the following instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. These instructions execute only at supervisor privilege level and can modify the S-bit of the SR. After these instructions execute, the instruction pipeline is flushed, then refilled from the appropriate address space. The RTE instruction causes a return to a program that was executing when an exception occurred. When RTE is executed, the exception stack frame saved on the supervisor stack can be restored in either of two ways. If the frame was generated by an interrupt, breakpoint, trap, or instruction exception, the SR and PC are restored to the values saved on the supervisor stack, and execution resumes at the restored PC address, with access level determined by the S-bit of the restored SR. If the frame was generated by a bus error or an address error exception, the entire processor state is restored from the stack.
5.5 EXCEPTION PROCESSING
An exception is a special condition that pre-empts normal processing. Exception processing is the transition from normal mode program execution to execution of a routine that deals with an exception. The following paragraphs discuss system resources related to exception handling, exception processing sequence, and specific features of individual exception processing routines.
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5.5.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. The VBR contains the base address of a 1024-byte exception vector table, which consists of 256 exception vectors. Sixty-four vectors are defined by the processor, and 192 vectors are reserved for user definition as interrupt vectors. Except for the reset vector, which is two long words, each vector in the table is one long word. Refer to Table 5-16 for information on vector assignment. Table 5-16. Exception Vector Assignments
Vector Offset Vector Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-23 24 25 26 27 28 29 30 31 32-47 48-58 59-63 64-255 Dec 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 92 96 100 104 108 112 116 120 124 128 188 192 232 236 252 256 1020 Hex 000 004 008 00C 010 014 018 01C 020 024 028 02C 030 034 038 03C 040 05C 060 064 068 06C 070 074 078 07C 080 0BC 0C0 0E8 0EC 0FC 100 3FC Space SP SP SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD Assignment Reset: Initial Stack Pointer Reset: Initial Program Counter Bus Error Address Error Illegal Instruction Zero Division CHK, CHK2 Instructions TRAPcc, TRAPV Instructions Privilege Violation Trace Line 1010 Emulator Line 1111 Emulator Hardware Breakpoint (Reserved for Coprocessor Protocol Violation) Format Error Uninitialized Interrupt (Unassigned, Reserved) -- Spurious Interrupt Level 1 Interrupt Autovector Level 2 Interrupt Autovector Level 3 Interrupt Autovector Level 4 Interrupt Autovector Level 5 Interrupt Autovector Level 6 Interrupt Autovector Level 7 Interrupt Autovector Trap Instruction Vectors (0-15) -- (Reserved for Coprocessor) -- (Unassigned, Reserved) -- User-Defined Vectors (192)
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CAUTION Because there is no protection on the 64 processor-defined vectors, external devices can access vectors reserved for internal purposes. This practice is strongly discouraged. All exception vectors, except the reset vector, are located in supervisor data space. The reset vector is located in supervisor program space. Only the initial reset vector is fixed in the processor memory map. When initialization is complete, there are no fixed assignments. Since the VBR stores the vector table base address, the table can be located anywhere in memory. It can also be dynamically relocated for each task executed by an operating system. Each vector is assigned an 8-bit number. Vector numbers for some exceptions are obtained from an external device; others are supplied by the processor. The processor multiplies the vector number by 4 to calculate vector offset, then adds the offset to the contents of the VBR. The sum is the memory address of the vector. 5.5.1.1 TYPES OF EXCEPTIONS. An exception can be caused by internal or external events. An internal exception can be generated by an instruction or by an error. The TRAP, TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause exceptions during normal execution. Illegal instructions, instruction fetches from odd addresses, word or long-word operand accesses from odd addresses, and privilege violations also cause internal exceptions. Sources of external exception include interrupts, breakpoints, bus errors, and reset requests. Interrupts are peripheral device requests for processor action. Breakpoints are used to support development equipment. Bus error and reset are used for access control and processor restart. 5.5.1.2 EXCEPTION PROCESSING SEQUENCE. For all exceptions other than a reset exception, exception processing occurs in the following sequence. Refer to 5.5.2.1 Reset for details of reset processing. As exception processing begins, the processor makes an internal copy of the SR. After the copy is made, the processor state bits in the SR are changed--the S-bit is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling tracing. For reset and interrupt exceptions, the interrupt priority mask is also updated. Next, the exception number is obtained. For interrupts, the number is fetched from CPU space $F (the bus cycle is an interrupt acknowledge). For all other exceptions, internal logic provides a vector number. Next, current processor status is saved. An exception stack frame is created and placed on the supervisor stack. All stack frames contain copies of the SR and the PC for use by RTE. The type of exception and the context in which the exception occurs determine what other information is stored in the stack frame.
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Finally, the processor prepares to resume normal execution of instructions. The exception vector offset is determined by multiplying the vector number by 4, and the offset is added to the contents of the VBR to determine displacement into the exception vector table. The exception vector is loaded into the PC. If no other exception is pending, the processor will resume normal execution at the new address in the PC. 5.5.1.3 EXCEPTION STACK FRAME. During exception processing, the most volatile portion of the current context is saved on the top of the supervisor stack. This context is organized in a format called the exception stack frame. The exception stack frame always includes the contents of SR and PC at the time the exception occurred. To support generic handlers, the processor also places the vector offset in the exception stack frame and marks the frame with a format code. The format field allows an RTE instruction to identify stack information so that it can be properly restored. The general form of the exception stack frame is illustrated in Figure 5-10. Although some formats are peculiar to a particular M68000 Family processor, format 0000 is always legal and always indicates that only the first four words of a frame are present. See 5.5.4 CPU32 Stack Frames for a complete discussion of exception stack frames.
15 SP HIGHER ADDRESSES STATUS REGISTER STACKING ORDER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW FORMAT VECTOR OFFSET OTHER PROCESSOR STATE INFORMATION, DEPENDING ON EXCEPTION (0, 2, OR 8 WORDS) 0
Figure 5-10. Exception Stack Frame 5.5.1.4 MULTIPLE EXCEPTIONS. Each exception has been assigned a priority based on its relative importance to system operation. Priority assignments are shown in Table 5-17. Group 0 exceptions have the highest priorities; group 4 exceptions have the lowest priorities. Exception processing for exceptions that occur simultaneously is done by priority, from highest to lowest. It is important to be aware of the difference between exception processing mode and execution of an exception handler. Each exception has an assigned vector that points to an associated handler routine. Exception processing includes steps described in 5.5.1.2 Exception Processing Sequence, but does not include execution of handler routines, which is done in normal mode.
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When the CPU32 completes exception processing, it is ready to begin either exception processing for a pending exception or execution of a handler routine. Priority assignment governs the order in which exception processing occurs, not the order in which exception handlers are executed. Table 5-17. Exception Priority Groups
Group/ Priority 0 1.1 1.2 2 Reset Address Error Bus Error BKPT#n, CHK, CHK2, Division by Zero, RTE, TRAP#n, TRAPcc, TRAPV Illegal Instruction, Line A, Unimplemented Line F, Privilege Violation Trace Hardware Breakpoint Interrupt Exception and Relative Priority Characteristics Aborts all processing (instruction or exception); does not save old context. Suspends processing (instruction or exception); saves internal context. Exception processing is a part of instruction execution. Exception processing begins before instruction execution. Exception processing begins when current instruction or previous exception processing is complete.
3
4.1 4.2 4.3
As a general rule, when simultaneous exceptions occur, the handler routines for lower priority exceptions are executed before the handler routines for higher priority exceptions. For example, consider the arrival of an interrupt during execution of a TRAP instruction while tracing is enabled. Trap exception processing (2) is done first, followed immediately by exception processing for the trace (4.1), and then by exception processing for the interrupt (4.3). Each exception places a new context on the stack. When the processor resumes normal instruction execution, it is vectored to the interrupt handler, which returns to the trace handler that returns to the trap handler. There are special cases to which the general rule does not apply. The reset exception will always be the first exception handled since reset clears all other exceptions. It is also possible for high-priority exception processing to begin before low-priority exception processing is complete. For example, if a bus error occurs during trace exception processing, the bus error will be processed and handled before trace exception processing has completed.
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5.5.2 Processing of Specific Exceptions
The following paragraphs provide details concerning sources of specific exceptions, how each arises, and how each is processed. 5.5.2.1 RESET. Assertion of RESET by external hardware or assertion of the internal RESET signal by an internal module causes a reset exception. The reset exception has the highest priority of any exception. Reset is used for system initialization and for recovery from catastrophic failure. When the reset exception is recognized, it aborts any processing in progress, and that processing cannot be recovered. Reset performs the following operations: 1. Clears T0 and T1 in the SR to disable tracing 2. Sets the S-bit in the SR to establish supervisor privilege 3. Sets the interrupt priority mask to the highest priority level (%111) 4. Initializes the VBR to zero ($00000000) 5. Generates a vector number to reference the reset exception vector 6. Loads the first long word of the vector into the interrupt SP 7. Loads the second long word of the vector into the PC 8. Fetches and initiates decode of the first instruction to be executed Figure 5-11 is a flowchart of the reset exception After initial instruction prefetches, normal program execution begins at the address in the PC. The reset exception does not save the value of either the PC or the SR. If a bus error or address error occurs during reset exception processing, a double bus fault occurs, the processor halts, and the HALT signal is asserted to indicate the halted condition. Execution of the RESET instruction does not cause a reset exception nor does it affect any internal CPU register. The SIM40 registers and the module control register in each internal peripheral module (DMA, timers, and serial modules) are not affected. All other internal peripheral module registers are reset the same as for a hardware reset. The external devices connected to the RESET signal are reset at the completion of the RESET instruction.
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ENTRY 1 0 $7 $0
S T0,T1 I2:I0 VBR
.
FETCH VECTOR # 0
OTHERWISE SP (VECTOR # 0)
BUS ERROR
FETCH VECTOR # 1
PC
(VECTOR # 1)
OTHERWISE
BUS ERROR
PREFETCH 3 WORDS
OTHERWISE BEGIN INSTRUCTION EXECUTION
BUS ERROR/ ADDRESS ERROR (DOUBLE BUS FAULT) ASSERT HALT
EXIT
EXIT
Figure 5-11. Reset Operation Flowchart
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5.5.2.2 BUS ERROR. A bus error exception occurs when an assertion of the BERR signal is acknowledged. The BERR signal can be asserted by one of three sources: 1. External logic by assertion of the BERR input pin 2. Direct assertion of the internal BERR signal by an internal module 3. Direct assertion of the internal BERR signal by the on-chip hardware watchdog after detecting a no-response condition Bus error exception processing begins when the processor attempts to use information from an aborted bus cycle. When the aborted bus cycle is an instruction prefetch, the processor will not initiate exception processing unless the prefetched information is used. For example, if a branch instruction flushes an aborted prefetch, that word is not accessed, and no exception occurs. When the aborted bus cycle is a data access, the processor initiates exception processing immediately, except in the case of released operand writes. Released write bus errors are delayed until the next instruction boundary or until another operand access is attempted. Exception processing for bus error exceptions follows the regular sequence, but context preservation is more involved than for other exceptions because a bus exception can be initiated while an instruction is executing. Several bus error stack format organizations are utilized to provide additional information regarding the nature of the fault. First, any register altered by a faulted-instruction EA calculation is restored to its initial value. Then a special status word (SSW) is placed on the stack. The SSW contains specific information about the aborted access--size, type of access (read or write), bus cycle type, and function code. Finally, fault address, bus error exception vector number, PC value, and a copy of the SR are saved. If a bus error occurs during exception processing for a bus error, an address error, a reset, or while the processor is loading stack information during RTE execution, the processor halts. This simplifies isolation of catastrophic system failure by preventing processor interaction with stacks and memory. Only assertion of RESET can restart a halted processor. 5.5.2.3 ADDRESS ERROR. Address error exceptions occur when the processor attempts to access an instruction, word operand, or long-word operand at an odd address. The effect is much the same as an internally generated bus error. The exception processing sequence is the same as that for bus error, except that the vector number refers to the address error exception vector. Address error exception processing begins when the processor attempts to use information from the aborted bus cycle. If the aborted cycle is a data space access, exception processing begins when the processor attempts to use the data, except in the
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case of a released operand write. Released write exceptions are delayed until the next instruction boundary or attempted operand access. An address exception on a branch to an odd address is delayed until the PC is changed. No exception occurs if the branch is not taken. In this case, the fault address and return PC value placed in the exception stack frame are the odd address, and the current instruction PC points to the instruction that caused the exception. If an address error occurs during exception processing for a bus error, another address error, or a reset, the processor halts. 5.5.2.4 INSTRUCTION TRAPS. Traps are exceptions caused by instructions. They arise from either processor recognition of abnormal conditions during instruction execution or from use of specific trapping instructions. Traps are generally used to handle abnormal conditions that arise in control routines. The TRAP instruction, which always forces an exception, is useful for implementing system calls for user programs. The TRAPcc, TRAPV, CHK, and CHK2 instructions force exceptions when a program detects a run-time error. The DIVS and DIVU instructions force an exception if a division operation is attempted with a divisor of zero. Exception processing for traps follows the regular sequence. If tracing is enabled when an instruction that causes a trap begins execution, a trace exception will be generated by the instruction, but the trap handler routine will not be traced. (The trap exception will be processed first, then the trace exception.) The vector number for the TRAP instruction is internally generated--part of the number comes from the instruction itself. The trap vector number, PC value, and a copy of the SR are saved on the supervisor stack. The saved PC value is the address of the instruction that follows the instruction that generated the trap. For all instruction traps other than TRAP, a pointer to the instruction causing the trap is also saved in the fifth and sixth words of the exception stack frame. 5.5.2.5 SOFTWARE BREAKPOINTS. To support hardware emulation, the CPU32 must provide a means of inserting breakpoints into target code and of announcing when a breakpoint is reached. The MC68000 and MC68008 can detect an illegal instruction inserted at a breakpoint when the processor fetches from the illegal instruction exception vector location. Since the VBR on the CPU32 allows relocation of exception vectors, the exception vector address is not a reliable indication of a breakpoint. CPU32 breakpoint support is provided by extending the function of a set of illegal instructions ($4848-$484F). When a breakpoint instruction is executed, the CPU32 performs a read from CPU space $0, at a location corresponding to the breakpoint number. If this bus cycle is terminated by BERR , the processor performs illegal instruction exception processing. If the bus cycle is terminated by DSACK, the processor uses the data returned to replace the breakpoint in the instruction pipeline and begins execution of that instruction. See Section 3 Bus Operation for a description of CPU space operations.
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5.5.2.6 HARDWARE BREAKPOINTS. The CPU32 recognizes hardware breakpoint requests. Hardware breakpoint requests do not force immediate exception processing, but are left pending. An instruction breakpoint is not made pending until the instruction corresponding to the request is executed. A pending breakpoint can be acknowledged between instructions or at the end of exception processing. To acknowledge a breakpoint, the CPU performs a read from CPU space $0 at location $1E (see Section 3 Bus Operation). If the bus cycle terminates normally, instruction execution continues with the next instruction as if no breakpoint request occurred. If the bus cycle is terminated by BERR , the CPU begins exception processing. Data returned during this bus cycle is ignored. Exception processing follows the regular sequence. Vector number 12 (offset $30) is internally generated. The PC of the executing instruction, the PC of the next instruction to be executed, and a copy of the SR are saved on the supervisor stack. 5.5.2.7 FORMAT ERROR. The processor checks certain data values for control operations. The validity of the stack format code and, in the case of a bus cycle fault format, the version number of the processor that generated the frame are checked during execution of the RTE instruction. This check ensures that the program does not make erroneous assumptions about information in the stack frame. If the format of the control data is improper, the processor generates a format error exception. This exception saves a four-word format exception frame and then vectors through vector table entry number 14. The stacked PC is the address of the RTE instruction that discovered the format error. 5.5.2.8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS. An instruction is illegal if it contains a word bit pattern that does not correspond to the bit pattern of the first word of a legal CPU32 instruction, if it is a MOVEC instruction that contains an undefined register specification field in the first extension word, or if it contains an indexed addressing mode extension word with bits 5-4 = 00 or bits 3-0 0000. If an illegal instruction is fetched during instruction execution, an illegal instruction exception occurs. This facility allows the operating system to detect program errors or to emulate instructions in software. Word patterns with bits 15-12 = 1010 (referred to as A-line opcodes) are unimplemented instructions. A separate exception vector (vector 10, offset $28) is given to unimplemented instructions to permit efficient emulation. Word patterns with bits 15-12 = 1111 (referred to as F-line opcodes) are used for M68000 family instruction set extensions. They can generate an unimplemented instruction exception caused by the first extension word of the instruction or by the addressing mode extension word. A separate F-line emulation vector (vector 11, offset $2C) is used for the exception vector.
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All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal on all M68000 family members. Those customers requiring the use of an unimplemented opcode for synthesis of "custom instructions," operating system calls, etc., should use this opcode. Exception processing for illegal and unimplemented instructions is similar to that for traps. The instruction is fetched and decoding is attempted. When the processor determines that execution of an illegal instruction is being attempted, exception processing begins. No registers are altered. Exception processing follows the regular sequence. The vector number is generated to refer to the illegal instruction vector or in the case of an unimplemented instruction, to the corresponding emulation vector. The illegal instruction vector number, current PC, and a copy of the SR are saved on the supervisor stack, with the saved value of the PC being the address of the illegal or unimplemented instruction. 5.5.2.9 PRIVILEGE VIOLATIONS. To provide system security, certain instructions can be executed only at the supervisor access level. An attempt to execute one of these instructions at the user level will cause an exception. The privileged exceptions are as follows: * AND Immediate to SR * EOR Immediate to SR * LPSTOP * MOVE from SR * MOVE to SR * MOVE USP * MOVEC * MOVES * OR Immediate to SR * RESET * RTE * STOP Exception processing for privilege violations is nearly identical to that for illegal instructions. The instruction is fetched and decoded. If the processor determines that a privilege violation has occurred, exception processing begins before instruction execution. Exception processing follows the regular sequence. The vector number (8) is generated to reference the privilege violation vector. Privilege violation vector offset, current PC, and SR are saved on the supervisor stack. The saved PC value is the address of the first word of the instruction causing the privilege violation.
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5.5.2.10 TRACING. To aid in program development, M68000 processors include a facility to allow tracing of instruction execution. CPU32 tracing also has the ability to trap on changes in program flow. In trace mode, a trace exception is generated after each instruction executes, allowing a debugging program to monitor the execution of a program under test. The T1 and T0 bits in the supervisor portion of the SR are used to control tracing. When T1-T0 = 00, tracing is disabled, and instruction execution proceeds normally (see Table 5-18). Table 5-18. Tracing Control
T1 0 0 1 1 T0 0 1 0 1 Tracing Function No tracing Trace on change of flow Trace on instruction execution Undefined; reserved
When T1-T0 = 01 at the beginning of instruction execution, a trace exception will be generated if the PC changes sequence during execution. All branches, jumps, subroutine calls, returns, and SR manipulations can be traced in this way. No exception occurs if a branch is not taken. When T1-T0 = 10 at the beginning of instruction execution, a trace exception will be generated when execution is complete. If the instruction is not executed, either because an interrupt is taken or because the instruction is illegal, unimplemented, or privileged, an exception is not generated. At the present time, T1-T0 = 11 is an undefined condition. It is reserved by Motorola for future use. Exception processing for trace starts at the end of normal processing for the traced instruction and before the start of the next instruction. Exception processing follows the regular sequence; tracing is disabled so that the trace exception itself is not traced. A vector number is generated to reference the trace exception vector. The address of the instruction that caused the trace exception, the trace exception vector offset, the current PC, and a copy of the SR are saved on the supervisor stack. The saved value of the PC is the address of the next instruction to be executed. A trace exception can be viewed as an extension to the function of any instruction. If a trace exception is generated by an instruction, the execution of that instruction is not complete until the trace exception processing associated with it is also complete. If an instruction is aborted by a bus error or address error exception, trace exception processing is deferred until the suspended instruction is restarted and completed normally. An RTE from a bus error or address error will not be traced because of the possibility of continuing the instruction from the fault.
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If an instruction is executed and an interrupt is pending on completion, the trace exception is processed before the interrupt exception. If an instruction forces an exception, the forced exception is processed before the trace exception. If an instruction is executed and a breakpoint is pending upon completion of the instruction, the trace exception is processed before the breakpoint. If an attempt is made to execute an illegal, unimplemented, or privileged instruction while tracing is enabled, no trace exception will occur because the instruction is not executed. This is particularly important to an emulation routine that performs an instruction function, adjusts the stacked PC to beyond the unimplemented instruction, and then returns. The SR on the stack must be checked to determine if tracing is on before the return is executed. If tracing is on, trace exception processing must be emulated so that the trace exception handler can account for the emulated instruction. Tracing also affects normal operation of the STOP and LPSTOP instructions. If either instruction begins execution with T1 set, a trace exception will be taken after the instruction loads the SR. Upon return from the trace handler routine, execution will continue with the instruction following STOP (LPSTOP), and the processor will not enter the stopped condition. 5.5.2.11 INTERRUPTS. There are seven levels of interrupt priority and 192 assignable interrupt vectors within each exception vector table. Careful use of multiple vector tables and hardware chaining will permit a virtually unlimited number of peripherals to interrupt the processor. Interrupt recognition and subsequent processing are based on internal interrupt request signals (IRQ7- IRQ1 ) and the current priority set in SR priority mask I2-I0. Interrupt request level 0 (IRQ7- IRQ1 negated) indicates that no service is requested. When an interrupt of level 1 through 6 is requested via IRQ6- IRQ1 , the processor compares the request level with the interrupt mask to determine whether the interrupt should be processed. Interrupt requests are inhibited for all priority levels less than or equal to the current priority. Level 7 interrupts are nonmaskable. IRQ7- IRQ1 are synchronized and debounced by input circuitry on consecutive rising edges of the processor clock. To be valid, an interrupt request must be held constant for at least two consecutive clock periods. Interrupt requests do not force immediate exception processing, but are left pending. A pending interrupt is detected between instructions or at the end of exception processing-- all interrupt requests must be held asserted until they are acknowledged by the CPU. If the priority of the interrupt is greater than the current priority level, exception processing begins. Exception processing occurs as follows. First, the processor makes an internal copy of the SR. After the copy is made, the processor state bits in the SR are changed--the S-bit is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling
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tracing. Priority level is then set to the level of the interrupt, and the processor fetches a vector number from the interrupting device (CPU space $F). The fetch bus cycle is classified as an interrupt acknowledge, and the encoded level number of the interrupt is placed on the address bus. If an interrupting device requests automatic vectoring, the processor generates a vector number (25 to 31) determined by the interrupt level number. If the response to the interrupt acknowledge bus cycle is a bus error, the interrupt is taken to be spurious, and the spurious interrupt vector number (24) is generated. The exception vector number, PC, and SR are saved on the supervisor stack. The saved value of the PC is the address of the instruction that would have executed if the interrupt had not occurred. Priority level 7 interrupt is a special case. Level 7 interrupts are nonmaskable interrupts (NMI). Level 7 requests are transition sensitive to eliminate redundant servicing and resultant stack overflow. Transition sensitive means that the level 7 input must change state before the CPU will detect an interrupt. An NMI is generated each time the interrupt request level changes to level 7 (regardless of priority mask value), and each time the priority mask changes from 7 to a lower number while the request level remains at 7. Many M68000 peripherals provide for programmable interrupt vector numbers to be used in the system interrupt request/acknowledge mechanism. If the vector number is not initialized after reset and if the peripheral must acknowledge an interrupt request, the peripheral should return the uninitialized interrupt vector number (15). See Section 3 Bus Operation for detailed information on interrupt acknowledge cycles. 5.5.2.12 RETURN FROM EXCEPTION. When exception stacking operations for all pending exceptions are complete, the processor begins execution of the handler for the last exception processed. After the exception handler has executed, the processor must restore the system context in existence prior to the exception. The RTE instruction is designed to accomplish this task. When RTE is executed, the processor examines the stack frame on top of the supervisor stack to determine if it is valid and determines what type of context restoration must be performed. See 5.5.4 CPU32 Stack Frames for a description of stack frames. For a normal four-word frame, the processor updates the SR and PC with data pulled from the stack, increments the SSP by 8, and resumes normal instruction execution. For a sixword frame, the SR and PC are updated from the stack, the active SSP is incremented by 12, and normal instruction execution resumes. For a bus fault frame, the format value on the stack is first checked for validity. In addition, the version number on the stack must match the version number of the processor that is
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attempting to read the stack frame. The version number is located in the most significant byte (bits 15-8) of the internal register word at location SP + $14 in the stack frame. The validity check ensures that stack frame data will be properly interpreted in multiprocessor systems. If a frame is invalid, a format error exception is taken. If it is inaccessible, a bus error exception is taken. Otherwise, the processor reads the entire frame into the proper internal registers, de-allocates the stack (12 words), and resumes normal processing. Bus error frames for faults during exception processing require the RTE instruction to rewrite the faulted stack frame. If an error occurs during any of the bus cycles required by rewrite, the processor halts. If a format error occurs during RTE execution, the processor creates a normal four-word fault stack frame below the frame that it was attempting to use. If a bus error occurs, a bus-error stack frame will be created. The faulty stack frame remains intact, so that it may be examined and repaired by an exception handler or used by a different type of processor (e.g., MC68010, MC68020, or future M68000 processor) in a multiprocessor system.
5.5.3 Fault Recovery
There are four phases of recovery from a fault: recognizing the fault, saving the processor state, repairing the fault (if possible), and restoring the processor state. Saving and restoring the processor state are described in the following paragraphs. The stack contents are identified by the special status word (SSW). In addition to identifying the fault type represented by the stack frame, the SSW contains the internal processor state corresponding to the fault.
15 TP 14 MV 13 0 12 TR 11 B1 10 B0 9 RR 8 RM 7 IN 6 RW 5 LG 4 SIZ 3 2 1 FUNC 0
TP--BERR Frame Type The TP field defines the class of the faulted bus operation. Two bus error exception frame types are defined. One is for faults on prefetch and operand accesses, and the other is for faults during exception frame stacking. 0 = Operand or prefetch bus fault 1 = Exception processing bus fault MV--MOVEM in Progress MV is set when the operand transfer portion of the MOVEM instruction is in progress at the time of a bus fault. If a prefetch bus fault occurs while prefetching the MOVEM opcode and extension word, both the MV and IN bits will be set. 0 = MOVEM was not in progress when fault occurred 1 = MOVEM was in progress when fault occurred
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TR--Trace Pending TR indicates that a trace exception was pending when a bus error exception was processed. The instruction that generated the trace will not be restarted upon return from the exception handler. This includes MOVEM and released write bus errors indicated by the assertion of either MV or RR in the SSW. 0 = Trace not pending 1 = Trace pending B1--Breakpoint Channel 1 Pending B1 indicates that a breakpoint exception was pending on channel 1 (external breakpoint source) when a bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception. 0 = Breakpoint not pending 1 = Breakpoint pending B0--Breakpoint Channel 0 Pending B0 indicates that a breakpoint exception was pending on channel 0 (internal breakpoint source) when the bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception. 0 = Breakpoint not pending 1 = Breakpoint pending RR--Rerun Write Cycle after RTE RR will be set if the faulted bus cycle was a released write. A released write is one that is overlapped. If the write is completed (rerun) in the exception handler, the RR bit should be cleared before executing RTE. The bus cycle will be rerun if the RR bit is set upon return from the exception handler. 0 = Faulted cycle was read, RMW, or unreleased write 1 = Faulted cycle was a released write RM--Faulted Cycle Was Read-Modify-Write Faulted RMW bus cycles set the RM bit. RM is ignored during unstacking. 0 = Faulted cycle was non-RMW cycle 1 = Faulted cycle was either the read or write of an RMW cycle IN--Instruction/Other Instruction prefetch faults are distinguished from operand (both read and write) faults by the IN bit. If IN is cleared, the error was on an operand cycle; if IN is set, the error was on an instruction prefetch. IN is ignored during unstacking. 0 = Operand 1 = Prefetch
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RW--Read/Write of Faulted Bus Cycle Read and write bus cycles are distinguished by the RW bit. Read bus cycles will set this bit, and write bus cycles will clear it. RW is reloaded into the bus controller if the RR bit is set during unstacking. 0 = Faulted cycle was an operand write 1 = Faulted cycle was a prefetch or operand read SIZ--Remaining Size of Faulted Bus Cycle The SIZ field shows operand size remaining when a fault was detected. This field does not indicate the initial size of the operand, nor does it necessarily indicate the proper status of a dynamically sized bus cycle. Dynamic sizing occurs on the external bus and is transparent to the CPU. Byte size is shown only when the original operand was a byte. The field is reloaded into the bus controller if the RR bit is set during unstacking. The SIZ field is encoded as follows: 00 = Long word 01 = Byte 10 = Word 11 = Unused, reserved FUNC--Function Code of Faulted Bus Cycle The function code for the faulted cycle is stacked in the FUNC field of the SSW, which is a copy of FC2-FC0 for the faulted bus cycle. This field is reloaded into the bus controller if the RR bit is set during unstacking. All unused bits are stacked as zeros and are ignored during unstacking. Further discussion of the SSW is included in 5.5.3.1 Types of Faults. 5.5.3.1 TYPES OF FAULTS. An efficient implementation of instruction restart dictates that faults on some bus cycles be treated differently than faults on other bus cycles. The CPU32 defines four fault types: released write faults, faults during exception processing, faults during MOVEM operand transfer, and faults on any other bus cycle. 5.5.3.1.1 Type I--Released Write Faults. CPU32 instruction pipelining can cause a final instruction write to overlap the execution of a following instruction. A write that is overlapped is called a released write. A released write fault occurs when a bus error or some other fault occurs on the released write. Released write faults are taken at the next instruction boundary. The stacked PC is that of the next unexecuted instruction. If a subsequent instruction attempts an operand access while a released write fault is pending, the instruction is aborted and the write fault is acknowledged. This action prevents the instruction from using stale data.
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The SSW for a released write fault contains the following bit pattern:
15 0 14 0 13 0 12 TR 11 B1 10 B0 9 1 8 0 7 0 6 0 5 LG 4 SIZ 3 2 FUNC 0
TR, B1, and B0 are set if the corresponding exception is pending when the bus error exception is taken. Status regarding the faulted bus cycle is reflected in the LG, SIZ, and FUNC fields. The remainder of the stack contains the PC of the next unexecuted instruction, the current SR, the address of the faulted memory location, and the contents of the data buffer that was to be written to memory. This data is written on the stack in the format depicted in Figure 5-15. When a released write fault exception handler executes, the machine will complete the faulted write and then continue executing instructions wherever the PC indicates. 5.5.3.1.2 Type II--Prefetch, Operand, RMW, and MOVEP Faults. The majority of bus error exceptions are included in this category--all instruction prefetches, all operand reads, all RMW cycles, and all operand accesses resulting from execution of MOVEP (except the last write of a MOVEP Rn,ea or the last write of MOVEM, which are type I faults). The TAS, MOVEP, and MOVEM instructions account for all operand writes not considered released write faults. All type II faults cause an immediate exception that aborts the current instruction. Any registers that were altered as the result of an EA calculation (i.e., postincrement or predecrement) are restored prior to processing the bus cycle fault. The SSW for faults in this category contains the following bit pattern:
15 0 14 0 13 0 12 0 11 B1 10 B0 9 0 8 RM 7 IN 6 RW 5 LG 4 SIZ 3 2 FUNC 0
The trace pending bit is always cleared, since the instruction will be restarted upon return from the handler. Saving a pending exception on the stack causes a trace exception to be taken prior to restarting the instruction. If the exception handler does not alter the stacked SR trace bits, the trace is requeued when the instruction is started. The breakpoint pending bits are stacked in the SSW, even though the instruction is restarted upon return from the handler. This avoids problems with bus state analyzer equipment that has been programmed to breakpoint only the first access to a specific location or to count accesses to that location. If this response is not desired, the exception handler can clear the bits before return. The RM, IN, RW, LG, FUNC, and SIZ fields all reflect the type of bus cycle that caused the fault. If the bus cycle was an RMW, the RM bit will be set, and the RW bit will show whether the fault was on a read or write.
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5.5.3.1.3 Type III--Faults During MOVEM Operand Transfer. Bus faults that occur as a result of MOVEM operand transfer are classified as type III faults. MOVEM instruction prefetch faults are type II faults. Type III faults cause an immediate exception that aborts the current instruction. Registers altered during execution of the faulted instruction are not restored prior to execution of the fault handler. This includes any register predecremented as a result of the effective address calculation or any register overwritten during instruction execution. Since postincremented registers are not updated until the end of an instruction, the register retains its pre-instruction value unless overwritten by operand movement. The SSW for faults in this category contains the following bit pattern:
15 0 14 1 13 0 12 TR 11 B1 10 B0 9 RR 8 0 7 IN 6 RW 5 LG 4 SIZ 3 2 FUNC 0
MV is set, indicating that MOVEM should be continued from the point where the fault occurred upon return from the exception handler. TR, B1, and B0 are set if a corresponding exception is pending when the bus error exception is taken. IN is set if a bus fault occurs while prefetching an opcode or an extension word during instruction restart. RW, LG, SIZ, and FUNC all reflect the type of bus cycle that caused the fault. All write faults have the RR bit set to indicate that the write should be rerun upon return from the exception handler. The remainder of the stack frame contains sufficient information to continue MOVEM with operand transfer following a faulted transfer. The address of the next operand to be transferred, incremented or decremented by operand size, is stored in the faulted address location ($08). The stacked transfer counter is set to 16 minus the number of transfers attempted (including the faulted cycle). Refer to Figure 5-12 for the stacking format. 5.5.3.1.4 Type IV--Faults During Exception Processing. The fourth type of fault occurs during exception processing. If this exception is a second address or bus error, the machine halts in the double bus fault condition. However, if the exception is one that causes a four- or six-word stack frame to be written, a bus cycle fault frame is written below the faulted exception stack frame. The SSW for a fault within an exception contains the following bit pattern:
15 1 14 0 13 0 12 TR 11 B1 10 B0 9 0 8 0 7 0 6 1 5 LG 4 SIZ 3 2 FUNC 0
TR, B1, and B0 are set if a corresponding exception is pending when the bus error exception is taken. The contents of the faulted exception stack frame are included in the bus fault stack frame. The pre-exception SR and the format/vector word of the faulted frame are stacked. The type of exception can be determined from the format/vector word. If the faulted exception stack frame contains six words, the PC of the instruction that caused the initial
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exception is also stacked. This data is placed on the stack in the format shown in Figure 5-13. The return address from the initial exception is stacked for RTE . 5.5.3.2 CORRECTING A FAULT. There are two ways to complete a faulted released write bus cycle. The first is to use a software handler. The second is to rerun the bus cycle via RTE. Type II fault handlers must terminate with RTE, but specific requirements must also be met before an instruction is restarted. There are three varieties of type III operand fault recovery. The first is completion of an instruction in software. The second is conversion to type II with restart via RTE. The third is continuation from the fault via RTE. 5.5.3.2.1 Type I--Completing Released Writes via Software. To complete a bus cycle in software, a handler must first read the SSW function code field to determine the appropriate address space, access the fault address pointer on the stack, and then transfer data from the stacked image of the output buffer to the fault address. Because the CPU32 has a 16-bit internal data bus, long operands require two bus accesses. A fault during the second access of a long operand causes the LG bit in the SSW to be set. The SIZ field indicates remaining operand size. If operand coherency is important, the complete operand must be rewritten. After a long operand is rewritten, the RR bit must be cleared. Failure to clear the RR bit can cause the RTE instruction to rerun the bus cycle. Following rewrite, it is not necessary to adjust the PC (or other stack contents) before executing RTE. 5.5.3.2.2 Type I--Completing Released Writes via RTE. An exception handler can use the RTE instruction to complete a faulted bus cycle. When RTE executes, the fault address, data output buffer, PC, and SR are restored from the stack. Any pending breakpoint or trace exceptions, as indicated by TR, B1, and B0 in the stacked SSW, are requeued during SSW restoration. The RR bit in the SSW is checked during the unstacking operation; if it is set, the RW, FUNC, and SIZ fields are restored and the released write cycle is rerun. To maintain long-word operand coherence, stack contents must be adjusted prior to RTE execution. The fault address must be decremented by 2 if LG is set and SIZ indicates a remaining byte or word. SIZ must be set to long. All other fields should be left unchanged. The bus controller uses the modified fault address and SIZ field to rerun the complete released write cycle. Manipulating the stacked SSW can cause unpredictable results because RTE checks only the RR bit to determine if a bus cycle must be rerun. Inadvertent alteration of the control bits could cause the bus cycle to be a read instead of a write or could cause access to a different address space than the original bus cycle. If the rerun bus cycle is a read, returned data will be ignored.
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5.5.3.2.3 Type II--Correcting Faults via RTE. Instructions aborted because of a type II fault are restarted upon return from the exception handler. A fault handler must establish safe restart conditions. If a fault is caused by a nonresident page in a demand-paged virtual memory configuration, the fault address must be read from the stack, and the appropriate page retrieved. An RTE instruction terminates the exception handler. After unstacking the machine state, the instruction is refetched and restarted. 5.5.3.2.4 Type III--Correcting Faults via Software. Sufficient information is contained in the stack frame to complete MOVEM in software. After the cause of the fault is corrected, the faulted bus cycle must be rerun. Perform the following procedures to complete an instruction through software: A. Set Up for Rerun 1. Read the MOVEM opcode and extension from locations pointed to by stack frame PC and PC + 2. The EA need not be recalculated since the next operand address is saved in the stack frame. However, the opcode EA field must be examined to determine how to update the address register and PC when the instruction is complete. 2. Adjust the mask to account for operands already transferred. Subtract the stacked operand transfer count from 16 to obtain the number of operands transferred. Scan the mask using this count value. Each time a set bit is found, clear it and decrement the counter. When the count is zero, the mask is ready for use. 3. Adjust the operand address. If the predecrement addressing mode is in effect, subtract the operand size from the stacked value; otherwise, add the operand size to the stacked value. B. Rerun Instruction 1. Scan the mask for set bits. Read/write the selected register from/to the operand address as each bit is found. 2. As each operand is transferred, clear the mask bit and increment (decrement) the operand address. When all bits in the mask are cleared, all operands have been transferred. 3. If the addressing mode is predecrement or postincrement, update the register to complete the execution of the instruction. 4. If TR is set in the stacked SSW, create a six-word stack frame and execute the trace handler. If either B1 or B0 is set in the SSW, create another six-word stack frame and execute the hardware breakpoint handler. 5. De-allocate the stack and return control to the faulted program. 5.5.3.2.5 Type III--Correcting Faults by Conversion and Restart. In some situations, it may be necessary to rerun all the operand transfers for a faulted instruction rather than continue from a faulted operand. Clearing the MV bit in the stacked SSW converts a type III fault into a type II fault. Consequently, MOVEM, like all other type II
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exceptions, will be restarted upon return from the exception handler. When a fault occurs after an operand has transferred, that transfer is not "undone". However, these memory locations are accessed a second time when the instruction is restarted. If a register used in an EA calculation is overwritten before a fault occurs, an incorrect EA is calculated upon instruction restart. 5.5.3.2.6 Type III--Correcting Faults via RTE. The preferred method of MOVEM bus fault recovery is to correct the cause of the fault and then execute an RTE instruction without altering the stack contents. The RTE recognizes that MOVEM was in progress when a fault occurred, restores the appropriate machine state, refetches the instruction, repeats the faulted transfer, and continues the instruction. MOVEM is the only instruction continued upon return from an exception handler. Although the instruction is refetched, the EA is not recalculated, and the mask is rescanned the same number of times as before the fault. Modifying the code prior to RTE can cause unexpected results. 5.5.3.2.7 Type IV--Correcting Faults via Software. Bus error exceptions can occur during exception processing while the processor is fetching an exception vector or while it is stacking. The same stack frame and SSW are used in both cases, but each has a distinct fault address. The stacked faulted exception format/vector word identifies the type of faulted exception and the contents of the remainder of the frame. A fault address corresponding to the vector specified in the stacked format/vector word indicates that the processor could not obtain the address of the exception handler. A bus error exception handler should execute RTE after correcting a fault. RTE restores the internal machine state, fetches the address of the original exception handler, recreates the original exception stack frame, and resumes execution at the exception handler address. If the fault is intractable, the exception handler should rewrite the faulted exception stack frame at SP + $14 + $06 and then jump directly to the original exception handler. The stack frame can be generated from the information in the bus error frame: the preexception SR (SP + $0C), the format/vector word (SP + $0E), and, if the frame being written is a six-word frame, the PC of the instruction causing the exception (SP + $10). The return PC value is available at SP + $02. A stacked fault address equal to the current SP may indicate that, although the first exception received a bus error while stacking, the bus error exception stacking successfully completed. This occurrence is extremely improbable, but the CPU32 supports recovery from it. Once the exception handler determines that the fault has been corrected, recovery can proceed as described previously. If the fault cannot be corrected, move the supervisor stack to another area of memory, copy all valid stack frames to the new stack, create a faulted exception frame on top of the stack, and resume execution at the exception handler address.
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5.5.4 CPU32 Stack Frames
The CPU32 generates three different stack frames: four-word frames, six-word frames, and twelve-word bus error frames. 5.5.4.1 FOUR-WORD STACK FRAME. This stack frame is created by interrupt, format error, TRAP #n, illegal instruction, A-line and F-line emulator trap, and privilege violation exceptions. Depending on the exception type, the PC value is either the address of the next instruction to be executed or the address of the instruction that caused the exception (see Figure 5-12).
15 SP +$02 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW +$06 0 0 0 0 VECTOR OFFSET 0
Figure 5-12. Format $0--Four-Word Stack Frame 5.5.4.2 SIX-WORD STACK FRAME. This stack frame (see Figure 5-13) is created by instruction-related traps, which include CHK, CHK2, TRAPcc, TRAPV, and divide-by-zero, and by trace exceptions. The faulted instruction PC value is the address of the instruction that caused the exception. The next PC value (the address to which RTE returns) is the address of the next instruction to be executed.
15 0 STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW
SP +$02 +$06 +$08
0 0 1
0
VECTOR OFFSET
FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW
Figure 5-13. Format $2--Six-Word Stack Frame Hardware breakpoints also utilize this format. The faulted instruction PC value is the address of the instruction executing when the breakpoint was sensed. Usually this is the address of the instruction that caused the breakpoint, but, because released writes can overlap following instructions, the faulted instruction PC may point to an instruction following the instruction that caused the breakpoint. The address to which RTE returns is the address of the next instruction to be executed. 5.5.4.3 BUS ERROR STACK FRAME. This stack frame is created when a bus cycle fault is detected. The CPU32 bus error stack frame differs significantly from the equivalent stack frames of other M68000 Family members. The only internal machine state required in the CPU32 stack frame is the bus controller state at the time of the error and a single register.
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Bus operation in progress at the time of a fault is conveyed by the SSW.
15 TP 14 MV 13 0 12 TR 11 B1 10 B0 9 RR 8 RM 7 IN 6 RW 5 LG 4 SIZ 3 2 1 FUNC 0
The bus error stack frame is 12 words in length. There are three variations of the frame, each distinguished by different values in the SSW TP and MV fields. An internal transfer count register appears at location SP + $14 in all bus error stack frames. The register contains an 8-bit microcode revision number, and, for type III faults, an 8-bit transfer count. Register format is shown in Figure 5-14.
15 MICROCODE REVISION NUMBER 87 TRANSFER COUNT 0
Figure 5-14. Internal Transfer Count Register The microcode revision number is checked before a bus error stack frame is restored via RTE. In a multiprocessor system, this check ensures that a processor using stacked information is at the same revision level as the processor that created it. The transfer count is ignored unless the MV bit in the stacked SSW is set. If the MV bit is set, the least significant byte of the internal register is reloaded into the MOVEM transfer counter during RTE execution. For faults occurring during normal instruction execution (both prefetches and non-MOVEM operand accesses), SSW TP,MV = 00. Stack frame format is shown in Figure 5-15. Faults that occur during the operand portion of the MOVEM instruction are identified by SSW TP,MV = 01. Stack frame format is shown in Figure 5-16. When a bus error occurs during exception processing, SSW TP,MV = 10. The frame shown in Figure 5-17 is written below the faulting frame. Stacking begins at the address pointed to by SP - 6 (SP value is the value before initial stacking on the faulted frame). The frame can have either four or six words, depending on the type of error. Four-word stack frames do not include the faulted instruction PC. (The internal transfer count register is located at SP + $10 and the SSW is located at SP + $12.) The fault address of a dynamically sized bus cycle is the address of the upper byte, regardless of the byte that caused the error.
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15 SP +$02 STATUS REGISTER RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW +$06 +$08 1 1 0 0 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C DBUF HIGH DBUF LOW +$10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW +$14 +$16 0 0 INTERNAL TRANSFER COUNT REGISTER SPECIAL STATUS WORD
0
Figure 5-15. Format $C--BERR Stack for Prefetches and Operands
15 SP +$02 STATUS REGISTER RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW +$06 +$08 1 1 0 0 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C DBUF HIGH DBUF LOW +$10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW +$14 +$16 0 1 INTERNAL TRANSFER COUNT REGISTER SPECIAL STATUS WORD
0
Figure 5-16. Format $C--BERR Stack on MOVEM Operand
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15 SP +$02 STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW +$06 +$08 1 1 0 0 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C PRE-EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMAT/VECTOR WORD +$10 FAULTED INSTRUCTION PROGRAM COUNTER HIGH (SIX WORD FRAME ONLY) FAULTED INSTRUCTION PROGRAM COUNTER LOW (SIX WORD FRAME ONLY) +$14 +$16 1 0 INTERNAL TRANSFER COUNT REGISTER SPECIAL STATUS WORD
0
Figure 5-17. Format $C--Four- and Six-Word BERR Stack
5.6 DEVELOPMENT SUPPORT
All M68000 family members have the following special features that facilitate applications development. Trace on Instruction Execution--All M68000 processors include an instruction-byinstruction tracing facility to aid in program development. The MC68020, MC68030, and CPU32 can also trace those instructions that change program flow. In trace mode, an exception is generated after each instruction is executed, allowing a debugger program to monitor execution of a program under test. See 5.5.2.10 Tracing for more information. Breakpoint Instruction--An emulator can insert software breakpoints into target code to indicate when a breakpoint occurs. On the MC68010, MC68020, MC68030, and CPU32, this function is provided via illegal instructions ($4848-$484F) that serve as breakpoint instructions. See 5.5.2.5 Software Breakpoints for more information. Unimplemented Instruction Emulation--When an attempt is made to execute an illegal instruction, an illegal instruction exception occurs. Unimplemented instructions (F-line, Aline) utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software. See 5.5.2.8 Illegal or Unimplemented Instructions for more information.
5.6.1 CPU32 Integrated Development Support
In addition to standard MC68000 family capabilities, the CPU32 has features to support advanced integrated system development. These features include background debug mode, deterministic opcode tracking, hardware breakpoints, and internal visibility in a single-chip environment.
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5.6.1.1 BACKGROUND DEBUG MODE (BDM) OVERVIEW. Microprocessor systems generally provide a debugger, implemented in software, for system analysis at the lowest level. The BDM on the CPU32 is unique because the debugger is implemented in CPU microcode. BDM incorporates a full set of debug options--registers can be viewed and/or altered, memory can be read or written, and test features can be invoked. A resident debugger simplifies implementation of an in-circuit emulator. In a common setup (see Figure 5-18), emulator hardware replaces the target system processor. A complex, expensive pod-and-cable interface provides a communication path between target system and emulator.
IN-CIRCUIT EMULATOR
.. .
TARGET SYSTEM
TARGET MCU
Figure 5-18. In-Circuit Emulator Configuration By contrast, an integrated debugger supports use of a bus state analyzer (BSA) for incircuit emulation. The processor remains in the target system (see Figure 5-19), and the interface is simplified. The BSA monitors target processor operation and the on-chip debugger controls the operating environment. Emulation is much closer to target hardware; thus, many interfacing problems (i.e., limitations on high-frequency operation, AC and DC parametric mismatches, and restrictions on cable length) are minimized.
TARGET SYSTEM TARGET MCU BUS STATE ANALYZER
.
Figure 5-19. Bus State Analyzer Configuration 5.6.1.2 DETERMINISTIC OPCODE TRACKING OVERVIEW. CPU32 function code outputs are augmented by three supplementary signals that monitor the instruction pipeline. The IFETCH output signal identifies bus cycles in which data is loaded into the pipeline and signals pipeline flushes. The IPIPE output signals indicate when each midinstruction pipeline advance occurs and when instruction execution begins. These signals allow a BSA to synchronize with instruction stream activity. Refer to 5.6.3 Deterministic Opcode Tracking for complete information.
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5.6.1.3 ON-CHIP HARDWARE BREAKPOINT OVERVIEW. An external breakpoint input and an on-chip hardware breakpoint capability permit breakpoint trap on any memory access. Off-chip address comparators will not detect breakpoints on internal accesses unless show cycles are enabled. Breakpoints on prefetched instructions, which are flushed from the pipeline before execution, are not acknowledged, but operand breakpoints are always acknowledged. Acknowledged breakpoints can initiate either exception processing or BDM. See 5.5.2.6 Hardware Breakpoints for more information.
5.6.2 Background Debug Mode
BDM is an alternate CPU32 operating mode. During BDM, normal instruction execution is suspended, and special microcode performs debugging functions under external control. Figure 5-20 is a BDM block diagram. BDM can be initiated in several ways--by externally generated breakpoints, by internal peripheral breakpoints, by the background instruction (BGND), or by catastrophic exception conditions. While in BDM, the CPU32 ceases to fetch instructions via the parallel bus and communicates with the development system via a dedicated, high-speed, SPI-type serial command interface.
SERIAL INTERFACE
IPIPE/DSO MICROCODE SEQUENCER IFETCH/DSI
IRC
IRB
IR
BERR BKPT
BERR BKPT
BERR BKPT
BKPT/DSCLK BUS CONTROL DATA BUS BERR
EXECUTION UNIT
. . ...
FREEZE ADDRESS BUS
Figure 5-20. BDM Block Diagram 5.6.2.1 ENABLING BDM. Accidentally entering BDM in a nondevelopment environment could lock up the CPU32 since the serial command interface would probably not be available. For this reason, BDM is enabled during reset via the BKPT signal.
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BDM operation is enabled when BKPT is asserted (low) at the rising edge of RESET. BDM remains enabled until the next system reset. A high BKPT on the trailing edge of RESET disables BDM. BKPT is relatched on each rising transition of RESET. BKPT is synchronized internally and must be held low for at least two clock cycles prior to negation of RESET . BDM enable logic must be designed with special care. If hold time on BKPT (after the trailing edge of RESET) extends into the first bus cycle following reset, this bus cycle could be tagged with a breakpoint. Refer to Section 3 Bus Operation for timing information. 5.6.2.2 BDM SOURCES. When BDM is enabled, any of several sources can cause the transition from normal mode to BDM. These sources include external BKPT hardware, the BGND instruction, a double bus fault, and internal peripheral breakpoints. If BDM is not enabled when an exception condition occurs, the exception is processed normally. Table 5-19 summarizes the processing of each source for both enabled and disabled cases. Note that the BKPT instruction never causes a transition into BDM. Table 5-19. BDM Source Summary
Source BKPT Double Bus Fault BGND Instruction BKPT Instruction BDM Enabled Background Background Background Opcode Substitution/ Illegal Instruction Halted Illegal Instruction Opcode Substitution/ Illegal Instruction BDM Disabled Breakpoint Exception
5.6.2.2.1 External BKPT Signal . Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has the same timing relationship to the data strobe trailing edge as read cycle data. There is no breakpoint acknowledge bus cycle when BDM is entered. 5.6.2.2.2 BGND Instruction. An illegal instruction, $4AFA, is reserved for use by development tools. The CPU32 defines $4AFA (BGND) to be a BDM entry point when BDM is enabled. If BDM is disabled, an illegal instruction trap is acknowledged. Illegal instruction traps are discussed in 5.5.2.8 Illegal or Unimplemented Instructions. 5.6.2.2.3 Double Bus Fault. The CPU32 normally treats a double bus fault (two bus faults in succession) as a catastrophic system error and halts. When this condition occurs during initial system debug (a fault in the reset logic), further debugging is impossible until the problem is corrected. In BDM, the fault can be temporarily bypassed so that its origin can be isolated and eliminated. 5.6.2.3 ENTERING BDM. When the processor detects a BKPT or a double bus fault or decodes a BGND instruction, it suspends instruction execution and asserts the FREEZE output. FREEZE assertion is the first indication that the processor has entered BDM. Once
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FREEZE has been asserted, the CPU enables the serial communication hardware and awaits a command. The CPU writes a unique value indicating the source of BDM transition into temporary register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP and determine the source (see Table 5-20) by issuing a read system register command (RSREG). ATEMP is used in most debugger commands for temporary storage--it is imperative that the RSREG command be the first command issued after transition into BDM. Table 5-20. Polling the BDM Entry Source
Source Double Bus Fault BGND Instruction ATEMP 31-16 SSW* $0000 ATEMP 15-0 $FFFF $0001 $0000
Hardware Breakpoint $0000 *SSW is described in detail in 5.5.3 Fault Recovery.
A double bus fault during initial SP/PC fetch sequence is distinguished by a value of $FFFFFFFF in the current instruction PC. At no other time will the processor write an odd value into this register. 5.6.2.4 COMMAND EXECUTION. Figure 5-21 summarizes BDM command execution. Commands consist of one 16-bit operation word and can include one or more 16-bit extension words. Each incoming word is read as it is assembled by the serial interface. The microcode routine corresponding to a command is executed as soon as the command is complete. Result operands are loaded into the output shift register to be shifted out as the next command is read. This process is repeated for each command until the CPU returns to normal operating mode. 5.6.2.5 BDM REGISTERS. BDM processing uses three special-purpose registers to track program context during development. A description of each register follows. 5.6.2.5.1 Fault Address Register (FAR). The FAR contains the address of the faulting bus cycle immediately following a bus or address error. This address remains available until overwritten by a subsequent bus cycle. Following a double bus fault, the FAR contains the address of the last bus cycle. The address of the first fault (if one occurred) is not visible to the user. 5.6.2.5.2 Return Program Counter (RPC). The RPC points to the location where fetching will commence after transition from BDM to normal mode. This register should be accessed to change the flow of a program under development. Changing the RPC to an odd value will cause an address error when normal mode prefetching begins. 5.6.2.5.3 Current Instruction Program Counter (PCC). The PCC holds a pointer to the first word of the last instruction executed prior to transition into BDM. Due to instruction pipelining, the instruction pointed to may not be the instruction that caused the transition. An example is a breakpoint on a released write. The bus cycle may overlap as many as two subsequent instructions before stalling the instruction sequencer. A BKPT asserted
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during this cycle will not be acknowledged until the end of the instruction executing at completion of the bus cycle. PCC will contain $00000001 if BDM is entered via a double bus fault immediately out of reset.
CPU32 ACTIVITY ENTER (BDM) * ASSERT FREEZE SIGNAL * WAIT FOR COMMAND DEVELOPMENT SYSTEM ACTIVITY
.
SEND INITIAL COMMAND * LOAD COMMAND REGISTER * ENABLE SHIFT CLOCK * SHIFT OUT 17 BITS * DISABLE SHIFT CLOCK
EXECUTE COMMAND
* LOAD: NOT READY/ RESPONSE * PERFORM COMMAND * STORE RESULTS READ RESULTS/NEW COMMAND * LOAD COMMAND REGISTER * ENABLE SHIFT CLOCK * SHIFT IN/OUT 17 BITS * DISABLE SHIFT CLOCK * READ RESULT REGISTER
IF RESULTS = "NOT READY"
YES
NO CONTINUE
Figure 5-21. BDM Command Execution Flowchart 5.6.2.6 RETURNING FROM BDM. BDM is terminated when a resume execution (GO) or call user code (CALL) command is received. Both GO and CALL flush the instruction pipeline and prefetch instructions from the location pointed to by the RPC. The return PC and the memory space referred to by the SR SUPV bit reflect any changes made during BDM. FREEZE is negated prior to initiating the first prefetch. Upon negation of FREEZE, the serial subsystem is disabled, and the signals revert to IPIPE and IFETCH functionality. 5.6.2.7 SERIAL INTERFACE. Communication with the CPU32 during BDM occurs via a dedicated serial interface, which shares pins with other development features. The BKPT signal becomes the DSCLK; DSI is received on IFETCH , and DSO is transmitted on IPIPE.
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The serial interface uses a full-duplex synchronous protocol similar to the serial peripheral interface (SPI) protocol. The development system serves as the master of the serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from the CPU32 system clock, development system serial logic is unhindered by the operating frequency of the target processor. Operable frequency range of the serial clock is from DC to one-half the processor system clock frequency. The serial interface operates in full-duplex mode--i.e., data is transmitted and received simultaneously by both master and slave devices. In general, data transitions occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data is transmitted MSB first and is latched on the rising edge of DSCLK. The serial data word is 17 bits wide--16 data bits and a status/control (S/C) bit.
16 S/C 15 DATA FIELD 0
Bit 16 indicates the status of CPU-generated messages as listed in Table 5-21. Table 5-21. CPU Generated Message Encoding
Encoding 0 0 1 1 1 Data xxxx FFFF 0000 0001 FFFF Valid Data Transfer Command Complete; Status OK Not Ready with Response; Come Again BERR Terminated Bus Cycle; Data Invalid Illegal Command Message Type
Command and data transfers initiated by the development system should clear bit 16. The current implementation ignores this bit; however, Motorola reserves the right to use this bit for future enhancements. 5.6.2.7.1 CPU Serial Logic. CPU serial logic, shown in the left-hand portion of Figure 522, consists of transmit and receive shift registers and of control logic that includes synchronization, serial clock generation circuitry, and a received bit counter. Both DSCLK and DSI are synchronized to on-chip clocks, thereby minimizing the chance of propagating metastable states into the serial state machine. Data is sampled during the high phase of CLKOUT. At the falling edge of CLKOUT, the sampled value is made available to internal logic. If there is no synchronization between CPU32 and development system hardware, the minimum hold time on DSI with respect to DSCLK is one full period of CLKOUT.
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CPU INSTRUCTION REGISTER BUS 16 RCV DATA LATCH 0
.
DEVELOPMENT SYSTEM DATA 16
COMMAND LATCH
SERIAL IN PARALLEL OUT
DSI
PARALLEL IN SERIAL OUT
DSO
PARALLEL IN SERIAL OUT
SERIAL IN PARALLEL OUT
16 STATUS EXECUTION UNIT SYNCHRONIZE MICROSEQUENCER STATUS RESULT LATCH 16 DATA
CONTROL LOGIC
DSCLK
CONTROL LOGIC
SERIAL CLOCK
Figure 5-22. Debug Serial I/O Block Diagram The serial state machine begins a sequence of events based on the rising edge of the synchronized DSCLK (see Figure 5-23). Synchronized serial data is transferred to the input shift register, and the received bit counter is decremented. One-half clock period later, the output shift register is updated, bringing the next output bit to the DSO signal. DSO changes relative to the rising edge of DSCLK and does not necessarily remain stable until the falling edge of DSCLK. One clock period after the synchronized DSCLK has been seen internally, the updated counter value is checked. If the counter has reached zero, the receive data latch is updated from the input shift register. At this same time, the output shift register is reloaded with the "not ready/come again" response. Once the receive data latch has been loaded, the CPU is released to act on the new data. Response data overwrites the "not ready" response when the CPU has completed the current operation. Data written into the output shift register appears immediately on the DSO signal. In general, this action changes the state of the signal from a high ("not ready" response status bit) to a low (valid data status bit) logic level. However, this level change only occurs if the command completes successfully. Error conditions overwrite the "not ready" response with the appropriate response that also has the status bit set.
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CLKOUT
FREEZE
DSCLK
DSI
SAMPLE WINDOW INTERNAL SYNCHRONIZED DSCLK INTERNAL SYNCHRONIZED DSI DSO
.
CLKOUT
Figure 5-23. Serial Interface Timing Diagram A user can use the state change on DSO to signal hardware that the next serial transfer may begin. A timeout of sufficient length to trap error conditions that do not change the state of DSO should also be incorporated into the design. Hardware interlocks in the CPU prevent result data from corrupting serial transfers in progress. 5.6.2.7.2 Development System Serial Logic. The development system, as the master of the serial data link, must supply the serial clock. However, normal and BDM operations could interact if the clock generator is not properly designed. Breakpoint requests are made by asserting BKPT to the low state in either of two ways. The primary method is to assert BKPT during a single bus cycle for which an exception is desired. Another method is to assert BKPT, then continue to assert it until the CPU32 responds by asserting FREEZE. This method is useful for forcing a transition into BDM when the bus is not being monitored. Each method requires a slightly different serial logic design to avoid spurious serial clocks. Figure 5-24 represents the timing required for asserting BKPT during a single bus cycle.
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SHIFT_CLK FORCE_BGND BKPT_TAG
. . .... .. . . . . .. . . . .
BKPT
FREEZE
Figure 5-24.
BKPT
Timing for Single Bus Cycle
Figure 5-25 depicts the timing of the BKPT /FREEZE method. In both cases, the serial clock is left high after the final shift of each transfer. This technique eliminates the possibility of accidentally tagging the prefetch initiated at the conclusion of a BDM session. As mentioned previously, all timing within the CPU is derived from the rising edge of the clock; the falling edge is effectively ignored.
SHIFT_CLK FORCE_BGND BKPT_TAG BKPT
. . .... .. . . . . .. . . . .. .
FREEZE
Figure 5-25.
BKPT
Timing for Forcing BDM
Figure 5-26 represents a sample circuit providing for both BKPT assertion methods. As the name implies, FORCE_BGND is used to force a transition into BDM by the assertion of BKPT . FORCE_BGND can be a short pulse or can remain asserted until FREEZE is asserted. Once asserted, the set-reset latch holds BKPT low until the first SHIFT_CLK is applied.
BKPT_TAG
...
SHIFT_CLK S1 RESET S2 R
BKPT
BKPT/DSCLK Q
FORCE_BGND
Q
Figure 5-26.
/DSCLK Logic Diagram
BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32 as the first DSCLK.
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DSCLK, the gated serial clock, is normally high, but it pulses low for each bit to be transferred. At the end of the seventeenth clock period, it remains high until the start of the next transmission. Clock frequency is implementation dependent and may range from DC to the maximum specified frequency. Although performance considerations might dictate a hardware implementation, software solutions can be used provided serial bus timing is maintained. 5.6.2.8 COMMAND SET. The following paragraphs describe the command set available in BDM. 5.6.2.8.1 Command Format. The following standard bit command format is utilized by all BDM commands.
15 OPERATION 10 9 0 8 R/W 7 6 5 0 4 0 3 A/D 2 REGISTER 0
OP SIZE
EXTENSION WORD(S)
Bits 15-10--Operation Field The operation field specifies the commands. This 6-bit field provides for a maximum of 64 unique commands. R/W Field The R/W field specifies the direction of operand transfer. When the bit is set, the transfer is from theCPU to the development system. When the bit is cleared, data is written to the CPU or to memory from the development system. Operand Size For sized operations, this field specifies the operand data size. All addresses are expressed as 32-bit absolute values. The size field is encoded as listed in Table 5-22. Table 5-22. Size Field Encoding
Encoding 00 01 10 11 Operand Size Byte Word Long Reserved
Address/Data (A/D) Field The A/D field is used by commands that operate on address and data registers. It determines whether the register field specifies a data or address register. One indicates an address register; zero indicates a data register. For other commands, this field may be interpreted differently. Register Field: In most commands, this field specifies the register number for operations performed on an address or data register.
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Extension Word(s) (as required): At this time, no command requires an extension word to specify fully the operation to be performed, but some commands require extension words for addresses or immediate data. Addresses require two extension words because only absolute long addressing is permitted. Immediate data can be either one or two words in length--byte and word data each require a single extension word; long-word data requires two words. Both operands and addresses are transferred most significant word first. 5.6.2.8.2 Command Sequence Diagram. A command sequence diagram (see Figure 527) illustrates the serial bus traffic for each command. Each bubble in the diagram represents a single 17-bit transfer across the bus. The top half in each diagram corresponds to the data transmitted by the development system to the CPU; the bottom half corresponds to the data returned by the CPU in response to the development system commands. Command and result transactions are overlapped to minimize latency. The cycle in which the command is issued contains the development system command mnemonic (in this example, "read memory location"). During the same cycle, the CPU responds with either the lowest order results of the previous command or with a command complete status (if no results were required). During the second cycle, the development system supplies the high-order 16 bits of the memory address. The CPU returns a "not ready" response unless the received command was decoded as unimplemented, in which case the response data is the illegal command encoding. If an illegal command response occurs, the development system should retransmit the command. NOTE The "not ready" response can be ignored unless a memory bus cycle is in progress. Otherwise, the CPU can accept a new serial transfer with eight system clock periods. In the third cycle, the development system supplies the low-order 16 bits of a memory address. The CPU always returns the "not ready" response in this cycle. At the completion of the third cycle, the CPU initiates a memory read operation. Any serial transfers that begin while the memory access is in progress return the "not ready" response. Results are returned in the two serial transfer cycles following the completion of memory access. The data transmitted to the CPU during the final transfer is the opcode for the following command. Should a memory access generate either a bus or address error, an error status is returned in place of the result data.
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COMMANDS TRANSMITTED TO THE CPU32 COMMAND CODE TRANSMITTED DURING THIS CYCLE HIGH-ORDER 16 BITS OF MEMORY ADDRESS LOW-ORDER 16 BITS OF MEMORY ADDRESS NONSERIAL-RELATED ACTIVITY SEQUENCE TAKEN IF OPERATION HAS NOT COMPLETED READ MEMORY LOCATION NEXT COMMAND CODE NEXT CMD LS RESULT NEXT CMD "NOT READY"
READ (LONG) ???
MS ADDR "NOT READY" XXX "ILLEGAL"
LS ADDR "NOT READY" NEXT CMD "NOT READY"
XXX "NOT READY" XXX XXX MS RESULT XXX BERR/AERR
DATA UNUSED FROM THIS TRANSFER SEQUENCE TAKEN IF ILLEGAL COMMAND IS RECEIVED BY CPU32 RESULTS FROM PREVIOUS COMMAND RESPONSES FROM THE CPU
. . .... .. . . . . .. . . . .. .. .. .
SEQUENCE TAKEN IF BUS ERROR OR ADDRESS ERROR OCCURS ON MEMORY ACCESS HIGH- AND LOW-ORDER 16 BITS OF RESULT
Figure 5-27. Command Sequence Diagram 5.6.2.8.3 Command Set Summary. The BDM command set is summarized in Table 5-23. Subsequent paragraphs contain detailed descriptions of each command.
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Table 5-23. BDM Command Summary
Command Read A/D Register Write A/D Register Read System Register Write System Register Read Memory Location Mnemonic RAREG/RDREG Description Read the selected address or data register and return the results via the serial interface .
WAREG/WDREG The data operand is written to the specified address or data register. RSREG WSREG READ The specified system control register is read. All registers that can be read in supervisor mode can be read in BDM. The operand data is written into the specified system control register. Read the sized data at the memory location specified by the longword address. The SFC register determines the address space accessed. Write the operand data to the memory location specified by the long-word address. The DFC register determines the address space accessed. Used in conjunction with the READ command to dump large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. Subsequent operands are retrieved with the DUMP command. Used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. Subsequent operands are written with the FILL command. The pipeline is flushed and refilled before resuming instruction execution at the return PC. Current PC is stacked at the location of the current SP. Instruction execution begins at user patch code. Asserts RESET for 512 clock cycles. The CPU is not reset by this command. Synonymous with the CPU RESET instruction . NOP performs no operation and may be used as a null command.
Write Memory Location
WRITE
Dump Memory Block
DUMP
Fill Memory Block
FILL
Resume Execution Call User Code Reset Peripherals No Operation
GO CALL RST NOP
5.6.2.8.4 Read A/D Register (RAREG/RDREG). Read the selected address or data register and return the results via the serial interface. Command Format:
15 0 14 0 13 1 12 0 11 0 10 0 9 0 8 1 7 1 6 0 5 0 4 0 3 A/D 2 1 REGISTER 0
Command Sequence:
RDREG/RAREG ??? XXX MS RESULT XXX "ILLEGAL" NEXT CMD LS RESULT NEXT CMD "NOT READY"
Operand Data: None
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Result Data: The contents of the selected register are returned as a long-word value. The data is returned most significant word first. 5.6.2.8.5 Write A/D Register (WAREG/WDREG). The operand (long-word) data is written to the specified address or data register. All 32 bits of the register are altered by the write. Command Format:
15 0 14 0 13 1 12 0 11 0 10 0 9 0 8 0 7 1 6 0 5 0 4 0 3 A/D 2 REGISTER 0
Command Sequence:
WDREG/WAREG ??? MS DATA "NOT READY" XXX "ILLEGAL" LS DATA "NOT READY" NEXT CMD "NOT READY" NEXT CMD "CMD COMPLETE"
Operand Data: Long-word data is written into the specified address or data register. The data is supplied most significant word first. Result Data: Command complete status ($0FFFF) is returned when register write is complete. 5.6.2.8.6 Read System Register (RSREG). The specified system control register is read. All registers that can be read in supervisor mode can be read in BDM. Several internal temporary registers are also accessible. Command Format:
15 0 14 0 13 1 12 0 11 0 10 1 9 0 8 0 7 1 6 0 5 0 4 0 3 REGISTER 0
Command Sequence:
RSREG ??? XXX MS RESULT XXX "ILLEGAL" NEXT CMD LS RESULT NEXT CMD "NOT READY"
Operand Data: None
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Result Data: Always returns 32 bits of data, regardless of the size of the register being read. If the register is less than 32 bits, the result is returned zero extended. Register Field: The system control register is specified by the register field (see Table 5-24). Table 5-24. Register Field for RSREG and WSREG
System Register Return Program Counter (RPC) Current Instruction Program Counter (PCC) Status Register (SR) User Stack Pointer (USP) Supervisor Stack Pointer (SSP) Source Function Code Register (SFC) Destination Function Code Register (DFC) Temporary Register A (ATEMP) Fault Address Register (FAR) Vector Base Register (VBR) Select Code 0000 0001 1011 1100 1101 1110 1111 1000 1001 1010
5.6.2.8.7 Write System Register (WSREG). Operand data is written into the specified system control register. All registers that can be written in supervisor mode can be written in BDM. Several internal temporary registers are also accessible. Command Format:
15 0 14 0 13 1 12 0 11 0 10 1 9 0 8 0 7 1 6 0 5 0 4 0 3 REGISTER 0
Command Sequence:
WSREG ??? MS DATA "NOT READY" XXX "ILLEGAL" LS DATA "NOT READY" NEXT CMD "NOT READY" NEXT CMD "CMD COMPLETE"
Operand Data: The data to be written into the register is always supplied as a 32-bit long word. If the register is less than 32 bits, the least significant word is used. Result Data: "Command complete" status is returned when register write is complete.
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Register Field: The system control register is specified by the register field (see Table 5-24). The FAR is a read-only register--any write to it is ignored. 5.6.2.8.8 Read Memory Location (READ). Read the sized data at the memory location specified by the long-word address. Only absolute addressing is supported. The SFC register determines the address space accessed. Valid data sizes include byte, word, or long word. Command Format:
15 0 14 0 13 0 12 1 11 1 10 0 9 0 8 1 7 6 5 0 4 0 3 0 2 0 1 0 0 0
OP SIZE
Command Sequence:
READ (B/W) ???
MS ADDR "NOT READY" XXX "ILLEGAL"
LS ADDR "NOT READY" NEXT CMD "NOT READY"
READ MEMORY LOCATION
XXX "NOT READY" NEXT CMD RESULT XXX BERR/AERR NEXT CMD "NOT READY"
READ (LONG) ???
MS ADDR "NOT READY" XXX "ILLEGAL"
LS ADDR "NOT READY" NEXT CMD "NOT READY"
READ MEMORY LOCATION
XXX "NOT READY" XXX MS RESULT XXX BERR/AERR NEXT CMD LS RESULT NEXT CMD "NOT READY"
Operand Data: The single operand is the long-word address of the requested memory location. Result Data: The requested data is returned as either a word or long word. Byte data is returned in the least significant byte of a word result, with the upper byte cleared. Word results return 16 bits of significant data; long-word results return 32 bits. A successful read operation returns data bit 16 cleared. If a bus or address error is encountered, the returned data is $10001.
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5.6.2.8.9 Write Memory Location (WRITE). Write the operand data to the memory location specified by the long-word address. The DFC register determines the address space accessed. Only absolute addressing is supported. Valid data sizes include byte, word, and long word. Command Format:
15 0 14 0 13 0 12 1 11 1 10 0 9 0 8 0 7 6 5 0 4 0 3 0 2 0 1 0 0 0
OP SIZE
Command Sequence:
WRITE (B/W) ???
MS ADDR "NOT READY" XXX "ILLEGAL"
LS ADDR "NOT READY" NEXT CMD "NOT READY"
DATA "NOT READY"
WRITE MEMORY LOCATION
XXX "NOT READY" XXX NEXT CMD "CMD COMPLETE" XXX BERR/AERR NEXT CMD "NOT READY"
WRITE (LONG) ???
MS ADDR "NOT READY" XXX "ILLEGAL"
LS ADDR "NOT READY" NEXT CMD "NOT READY"
MS DATA "NOT READY"
LS DATA "NOT READY"
WRITE MEMORY LOCATION
XXX "NOT READY" NEXT CMD XXX "CMD COMPLETE" XXX BERR/AERR NEXT CMD "NOT READY"
Operand Data: Two operands are required for this instruction. The first operand is a long-word absolute address that specifies a location to which the operand data is to be written. The second operand is the data. Byte data is transmitted as a 16-bit word, justified in the least significant byte; 16- and 32-bit operands are transmitted as 16 and 32 bits, respectively. Result Data: Successful write operations return a status of $0FFFF. Bus or address errors on the write cycle are indicated by the assertion of bit 16 in the status message and by a data pattern of $0001.
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5.6.2.8.10 Dump Memory Block (DUMP). DUMP is used in conjunction with the READ command to dump large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. Subsequent operands are retrieved with the DUMP command. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent DUMP commands use this address, increment it by the current operand size, and store the updated address back in the temporary register. NOTE The DUMP command does not check for a valid address in the temporary register--DUMP is a valid command only when preceded by another DUMP or by a READ command. Otherwise, the results are undefined. The NOP command can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a DUMP command is given, allowing the operand size to be altered dynamically. Command Format:
15 0 14 0 13 0 12 1 11 1 10 1 9 0 8 1 7 6 5 0 4 0 3 0 2 0 1 0 0 0
OP SIZE
Command Sequence:
DUMP (LONG) ??? READ MEMORY LOCATION XXX "NOT READY" NEXT CMD RESULT XXX BERR/AERR XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "NOT READY"
DUMP (LONG) ???
READ MEMORY LOCATION
XXX "NOT READY" NEXT CMD MS RESULT XXX BERR/AERR XXX "ILLEGAL" NEXT CMR LS RESULT NEXT CMD "NOT READY" NEXT CMD "NOT READY"
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Operand Data: None Result Data: Requested data is returned as either a word or long word. Byte data is returned in the least significant byte of a word result. Word results return 16 bits of significant data; long-word results return 32 bits. Status of the read operation is returned as in the READ command: $0xxxx for success, $10001 for bus or address errors. 5.6.2.8.11 Fill Memory Block (FILL). FILL is used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. Subsequent operands are written with the FILL command. The initial address is incremented by the operand size (1, 2, or 4) and is saved in a temporary register. Subsequent FILL commands use this address, increment it by the current operand size, and store the updated address back in the temporary register. NOTE The FILL command does not check for a valid address in the temporary register--FILL is a valid command only when preceded by another FILL or by a WRITE command. Otherwise, the results are undefined. The NOP command can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a FILL command is given, allowing the operand size to be altered dynamically. Command Format:
15 0 14 0 13 0 12 1 11 1 10 1 9 0 8 0 7 6 5 0 4 0 3 0 2 0 1 0 0 0
OP SIZE
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Command Sequence:
FILL (B/W) ??? MS DATA "NOT READY" XXX "ILLEGAL" LS DATA "NOT READY" NEXT CMD "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" NEXT CMD "CMD COMPLETE" XXX BERR/AERR NEXT CMD "NOT READY"
FILL (LONG) ???
DATA "NOT READY" XXX "ILLEGAL"
WRITE MEMORY LOCATION NEXT CMD "NOT READY"
XXX "NOT READY" NEXT CMD "CMD COMPLETE" XXX BERR/AERR NEXT CMD "NOT READY"
Operand Data: A single operand is data to be written to the memory location. Byte data is transmitted as a 16-bit word, justified in the least significant byte; 16- and 32-bit operands are transmitted as 16 and 32 bits, respectively. Result Data: Status is returned as in the WRITE command: $0FFFF for a successful operation and $10001 for a bus or address error during write. 5.6.2.8.12 Resume Execution (GO). The pipeline is flushed and refilled before normal instruction execution is resumed. Prefetching begins at the return PC and current privilege level. If either the PC or SR is altered during BDM, the updated value of these registers is used when prefetching commences. NOTE The processor exits BDM when a bus error or address error occurs on the first instruction prefetch from the new PC--the error is trapped as a normal mode exception. The stacked value of the current PC may not be valid in this case, depending on the state of the machine prior to entering BDM. For address error, the PC does not reflect the true return PC. Instead, the stacked fault address is the (odd) return PC. Command Format:
15 0 14 0 13 0 12 0 11 1 10 1 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
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Command Sequence:
GO ??? NORMAL MODE XXX "ILLEGAL" NEXT CMD "NOT READY"
Operand Data: None Result Data: None 5.6.2.8.13 Call User Code (CALL). This instruction provides a convenient way to patch user code. The return PC is stacked at the location pointed to by the current SP. The stacked PC serves as a return address to be restored by the RTS command that terminates the patch routine. After stacking is complete, the 32-bit operand data is loaded into the PC. The pipeline is flushed and refilled from the location pointed to by the new PC, BDM is exited, and normal mode instruction execution begins. NOTE If a bus error or address error occurs during return address stacking, the CPU returns an error status via the serial interface and remains in BDM. If a bus error or address error occurs on the first instruction prefetch from the new PC, the processor exits BDM and the error is trapped as a normal mode exception. The stacked value of the current PC may not be valid in this case, depending on the state of the machine prior to entering BDM. For address error, the PC does not reflect the true return PC. Instead, the stacked fault address is the (odd) return PC. Command Format:
15 0 14 0 13 0 12 0 11 1 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
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Command Sequence:
CALL ???
MS ADDR "NOT READY" XXX "ILLEGAL"
LS ADDR "NOT READY" NEXT CMD "NOT READY"
STACK RETURN PC FREEZE NEGATED PREFETCH STARTED NORMAL MODE XXX BERR/AERR NEXT CMD "NOT READY"
Operand Data: The 32-bit operand data is the starting location of the patch routine, which is the initial PC upon exiting BDM. Result Data: None As an example, consider the following code segment. It outputs a character from the MC68341 serial module channel A.
CHKSTAT: MOVE.B BNE.B MOVE.B SRA,D0 CHKSTAT TBA,OUTPUT Move serial status to D0 Loop until condition true Transmit character
MISSING:
ANDI.B RTS
#3,D0
Check for TxEMP flag
BDM and the CALL command can be used to patch the code as follows: 1. 2. 3. 4. 5. 6. Breakpoint user program at CHKSTAT Enter BDM Execute CALL command to MISSING Exit BDM Execute MISSING code Return to user program
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5.6.2.8.14 Reset Peripherals (RST). RST asserts RESET for 512 clock cycles. The CPU is not reset by this command. This command is synonymous with the CPU RESET instruction. Command Format:
15 0 14 0 13 0 12 0 11 0 10 1 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Command Sequence:
RESET ???
ASSERT RESET
XXX "NOT READY" NEXT CMD "CMD COMPLETE"
XXX "ILLEGAL"
NEXT CMD "NOT READY"
Operand Data: None Result Data: The "command complete" response ($0FFFF) is loaded into the serial shifter after negation of RESET. 5.6.2.8.15 No Operation (NOP). NOP performs no operation and may be used as a null command where required. Command Format:
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Command Sequence:
NOP ??? NEXT CMD "CMD COMPLETE" XXX "ILLEGAL" NEXT CMD "NOT READY"
Operand Data: None
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Result Data: The "command complete" response ($0FFFF) is returned during the next shift operation. 5.6.2.8.16 Future Commands. Unassigned command opcodes are reserved by Motorola for future expansion. All unused Comand:formats within any revision level will perform a NOP and return the ILLEGAL command response.
5.6.3 Deterministic Opcode Tracking
The CPU32 utilizes deterministic opcode tracking to trace program execution. Two signals, IPIPE and IFETCH, provide all information required to analyze instruction pipeline operation. 5.6.3.1 INSTRUCTION FETCH (IFETCH) . IFETCH indicates which bus cycles are accessing data to fill the instruction pipeline. IFETCH is pulse-width modulated to multiplex two indications on a single pin. Asserted for a single clock cycle, IFETCH indicates that the data from the current bus cycle is to be routed to the instruction pipeline. IFETCH held low for two clock cycles indicates that the instruction pipeline has been flushed. The data from the bus cycle is used to begin filling the empty pipeline. Both user and supervisor mode fetches are signaled by IFETCH . Proper tracking of bus cycles via IFETCH on a fast bus requires a simple state machine. On a two-clock bus, IFETCH may signal a pipeline flush with associated prefetch followed immediately by a second prefetch. That is, IFETCH remains asserted for three clocks, two clocks indicating the flush/fetch and a third clock signaling the second fetch. These two operations are easily discerned if the tracking logic samples IFETCH on the two rising edges of CLKOUT, which follow the AS (DS during show cycles) falling edge. Three-clock and slower bus cycles allow time for negation of the signal between consecutive indications and do not experience this operation. 5.6.3.2 INSTRUCTION PIPE (IPIPE) . The internal instruction pipeline can be modeled as a three-stage FIFO (see Figure 5-28). Stage A is an input buffer--data can be used out of stages B and C. IPIPE signal s advances of instructions in the pipeline. Instruction register A (IRA) holds incoming words as they are prefetched. No decoding takes place in the buffer. Instruction register B (IRB) provides initial decoding of the opcode and decoding of extension words; it is a source of immediate data. Instruction register C (IRC) supplies residual opcode decoding during instruction execution.
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I DATA BUS R
I R B
I R C
EXTENSION WORDS
OPCODES RESIDUAL
Figure 5-28. Functional Model of Instruction Pipeline Assertion of IPIPE for a single clock cycle indicates the use of data from IRB. Regardless of the presence of valid data in IRA, the contents of IRB are invalidated when IPIPE is asserted. If IRA contains valid data, the data is copied into IRB (IRA IRB), and the IRB stage is revalidated. Assertion of IPIPE for two clock cycles indicates the start of a new instruction and subsequent replacement of data in IRC. This action causes a full advance of the pipeline (IRB IRC and IRA IRB). IRA is refilled during the next instruction fetch bus cycle. Data loaded into IRA propagates automatically through subsequent empty pipeline stages. Signals that show the progress of instructions through IRB and IRC are necessary to accurately monitor pipeline operation. These signals are provided by IRA and IRB validity bits. When a pipeline advance occurs, the validity bit of the stage being loaded is set, and the validity bit of the stage supplying the data is negated. Because instruction execution is not timed to bus activity, IPIPE is synchronized with the system clock, not the bus. Figure 5-29 illustrates the timing in relation to the system clock.
IR IRB IR IRC IR IRB
.. .
IR CLKOUT IPIPE EXTENSION WORD USED
IR
IR
IR
IR IRC
INSTRUCTION START
EXTENSION WORD USED
INSTRUCTION START
Figure 5-29. Instruction Pipeline Timing Diagram IPIPE should be sampled on the falling edge of the clock. The assertion of IPIPE for a single cycle after one or more cycles of negation indicates use of the data in IRB (advance of IRA into IRB). Assertion for two clock cycles indicates that a new instruction has started (IRB IRC and IRA IRB transfers have occurred). Loading IRC always indicates that an instruction is beginning execution--the opcode is loaded into IRC by the transfer. In some cases, instructions using immediate addressing begin executing and initiate a second pipeline advance simultaneously at the same time. IPIPE will not be negated
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between the two indications, which implies the need for a state machine to track the state of IPIPE . The state machine can be resynchronized during periods of inactivity on the signal. 5.6.3.3 OPCODE TRACKING DURING LOOP MODE. IPIPE and IFETCH continue to work normally during loop mode. IFETCH indicates all instruction fetches up through the point that data begins recirculating within the instruction pipeline. IPIPE continues to signal the start of instructions and the use of extension words even though data is being recirculated internally. IFETCH returns to normal operation with the first fetch after exiting loop mode.
5.7 INSTRUCTION EXECUTION TIMING
This section describes the instruction execution timing of the CPU32. External clock cycles are used to provide accurate execution and operation timing guidelines, but not exact timing for every possible circumstance. This approach is used because exact execution time for an instruction or operation depends on concurrence of independently scheduled resources, on memory speeds, and on other variables. An assembly language programmer or compiler writer can use the information in this section to predict the performance of the CPU32. Additionally, timing for exception processing is included so that designers of multitasking or real-time systems can predict task-switch overhead, maximum interrupt latency, and similar timing parameters. Instruction timing is given in clock cycles to eliminate clock frequency dependency.
5.7.1 Resource Scheduling
The CPU32 contains several independently scheduled resources. The organization of these resources within the CPU32 is shown in Figure 5-30. Some variation in instruction execution timing results from concurrent resource utilization. Because resource scheduling is not directly related to instruction boundaries, it is impossible to make an accurate prediction of the time required to complete an instruction without knowing the entire context within which the instruction is executing. 5.7.1.1 MICROSEQUENCER. The microsequencer either executes microinstructions or awaits completion of accesses necessary to continue microcode execution. The microsequencer supervises the bus controller, instruction execution, and internal processor operations such as calculation of EA and setting of condition codes. It also initiates instruction word prefetches after a change of flow and controls validation of instruction words in the instruction pipeline. 5.7.1.2 INSTRUCTION PIPELINE. The CPU32 contains a two-word instruction pipeline where instruction opcodes are decoded. Each stage of the pipeline is initially filled under microsequencer control and subsequently refilled by the prefetch controller as it empties. Stage A of the instruction pipeline is a buffer. Prefetches completed on the bus before stage B empties are temporarily stored in this buffer. Instruction words (instruction
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operation words and all extension words) are decoded at stage B. Residual decoding and execution occur in stage C. Each pipeline stage has an associated status bit that shows whether the word in that stage was loaded with data from a bus cycle that terminated abnormally. 5.7.1.3 BUS CONTROLLER RESOURCES. The bus controller consists of the instruction prefetch controller, the write pending buffer, and the microbus controller. These three resources transact all reads, writes, and instruction prefetches required for instruction execution. The bus controller and microsequencer operate concurrently. The bus controller can perform a read or write or schedule a prefetch while the microsequencer controls EA calculation or sets condition codes. The microsequencer can also request a bus cycle that the bus controller cannot perform immediately. When this happens, the bus cycle is queued, and the bus controller runs the cycle when the current cycle has completed.
MICROSEQUENCER AND CONTROL CONTROL STORE STAGE C
INSTRUCTION PIPELINE STAGE B
CONTROL LOGIC
EXECUTION UNIT PROGRAM COUNTER SECTION DATA SECTION DATA BUS
WRITE-PENDING BUFFER ADDRESS BUS MICROBUS CONTROLLER
PREFETCH CONTROLLER
BUS CONTROL SIGNALS
Figure 5-30. Block Diagram of Independent Resources
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5.7.1.3.1 Prefetch Controller. The instruction prefetch controller receives an initial request from the microsequencer to initiate prefetching at a given address. Subsequent prefetches are initiated by the prefetch controller whenever a pipeline stage is invalidated, either through instruction completion or through use of extension words. Prefetch occurs as soon as the bus is free of operand accesses previously requested by the microsequencer. Additional state information permits the controller to inhibit prefetch requests when a change in instruction flow (e.g., a jump or branch instruction) is anticipated. In a typical program, 10 to 25 percent of the instructions cause a change of flow. Each time a change occurs, the instruction pipeline must be flushed and refilled from the new instruction stream. If instruction prefetches, rather than operand accesses, were given priority, many instruction words would be flushed unused, and necessary operand cycles would be delayed. To maximize available bus bandwidth, the CPU32 will schedule a prefetch only when the next instruction is not a change-of-flow instruction and when there is room in the pipeline for the prefetch. 5.7.1.3.2 Write-Pending Buffer. The CPU32 incorporates a single-operand write-pending buffer. The buffer permits the microsequencer to continue execution after a request for a write cycle is queued in the bus controller. The time needed for a write at the end of an instruction can overlap the head cycle time for the following instruction, thus reducing overall execution time. Interlocks prevent the microsequencer from overwriting the buffer. 5.7.1.3.3 Microbus Controller. The microbus controller performs bus cycles issued by the microsequencer. Operand accesses always have priority over instruction prefetches. Word and byte operands are accessed in a single CPU-initiated bus cycle, although the external bus interface may be required to initiate a second cycle when a word operand is sent to a byte-sized external port. Long operands are accessed in two bus cycles, most significant word first. The instruction pipeline is capable of recognizing instructions that cause a change of flow. It informs the bus controller when a change of flow is imminent, and the bus controller refrains from starting prefetches that would be discarded due to the change of flow. 5.7.1.4 INSTRUCTION EXECUTION OVERLAP. Overlap is the time, measured in clock cycles, that an instruction executes concurrently with the previous instruction. As shown in Figure 5-31, portions of instructions A and B execute simultaneously, reducing total execution time. Because portions of instructions B and C also overlap, overall execution time for all three instructions is also reduced. Each instruction contributes to the total overlap time. The portion of execution time at the end of instruction A that can overlap the beginning of instruction B is called the tail of instruction A. The portion of execution time at the beginning of instruction B that can overlap the end of instruction A is called the head of instruction B. The total overlap time between instructions A and B is the smaller tail of A and the head of B.
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INSTRUCTION A
INSTRUCTION B
INSTRUCTION C
OVERLAP
OVERLAP
Figure 5-31. Simultaneous Instruction Execution The execution time attributed to instructions A, B, and C after considering the overlap is illustrated in Figure 5-32. The overlap time is attributed to the execution time of the completing instruction. The following equation shows the method for calculating the overlap time: Overlap = min (Tail N, HeadN+1 )
INSTRUCTION A
INSTRUCTION B
INSTRUCTION C
OVERLAP PERIOD (ABSORBED BY INSTRUCTION A)
OVERLAP PERIOD (ABSORBED BY INSTRUCTION B)
Figure 5-32. Attributed Instruction Times 5.7.1.5 EFFECTS OF WAIT STATES. The CPU32 access time for on-chip peripherals is two clocks. While two-clock external accesses are possible when the bus is operated in a synchronous mode, a typical external memory speed is three or more clocks. All instruction times listed in this section are for word access only (unless an explicit exception is given), and are based on the assumption that both instruction fetches and operand cycles are to a two-clock memory. Any time a long access is made, time for the additional bus cycle(s) must be added to the overall execution time. Wait states due to slow external memory must be added to the access time for each bus cycle. A typical application has a mixture of bus speeds--program execution from an off-chip ROM, accesses to on-chip peripherals, storage of variables in slow off-chip RAM, and accesses to external peripherals with speeds ranging from moderate to very slow. To arrive at an accurate instruction time calculation, each bus access must be individually
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considered. Many instructions have a head cycle count, which can overlap the cycles of an operand fetch to slower memory started by a previous instruction. In these cases, an increase in access time has no effect on the total execution time of the pair of instructions. To trace instruction execution time by monitoring the external bus, note that the order of operand accesses for a particular instruction sequence is always the same provided bus speed is unchanged and the interleaving of instruction prefetches with operands within each sequence is identical. 5.7.1.6 INSTRUCTION EXECUTION TIME CALCULATION. The overall execution time for an instruction depends on the amount of overlap with previous and subsequent instructions. To calculate an instruction time estimate, the entire code sequence must be analyzed. To derive the actual instruction execution times for an instruction sequence, the instruction times listed in the tables must be adjusted to account for overlap. The formula for this calculation is as follows: C1 - min (T1 , H2 ) + C 2 - min (T2 , H3 ) + C 3 - min (T3 , H4 ) + .. .. . where: CN is the number of cycles listed for instruction N TN is the tail time for instruction N HN is the head time for instruction N min (T N, HM) is the minimum of parameters T N and HM The number of cycles for the instruction (CN) can include one or two EA calculations in addition to the raw number in the cycles column. In these cases, calculate overall instruction time as if it were for multiple instructions, using the following equation: CEA - min (T EA, HOP) + C OP where: CEA is the instruction's EA time COP is the instruction's operation time TEA is the EA's tail time HOP is the instruction operation's head time min (T N, HM) is the minimum of parameters T N and HM The overall head for the instruction is the head for the EA, and the overall tail for the instruction is the tail for the operation. Therefore, the actual equation for execution time becomes: COP1 - min (TOP1 , HEA2 ) + CEA2 - min (TEA2 , HOP2 ) + C OP2 - min (TOP2 , HEA3 ) + . . .
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Every instruction must prefetch to replace itself in the instruction pipe. Usually, these prefetches occur during or after an instruction. A prefetch is permitted to begin in the first clock of any indexed EA mode operation. Additionally, a prefetch for an instruction is permitted to begin two clocks before the end of an instruction provided the bus is not being used. If the bus is being used, then the prefetch occurs at the next available time when the bus would otherwise be idle. 5.7.1.7 EFFECTS OF NEGATIVE TAILS. When the CPU32 changes instruction flow, the instruction decode pipeline must begin refilling before instruction execution can resume. Refilling forces a two-clock idle period at the end of the change-of-flow instruction. This idle period can be used to prefetch an additional word on the new instruction path. Because of the stipulation that each instruction must prefetch to replace itself, the concept of negative tails has been introduced to account for these free clocks on the bus. On a two-clock bus, it is not necessary to adjust instruction timing to account for the potential extra prefetch. The cycle times of the microsequencer and bus are matched, and no additional benefit or penalty is obtained. In the instruction execution time equations, a zero should be used instead of a negative number. Negative tails are used to adjust for slower fetches on slower buses. Normally, increasing the length of prefetch bus cycles directly affects the cycle count and tail values found in the tables. In the following equations, negative tail values are used to negate the effects of a slower bus. The equations are generalized, however, so that they may be used on any speed bus with any tail value.
NEW_TAIL = OLD_TAIL + (NEW_CLOCK - 2) IF ((NEW_CLOCK - 4) > 0) THEN NEW_CYCLE = OLD_CYCLE + (NEW_CLOCK -2) + (NEW_CLOCK - 4) ELSE NEW_CYCLE = OLD_CYCLE + (NEW _CLOCK - 2)
where:
NEW_TAIL/NEW_CYCLE OLD_TAIL/OLD_CYCLE NEW_CLOCK
is the adjusted tail/cycle at the slower speed
is the value listed in the instruction timing tables
is the number of clocks per cycle at the slower speed
Note that many instructions listed as having negative tails are change-of-flow instructions and that the bus speed used in the calculation is that of the new instruction stream.
5.7.2 Instruction Stream Timing Examples
The following programming examples provide a detailed examination of timing effects. In all examples, the memory access is from external synchronous memory, the bus is idle, and the instruction pipeline is full at the start.
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5.7.2.1 TIMING EXAMPLE 1--EXECUTION OVERLAP. Figure 5-33 illustrates execution overlap caused by the bus controller's completion of bus cycles while the sequencer is calculating the next EA. One clock is saved between instructions since that is the minimum time of the individual head and tail numbers. Instructions
MOVE.W ADDQ.W CLR.W
1 CLOCK 2 3 4 5 6 7 8 9 0
A1, (A0) + #1, (A0) $30 (A1)
1 2 3 4 5 6 7 8
BUS CONTROLLER INSTRUCTION CONTROLLER EXECUTION TIME
WRITE FOR 1 MOVE A1,(AO)+
1 PREFETCH
READ FOR 2
WRITE FOR 2 ADDQ TO ADDQ.W #1,(AO)
2 PREFETCH
3 PREFETCH
3 PREFETCH CLR CLR.W $30(A1)
WRITE FOR 3
EA FETCH ADDQ
EA CALC CLR
MOVE.W A1,(AO)+
Figure 5-33. Example 1--Instruction Stream 5.7.2.2 TIMING EXAMPLE 2--BRANCH INSTRUCTIONS. Example 2 shows what happens when a branch instruction is executed for both the taken and not-taken cases. (see Figures 5-34 and 5-35). The instruction stream is for a simple limit check with the variable already in a data register. Instructions
MOVEQ CMP.L BLE.B MOVE.L
1 CLOCK 2 3 4 5 6 7 8 9 0
#7, D1 D1, D0 NEXT D1, (A0)
1 2 3 4
BUS CONTROLLER INSTRUCTION CONTROLLER EXECUTION TIME
1 PREFETCH
2 PREFETCH CMP CMP D1,D0 OFFSET CALC
PREFETCH
PREFETCH TAKEN
PREFETCH TAKEN NEXT INST.
WRITE FOR 3
MOVEQ MOVEQ #7,D1
TAKEN
BLE.B NOT TAKEN
Figure 5-34. Example 2--Branch Taken
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1 CLOCK
2
3
4
5
6
7
8
9
0
1
2
3
4
BUS CONTROLLER INSTRUCTION CONTROLLER EXECUTION TIME
1 PREFETCH MOVEQ MOVEQ #7,D1
2 PREFETCH CMP CMP D1,D0 OFFSET CALC
3 PREFETCH NOT TAKEN
4 PREFETCH MOVE TO (A0)
WRITE FOR 4
WRITE FOR 4
BLE.B NOT TAKEN
MOVE.L D1,(AO)
Figure 5-35. Example 2--Branch Not Taken 5.7.2.3 TIMING EXAMPLE 3--NEGATIVE TAILS. This example (see Figure 5-36) shows how to use negative tail figures for branches and other change-of-flow instructions. In this example, bus speed is assumed to be four clocks per access. Instruction three is at the branch destination. Although the CPU32 has a two-word instruction pipeline, internal delay causes minimum branch instruction time to be three bus cycles. The negative tail is a reminder that an extra two clocks are available for prefetching a third word on a fast bus; on a slower bus, there is no extra time for the third word. Instructions MOVEQ BRA.W MOVE.L
1 CLOCK 2 3 4 5 6 7 8 9 0
#7, D1 FARAWAY D1, D0
1 2 3 4 5 6 7 8 9
BUS CONTROLLER INSTRUCTION CONTROLLER EXECUTION TIME
BRANCH OFFSET OFFSET CALC
FETCH MOVE.L
FETCH NEXT INSTRUCTION TAKEN
PREFETCH MOVE TO D0 MOVE.L D1,D0
MOVEQ
TAKEN
MOVEQ #7,D1
BRA.W FARAWAY
Figure 5-36. Example 3--Branch Negative Tail
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Example 3 illustrates three different aspects of instruction time calculation: 1. The branch instruction does not attempt to prefetch beyond the minimum number of words needed for itself. 2. The negative tail allows execution to begin sooner than a three-word pipeline would allow. 3. There is a one-clock delay due to late arrival of the displacement at the CPU. Only changes of flow require negative tail calculation, but the concept can be generalized to any instruction--only two words are required to be in the pipeline, but up to three words may be present. When there is an opportunity for an extra prefetch, it is made. A prefetch to replace an instruction can begin ahead of the instruction, resulting in a faster processor.
5.7.3 Instruction Timing Tables
The following assumptions apply to the times shown in the subsequent tables: 1. A 16-bit data bus is used for all memory accesses. 2. Memory access times are based on two clock bus cycles with no wait states. 3. The instruction pipeline is full at the beginning of the instruction and is refilled by the end of the instruction. Three values are listed for each instruction and addressing mode: Head: Tail: The number of cycles available at the beginning of an instruction to complete a previous instruction write or to perform a prefetch. The number of cycles an instruction uses to complete a write.
Cycles: Four numbers per entry, three contained in parentheses. The outer number is the minimum number of cycles required for the instruction to complete. Numbers within the parentheses represent the number of bus accesses performed by the instruction. The first number is the number of operand read accesses performed by the instruction. The second number is the number of instruction fetches performed by the instruction, including all prefetches that keep the instruction and the instruction pipeline filled. The third number is the number of write accesses performed by the instruction. As an example, consider an ADD.L (12, A3, D7.W 4), D2 instruction. Paragraph 5.7.3.5 Arithmetic/Logic Instructions shows that the instruction has a head = 0, a tail = 0, and cycles = 2 (0/1/0). However, in indexed address register indirect addressing mode, additional time is required to fetch the EA. Paragraph 5.7.3.1 Fetch Effective Address gives addressing mode data. For (d 8 , An, Xn.Sz Scale), head = 4, tail = 2, cycles = 8 (2/1/0). Because this example is for a long access and the fetch EA table lists data for word accesses, add two clocks to the tail and to the number of cycles ("X" in table notation) to obtain head = 4, tail = 4, cycles = 10 (2/1/0). Assuming that no trailing write exists from the previous instruction, EA calculation requires six clocks. Replacement fetch for the EA occurs during these six clocks, leaving a head of
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four. If there is no time in the head to perform a prefetch due to a previous trailing write, then additional time to perform the prefetches must be allotted in the middle of the instruction or after the tail.
8 (2 /1 /0)
TOTAL NUMBER OF CLOCKS NUMBER OF READ CYCLES NUMBER OF INSTRUCTION ACCESS CYCLES NUMBER OF WRITE CYCLES
The total number of clocks for bus activity is as follows: (2 Reads x 2 Clocks/Read) + (1 Instruction Access x 2 Clocks/Access) + (0 Writes x 2 Clocks/Write) = 6 Clocks of Bus Activity The number of internal clocks (not overlapped by bus activity) is as follows: 10 Clocks Total - 6 Clocks Bus Activity = 4 Internal Clocks Memory read requires two bus cycles at two clocks each. This read time, implied in the tail figure for the EA, cannot be overlapped with the instruction because the instruction has a head of zero. An additional two clocks are required for the ADD instruction itself. The total is 6 + 4 + 2 = 12 clocks. If bus cycles take more time (i.e., the memory is off-chip), add an appropriate number of clocks to each memory access. The instruction sequence MOVE.L D0, (A0) followed by LSL.L #7, D2 provides an example of overlapped execution. The MOVE instruction has a head of zero and a tail of four because it is a long write. The LSL instruction has a head of four. The trailing write from the MOVE overlaps the LSL head completely. Thus, the two-instruction sequence has a head of zero and a tail of zero, and a total execution of 8 rather than 12 clocks. General observations regarding calculation of execution time are as follows: * Any time the number of bus cycles is listed as "X", substitute a value of one for byte and word cycles and a value of two for long cycles. For long bus cycles, usually add a value of two to the tail. * The time calculated for an instruction on a three-clock (or longer) bus is usually longer than the actual execution time. All times shown are for two-clock bus cycles. * If the previous instruction has a negative tail, then a prefetch for the current instruction can begin during the execution of that previous instruction. * Certain instructions requiring an immediate extension word (immediate word EA, absolute word EA, address register indirect with displacement EA, conditional branches with word offsets, bit operations, LPSTOP, TBL, MOVEM, MOVEC, MOVES, MOVEP, MUL.L, DIV.L, CHK2, CMP2, and DBcc) are not permitted to begin until the extension word has been in the instruction pipeline for at least one cycle. This does not apply to long offsets or displacements.
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5.7.3.1 FETCH EFFECTIVE ADDRESS. The fetch EA table indicates the number of clock periods needed for the processor to calculate and fetch the specified EA. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction Dn An (An) (An) + -(An) (d 16 ,An) or (d16 ,PC) (xxx).W (xxx).L #data.B #data.W #data.L (d 8,An,Xn.Sz x Sc) or (d8,PC,Xn.Sz x Sc) (0) (All Suppressed) (d 16 ) (d 32 ) (An) (Xm.Sz x Sc) (An,Xm.Sz x Sc) (d 16 ,An) or (d16 ,PC) (d 32 ,An) or (d32 ,PC) (d 16 ,An,Xm) or (d16 ,PC,Xm) (d 32 ,An,Xm) or (d32 ,PC,Xm) (d 16 ,An,Xm.Sz x Sc) or (d16 ,PC,Xm.Sz x Sc) (d 32 ,An,Xm.Sz x Sc) or (d32 ,PC,Xm.Sz x Sc) Head - - 1 1 2 1 1 1 1 1 1 4 2 1 1 1 4 4 1 1 2 1 2 1 Tail - - 1 1 2 3 3 5 1 1 3 2 2 3 5 1 2 2 3 5 2 3 2 3 Cycles 0(0/0/0) 0(0/0/0) 3(X/0/0) 3(X/0/0) 4(X/0/0) 5(X/1/0) 5(X/1/0) 7(X/2/0) 3(0/1/0) 3(0/1/0) 5(0/2/0) 8(X/1/0) 6(X/1/0) 7(X/2/0) 9(X/3/0) 5(X/1/0) 8(X/1/0) 8(X/1/0) 7(X/2/0) 9(X/3/0) 8(X/2/0) 9(X/3/0) 8(X/2/0) 9(X/3/0) Notes - - 1 1 1 1,3 1 1 1 1 1 1,2,3,4 1,4 1,4 1,4 1,2,4 1,2,4 1,2,3,4 1,3,4 1,3,4 1,3,4 1,3,4 1,2,3,4 1,2,3,4
X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. NOTES: 1. The read of the EA and replacement fetches overlap the head of the operation by the amount specified in the tail. 2. Size and scale of the index register do not affect execution time. 3. The PC may be substituted for the base address register An. 4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts.
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5.7.3.2 CALCULATE EFFECTIVE ADDRESS. The calculate EA table indicates the number of clock periods needed for the processor to calculate a specified EA. The timing is equivalent to fetch EA except there is no read cycle. The tail and cycle time are reduced by the amount of time the read would occupy. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction Dn An (An) (An) + -(An) (d 16 ,An) or (d16 ,PC) (xxx).W (xxx).L (d 8,An,Xn.Sz x Sc) or (d 8,PC,Xn.Sz x Sc) (0) (All Suppressed) (d 16 ) (d 32 ) (An) (Xm.Sz x Sc) (An,Xm.Sz x Sc) (d 16 ,An) or (d16 ,PC) (d 32 ,An) or (d32 ,PC) (d 16 ,An,Xm) or (d16 ,PC,Xm) (d 32 ,An,Xm) or (d32 ,PC,Xm) (d 16 ,An,Xm.Sz x Sc) or (d16 ,PC,Xm.Sz x Sc) (d 32 ,An,Xm.Sz x Sc) or (d32 ,PC,Xm.Sz x Sc) Head - - 1 1 2 1 1 1 4 2 1 1 1 4 4 1 1 2 1 2 1 Tail - - 0 0 0 1 1 3 0 0 1 3 0 0 0 1 3 0 1 0 1 Cycles 0(0/0/0) 0(0/0/0) 2(0/0/0) 2(0/0/0) 2(0/0/0) 3(0/1/0) 3(0/1/0) 5(0/2/0) 6(0/1/0) 4(0/1/0) 5(0/2/0) 7(0/3/0) 4(0/1/0) 6(0/1/0) 6(0/1/0) 5(0/2/0) 7(0/3/0) 6(0/2/0) 7(0/3/0) 6(0/2/0) 7(0/3/0) Notes - - - - - 1,3 1 1 2,3,4 4 1,4 1,4 4 2,4 2,4 1,3,4 1,3,4 3,4 1,3,4 2,3,4 1,2,3,4
X = There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles. NOTES: 1. Replacement fetches overlap the head of the operation by the amount specified in the tail. 2. Size and scale of the index register do not affect execution time. 3. The PC may be substituted for the base address register An. 4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts.
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5.7.3.3 MOVE INSTRUCTION. The MOVE instruction table indicates the number of clock periods needed for the processor to calculate the destination EA and to perform a MOVE or MOVEA instruction. For entries with CEA or FEA, refer to the appropriate table to calculate that portion of the instruction time. Destination EAs are divided by their formats (see 5.3.4.4 Effective Address Encoding Summary). The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. When using this table, begin at the top and move downward. Use the first entry that matches both source and destination addressing modes.
Instruction MOVE MOVE MOVE MOVE MOVE MOVE MOVE MOVE MOVE MOVE MOVE Rn, Rn FEA, Rn Rn, (Am) Rn, (Am) + Rn, -(Am) Rn, CEA FEA, (An) FEA, (An) + FEA, -(An) #, CEA CEA, FEA Head 0 0 0 1 2 1 2 2 2 2 2 Tail 0 0 2 1 2 3 2 2 2 2 2 Cycles 2(0/1/0) 2(0/1/0) 4(0/1/x) 5(0/1/x) 6(0/1/x) 5(0/1/x) 6(0/1/x) 6(0/1/x) 6(0/1/x) 6(0/1/x) 6(0/1/x)
X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. = An # fetch EA time must be added for this instruction: FEA +CEA + OPER NOTE: For instructions not explicitly listed, use the MOVE CEA , FEA entry. The source EA is calculated by the calculate EA table, and the destination EA is calculated by the fetch EA table, even though the bus cycle is for the source EA.
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5.7.3.4 SPECIAL-PURPOSE MOVE INSTRUCTION. The special-purpose MOVE instruction table indicates the number of clock periods needed for the processor to fetch, calculate, and perform the special-purpose MOVE operation on control registers or a specified EA. Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction EXG MOVEC MOVEC MOVE MOVE MOVE MOVE MOVE MOVE MOVE MOVE MOVEM.W MOVEM.W MOVEM.L MOVEM.L MOVEP.W MOVEP.W MOVEP.L MOVEP.L MOVES (Save) MOVES (Op) MOVES (Save) MOVES (Op) MOVE MOVE SWAP Rn, Rm Cr, Rn Rn, Cr CCR, Dn CCR, CEA Dn, CCR FEA, CCR SR, Dn SR, CEA Dn, SR FEA, SR CEA, RL RL, CEA CEA, RL RL, CEA Dn, (d16 , An) (d 16 , An), Dn Dn, (d16 , An) (d 16 , An), Dn CEA, Rn CEA, Rn Rn, CEA Rn, CEA USP, An An, USP Dn Head 2 10 12 2 0 2 0 2 0 4 0 1 1 1 1 2 1 2 1 1 7 1 9 0 0 4 Tail 0 0 0 0 2 0 0 0 2 -2 -2 0 0 0 2 0 2 0 2 1 1 1 2 0 0 0 Cycles 4(0/1/0) 14(0/2/0) 14-16(0/1/0) 4(0/1/0) 4(0/1/1) 4(0/1/0) 4(0/1/0) 4(0/1/0) 4(0/1/1) 10(0/3/0) 10(0/3/0) 8 + n x 4 (n + 1, 2, 0) 8 + n x 4 (0, 2, n) 12 + n x 4(2n + 2, 2, 0) 10 + n x 4 (0, 2, 2n) 10(0/2/2) 11(2/2/0) 14(0/2/4) 19(4/2/0) 3(0/1/0) 11(X/1/0) 3(0/1/0) 12(0/1/X) 2(0/1/0) 2(0/1/0) 6(0/1/0)
X = There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles. = Each bus cycle may take up to four clocks without increasing total execution time. Cr = Control registers USP, VBR, SFC, and DFC n = Number of registers to transfer RL = Register List < = Maximum time (certain data or mode combinations may execute faster). NOTE: The MOVES instruction has an additional save step that other instructions do not have. To calculate the total instruction time, calculate the save, the EA, and the operation execution times, and combine in the order listed, using the equations given in 5.7.1.6 Instruction Execution Time Calculation.
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5.7.3.5 ARITHMETIC/LOGIC INSTRUCTIONS. The arithmetic/logic instruction table indicates the number of clock periods needed to perform the specified arithmetic/logical instruction using the specified addressing mode. Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction ADD(A) ADD(A) ADD AND AND AND EOR EOR OR OR OR SUB(A) SUB(A) SUB CMP(A) CMP(A) CMP2 (Save) * CMP2 (Op) MUL(su).W Rn, Rm FEA, Rn Dn, FEA Dn, Dm FEA, Dn Dn, FEA Dn, Dm Dn, FEA Dn, Dm FEA, Dn Dn, FEA Rn, Rm FEA, Rn Dn, FEA Rn, Rm FEA, Rn FEA, Rn FEA, Rn Head 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 2 2 0 0 1 2 1 2 26 1 6 30 1 6 Tail 0 0 3 0 0 3 0 3 0 0 3 0 0 3 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0 Cycles 2(0/1/0) 2(0/1/0) 5(0/1/x) 2(0/1/0) 2(0/1/0) 5(0/1/x) 2(0/1/0) 5(0/1/x) 2(0/1/0) 2(0/1/0) 5(0/1/x) 2(0/1/0) 2(0/1/0) 5(0/1/x) 2(0/1/0) 2(0/1/0) 3(0/1/0) 16-18(X/1/0) 26(0/1/0) 3(0/1/0) 46-52(0/1/0) 46(0/1/0) 32(0/1/0) 42(0/1/0) 3(0/1/0) <46(0/1/0) 3(0/1/0) <62(0/1/0) 28-30(0/2/0) 3(0/1/0) 33-35(2X/1/0) 30-34(0/2/0) 3(0/1/0) 35-39(2X/1/0)
FEA, Dn * FEA, Dn MUL(su).L (Save) MUL(su).L (Op) MUL(su).L (Op) DIVU.W DIVS.W DIVU.L (Save)* DIVU.L (Op) DIVS.L (Save) * DIVS.L (Op) TBL(su) TBL(su) (Save) * TBL(su) (Op) TBLSN TBLSN (Save)* TBLSN (Op) FEA, Dl FEA, Dn:Dl FEA, Dn FEA, Dn FEA, Dn FEA, Dn FEA, Dn FEA, Dn Dn:Dm, Dp CEA, Dn CEA, Dn Dn:Dm, Dp CEA, Dn CEA, Dn
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Instruction TBLUN TBLUN (Save)* TBLUN (Op) X Dn:Dm, Dp CEA, Dn CEA, Dn
Head 30 1 6
Tail 0 1 0
Cycles 34-40(0/2/0) 3(0/1/0) 39-45(2X/1/0)
= There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles. = Maximum time (certain data or mode combinations may execute faster). = The execution time is identical for signed or unsigned operands.
< su
*These instructions have an additional save operation that other instructions do not have. To calculate total instruction time, calculate save, ea, and operation execution times, then combine in the order listed, using equations in 5.7.1.6 Instruction Execution Time Calculations. A save operation is not run for long-word divide and multiply instructions when FEA = Dn,
5.7.3.6 IMMEDIATE ARITHMETIC/LOGIC INSTRUCTIONS. The immediate arithmetic/logic instruction table indicates the number of clock periods needed for the processor to fetch the source immediate data value and to perform the specified arithmetic/logic instruction using the specified addressing mode. Footnotes indicate when to account for the appropriate fetch effective or fetch immediate EA times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction MOVEQ ADDQ ADDQ SUBQ SUBQ ADDI ADDI ANDI ANDI EORI EORI ORI ORI SUBI SUBI CMPI CMPI X= #, Dn #, Rn #, FEA #, Rn #, FEA #, Rn #, FEA #, Rn #, FEA #, Rn #, FEA #, Rn #, FEA #, Rn #, FEA #, Rn #, FEA Head 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Tail 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 Cycles 2(0/1/0) 2(0/1/0) 5(0/1/x) 2(0/1/0) 5(0/1/x) 2(0/1/0) 5(0/1/x) 2(0/1/0) 5(0/1/x) 2(0/1/0) 5(0/1/x) 2(0/1/0) 5(0/1/x) 2(0/1/0) 5(0/1/x) 2(0/1/0) 5(0/1/x)
There is one bus cycle for byte and word operands and two bus cycles for longword operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. An # fetch EA time must be added for this instruction: FEA +FEA + OPER
=
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5.7.3.7 BINARY-CODED DECIMAL AND EXTENDED INSTRUCTIONS. The BCD and extended instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction ABCD ABCD SBCD SBCD ADDX ADDX SUBX SUBX CMPM Dn, Dm -(An), -(Am) Dn, Dm -(An), -(Am) Dn, Dm -(An), -(Am) Dn, Dm -(An), -(Am) (An)+, (Am)+ Head 2 2 2 2 0 2 0 2 1 Tail 0 2 0 2 0 2 0 2 0 Cycles 4(0/1/0) 12(2/1/1) 4(0/1/0) 12(2/1/1) 2(0/1/0) 10(2/1/1) 2(0/1/0) 10(2/1/1) 8(2/1/0)
5.7.3.8 SINGLE OPERAND INSTRUCTIONS. The single operand instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction CLR CLR NEG NEG NEGX NEGX NOT NOT EXT NBCD NBCD Scc Scc TAS TAS TST X Dn CEA Dn FEA Dn FEA Dn FEA Dn Dn FEA Dn CEA Dn CEA FEA Head 0 0 0 0 0 0 0 0 0 2 0 2 2 4 1 0 Tail 0 2 0 3 0 3 0 3 0 0 2 0 2 0 0 0 Cycles 2(0/1/0) 4(0/1/x) 2(0/1/0) 5(0/1/x) 2(0/1/0) 5(0/1/x) 2(0/1/0) 5(0/1/x) 2(0/1/0) 4(0/1/0) 6(0/1/1) 4(0/1/0) 6(0/1/1) 6(0/1/0) 10(0/1/1) 2(0/1/0)
= There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles.
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5.7.3.9 SHIFT/ROTATE INSTRUCTIONS. The shift/rotate instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. Footnotes indicate when to account for the appropriate EA times. The number of bits shifted does not affect the execution time, unless noted. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction LSd LSd LSd ASd ASd ASd ROd ROd ROd ROXd ROXd ROXd NOTES: 1. Head and cycle times can be derived from the following table or calculated as follows: Max (3 + (n/4) + mod(n,4) + mod (((n/4) + mod (n,4) + 1,2), 6) 2. Head and cycle times are calculated as follows: (count 63): max (3 + n + mod (n + 1,2), 6). 3. Head and cycle times are calculated as follows: (count 8): max (2 + n + mod (n,2), 6). Dn, Dm #, Dm FEA Dn, Dm #, Dm FEA Dn, Dm #, Dm FEA Dn, Dm #, Dm FEA Head -2 4 0 -2 4 0 -2 4 0 -2 -2 0 Tail 0 0 2 0 0 2 0 0 2 0 0 2 Cycles (0/1/0) 6(0/1/0) 6(0/1/1) (0/1/0) 6(0/1/0) 6(0/1/1) (0/1/0) 6(0/1/0) 6(0/1/1) (0/1/0) (0/1/0) 6(0/1/1) Note 1 -- -- 1 -- -- 1 -- -- 2 3 --
d = Direction (left or right)
Clocks 6 8 10 12 14 16 18 20 22 0 7 15 23 31 39 47 55 63 1 10 18 26 34 42 50 58 2 11 19 27 35 43 51 59 3 13 21 29 37 45 53 61
Shift Counts 4 14 22 30 38 46 54 62 5 16 24 32 40 48 56 6 17 25 33 41 49 57 8 20 28 36 44 52 60 9 12
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5.7.3.10 BIT MANIPULATION INSTRUCTIONS. The bit manipulation instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction BCHG BCHG BCHG BCHG BCLR BCLR BCLR BCLR BSET BSET BSET BSET BTST BTST BTST BTST #, Dn Dn, Dm #, FEA Dn, FEA #, Dn Dn, Dm #, FEA Dn, FEA #, Dn Dn, Dm #, FEA Dn, FEA #, Dn Dn, Dm #, FEA Dn, FEA Head 2 4 1 2 2 4 1 2 2 4 1 2 2 2 1 2 Tail 0 0 2 2 0 0 2 2 0 0 2 2 0 0 0 0 Cycles 6(0/2/0) 6(0/1/0) 8(0/2/1) 8(0/1/1) 6(0/2/0) 6(0/1/0) 8(0/2/1) 8(0/1/1) 6(0/2/0) 6(0/1/0) 8(0/2/1) 8(0/1/1) 4(0/2/0) 4(0/1/0) 4(0/2/0) 8(0/1/0)
= An # fetch EA time must be added for this instruction: FEA + FEA + OPER
5.7.3.11 CONDITIONAL BRANCH INSTRUCTIONS. The conditional branch instruction table indicates the number of clock periods needed for the processor to perform the specified branch on the given branch size, with complete execution times given. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction Bcc Bcc.B Bcc.W Bcc.L DBcc DBcc DBcc DBcc DBcc DBcc (taken) (not taken) (not taken) (not taken) (T, not taken) (F, -1, not taken) (F, not -1, taken) (T, not taken) (F, -1, not taken) (F, not -1, taken) Head 2 2 0 0 1 2 6 4 6 6 Tail -2 0 0 0 1 0 -2 0 0 0 Cycles 8(0/2/0) 4(0/1/0) 4(0/2/0) 6(0/3/1) 4(0/2/0) 6(0/2/0) 10(0/2/0) 6(0/1/0) 8(0/1/0) 10(0/0/0)
= In loop mode
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5.7.3.12 CONTROL INSTRUCTIONS. The control instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction ANDI EORI ORI ANDI EORI ORI BSR.B BSR.W BSR.L CHK CHK CHK2 (Save) CHK2 (Op) CHK2 (Save) CHK2 (Op) JMP JSR LEA LINK.W LINK.L NOP PEA RTD RTR RTS UNLK An CEA # FEA, Dn (no ex) FEA, Dn (ex) FEA, Dn (no ex) FEA, Dn (no ex) FEA, Dn (ex) FEA, Dn (ex) CEA CEA CEA, An An, # An, # #, SR #, SR #, SR #, CCR #, CCR #, CCR Head 0 0 0 2 2 2 3 3 1 2 2 1 2 1 2 0 3 0 2 0 0 0 1 1 1 1 Tail -2 -2 -2 0 0 0 -2 -2 -2 0 -2 1 0 1 -2 -2 -2 0 0 0 0 0 -2 -2 -2 0 Cycles 12(0/2/0) 12(0/2/0) 12(0/2/0) 6(0/2/0) 6(0/2/0) 6(0/2/0) 13(0/2/2) 13(0/2/2) 13(0/2/2) 8(0/1/0) 42(2/2/6) 3(0/1/0) 18(X/0/0) 3(0/1/0) 52(X + 2/1/6) 6(0/2/0) 13(0/2/2) 2(0/1/0) 10(0/2/2) 10(0/3/2) 2(0/1/0) 8(0/1/2) 12(2/2/0) 14(3/2/0) 12(2/2/0) 9(2/1/0)
X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. NOTE: The CHK2 instruction involves a save step that other instructions do not have. To calculate the total instruction time, calculate the save, the EA, and the operation execution times, and combine in the order listed using the equations given in 5.7.1.6 Instruction Execution Time Calculation.
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5.7.3.13 EXCEPTION-RELATED INSTRUCTIONS AND OPERATIONS. The exceptionrelated instructions and operations table indicates the number of clock periods needed for the processor to perform the specified exception-related actions. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction BKPT (Acknowledged) BKPT (Bus Error) Breakpoint (Acknowledged) Breakpoint (Bus Error) Interrupt RESET STOP LPSTOP Divide-by-Zero Trace TRAP # ILLEGAL A-line F-line (First word illegal) F-line (Second word illegal) ea = Rn F-line (Second word illegal) ea Rn (Save) F-line (Second word illegal) ea Rn (Op) Privileged TRAPcc (trap) TRAPcc (no trap) TRAPcc.W (trap) TRAPcc.W (no trap) TRAPcc.L (trap) TRAPcc.L (no trap) TRAPV (trap) TRAPV (no trap) Head 0 0 0 0 0 0 2 3 0 0 4 0 0 0 1 1 4 0 2 2 2 0 0 0 2 2 Tail 0 -2 0 -2 -2 0 0 -2 -2 -2 -2 -2 -2 -2 -2 1 -2 -2 -2 0 -2 0 -2 0 -2 0 Cycles 14(1/0/0) 35(3/2/4) 10(1/0/0) 42(3/2/6) 30(3/2/4) 518(0/1/0) 12(0/1/0) 25(0/3/1) 36(2/2/6) 36(2/2/6) 29(2/2/4) 25(2/2/4) 25(2/2/4) 25(2/2/4) 31(2/3/4) 3(0/1/0) 29(2/2/4) 25(2/2/4) 38(2/2/6) 4(0/1/0) 38(2/2/6) 4(0/2/0) 38(2/2/6) 6(0/3/0) 38(2/2/6) 4(0/1/0)
= Minimum interrupt acknowledge cycle time is assumed to be three clocks. NOTE: The F-line (second word illegal) operation involves a save step which other operations do not have. To calculate the total operation time, calculate the save, the calculate EA, and the operation execution times, and combine in the order listed, using the equations given in 5.7.1.6 Instruction Execution Time Calculation.
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5.7.3.14 SAVE AND RESTORE OPERATIONS. The save and restore operations table indicates the number of clock periods needed for the processor to perform the specified state save or return from exception. Complete execution times and stack length are given. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction BERR on instruction BERR on exception RTE (four-word frame) RTE (six-word frame) RTE (BERR on instruction) RTE (BERR on four-word frame) RTE (BERR on six-word frame) Head 0 0 1 1 1 1 1 Tail -2 -2 -2 -2 -2 -2 -2 Cycles <58(2/2/12) 48(2/2/12) 24(4/2/0) 26(4/2/0) 50(12/12/Y) 66(10/2/4) 70(12/2/6)
< = Maximum time is indicated (certain data or mode combinations execute faster). Y = If a bus error occurred during a write cycle, the cycle is rerun by the RTE.
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SECTION 6 DMA CONTROLLER MODULE
The direct memory access (DMA) controller module provides for high-speed transfer capability to/from an external peripheral or for memory-to-memory data transfer. The DMA module, shown in Figure 6-1, provides two channels that allow byte, word, or long-word operand transfers. These transfers can be either single or dual address and to either on- or off-chip devices. The DMA contains the following features: * Two Independent, Fully Programmable DMA Channels * Single-Address Transfers and Dual-Address Transfers * 32-Bit Address and 32-Bit Data Capability * Two 32-Bit Transfer Counters * Four 32-Bit Address Pointers That Can Increment or Remain Constant * Operand Packing and Unpacking for Dual-Address Transfers * Supports All Bus-Termination Modes * Provides Two-Clock-Cycle Internal Module Access * Provides Two-Clock-Cycle External Access Using MC68341 Chip Selects * Provides Full DMA Handshake for Burst Transfers and Cycle Steal * Programmable Interrupt Level Allows Central Processing Unit (CPU) to Preempt DMA Activity
INTERRUPT ARBITRATION DMA HANDSHAKE SIGNALS
DMA CHANNEL 1
SLAVE BIU I M B MASTER BIU
BUS ARBITRATION
DMA CHANNEL 2
DMA HANDSHAKE SIGNALS
.
Figure 6-1. DMA Block Diagram
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6.1 DMA MODULE OVERVIEW
The DMA module is the same as the DMA implemented in the MC68340, with three extra signals added to provide additional handshaking flexibility. Paragraphs 6.1 through 6.9 describe the standard DMA module. The MC68341 additions are described in paragraph 6.10 MC68341 Enhancements. The main purpose of the DMA controller module is to transfer data at very high rates, usually much faster than the CPU32 under software control can handle. The term DMA is used to refer to the ability of a peripheral device to access memory in a system in the same manner as a microprocessor does. DMA operations can greatly increase overall system performance. The DMA module consists of two independent, programmable channels. The term DMA is used throughout this section to reference either channel 1 or channel 2 since the two are functionally equivalent. Each channel has independent request, acknowledge, and done signals. However, both channels cannot own the bus at the same time. Therefore, it is impossible to implicitly address both DMA channels at the same time. The MC68341 onchip peripherals do not support the single-address transfer mode. DMA requests may be internally generated by the channel or externally generated by a device. For an internal request, the amount of bus bandwidth allocated for the DMA can be programmed. The DMA channels support two external request modes: burst mode and cycle steal mode. Each DMA channel has a configurable interrupt service mask (ISM) level which causes the channel to temporarily suspend DMA activity when the CPU interrupt service level exceeds the ISM value. This feature can be used to minimize the effects of DMA activity or timecritical interrupt sources. The DMA controller supports single- and dual-address transfers. In single-address mode, a channel supports 32 bits of address and 32 bits of data. Only an external request can be used to start a transfer in the single-address mode. The DMA provides address and control signals during a single-address transfer. The requesting device either sends or receives data to or from the specified address (see Figure 6-2). In dual-address mode, a channel supports 32 bits of address and 32 bits of data. The dual-address transfers can be started by either the internal request mode or by an external device using the request signal. In this mode, two bus transfers occur, one from a source device and the other to a destination device (see Figure 6-3). In dual-address mode, operands are packed or unpacked according to port sizes and addresses. Any operation involving the DMA will follow the same basic steps: channel initialization, data transfer, and channel termination. In the channel initialization step, the DMA channel registers are loaded with control information, address pointers, and a byte transfer count. The channel is then started. During the data transfer step, the DMA accepts requests for operand transfers and provides addressing and bus control for the transfers. The channel termination step occurs after operation is complete. The channel indicates the status of the operation in the channel status register.
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DMA DMA
MEMORY
DEVICE
MEMORY
PERIPHERAL PERIPHERAL IMPLICIT DEVICE WRITE
MEMORY READ
DMA
DEVICE
MEMORY
PERIPHERAL IMPLICIT DEVICE READ
MEMORY
MEMORY WRITE
.
Figure 6-2. Single-Address Transfers
DEVICE READ OR MEMORY READ PERIPHERAL MEMORY
DMA
PERIPHERAL DEVICE WRITE OR MEMORY WRITE
.. .
MEMORY
Figure 6-3. Dual-Address Transfer
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6.2 DMA MODULE SIGNAL DEFINITIONS
This section contains a brief description of the DMA module signals used to provide handshake control for either a source or destination external device. NOTE The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of activelow and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false.
6.2.1 DMA Request (DREQ1,
DREQ2)
This active-low input is asserted by a peripheral device to request an operand transfer between that peripheral and memory. The assertion of DREQ starts the DMA process. The assertion level in external burst mode is level sensitive; in external cycle steal mode, it is falling-edge sensitive.
6.2.2 DMA Acknowledge (DACK1, DACK2)
This active-low output is asserted by the DMA to signal to a peripheral that an operand is being transferred in response to a previous transfer request.
6.2.3 Ready (RDY1,
RDY2)
This active-low input is asserted by a peripheral device when it is ready to complete the DMA transfer. A slow device can delay assertion of RDY to delay termination of a single address DMA transfer between the device and faster memory. RDY1 and RDY2 are multiplexed with timer signals TGATE and TIN.
6.2.4 DMA Done (DONE1 , DONE2)
This active-low bidirectional signal is asserted by the DMA or a peripheral device during any DMA bus cycle to indicate that the last data transfer is being performed. DONE is an active input in any mode. As an output, DONE is only active in external request mode. An external pullup resistor is required even if operating only in the internal request mode.
6.2.5 Data Transfer Complete (DTC )
This active-low output is asserted for one clock at the end of all MC68341 bus cycles (CPU or DMA) to indicate completion of the cycle. DTC is multiplexed with FC3.
6.3 TRANSFER REQUEST GENERATION
The DMA channel supports two types of request generation methods: internal and external. Internally generated requests can be programmed to limit the amount of bus utilization.
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Externally generated requests can be either burst mode or cycle steal mode. The request generation method used for the channel is programmed by the REQ field in the channel control register (CCR).
6.3.1 Internal Request Generation
The channel is started as soon as the STR bit in the CCR is set. The channel immediately requests the bus and begins transferring data. Only internal requests can limit the amount of bus utilization. The percentage of the bus bandwidth that the DMA channel uses during a transfer is selected by the CCR bus bandwidth (BB) field. 6.3.1.1 INTERNAL REQUEST, MAXIMUM RATE. Internal generation using 100% of the internal bus always has a transfer request pending for the channel until the block transfer is complete. As soon as the channel is started, the DMA will arbitrate for the internal bus and begin to transfer data when it becomes bus master. If no exceptions occur, all operands in the data block will be transferred in one burst so that the DMA will use 100% of the available bus bandwidth. 6.3.1.2 INTERNAL REQUEST, LIMITED RATE. To guarantee that the DMA does not use all of the available bus bandwidth during a transfer, the bus bandwidth allocated to the DMA can be limited. There are three programmed constants in the CCR used to monitor the bus activity and allow the DMA to use a percentage of the bus bandwidth. Options are 25%, 50%, and 75% of 1024 clock periods. See Table 6-5 for more information.
6.3.2 External Request Generation
To control the transfer of operands to or from memory in an orderly manner, a peripheral device uses the DREQ input signal to request service. If the channel is programmed for external request and the CCR STR bit is set, an external request (DREQ) signal must be asserted before the channel requests the bus and begins a transfer. The DMA supports external burst mode and external cycle steal mode. The generation of the request from the source or destination is specified by the ECO bit of the CCR. The external requests can be for either single- or dual-address transfers. 6.3.2.1 EXTERNAL BURST MODE. For external devices that require very high data transfer rates, the burst request mode allows the DMA channel to use all of the bus bandwidth under control of the external device. In burst mode, the DREQ input to the DMA is level sensitive and is sampled at certain points to determine when a valid request is asserted by the device. The device requests service by asserting DREQ and leaving it asserted. In response, the DMA arbitrates for the bus and performs an operand transfer. During each operand transfer, the DMA asserts DMA acknowledge (DACK ) to indicate to the device that a request is being serviced. DACK is asserted on the cycle of either the source or destination device, depending on which one generated the request as programmed by the CCR ECO bit. To allow more than one transfer to be recognized, DREQ must meet the asynchronous setup and hold times while DACK is asserted in the DMA bus cycle. Upon completion of a
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request, DREQ should be held asserted (bursting) into the following DMA bus cycle to allow another transfer to occur. The recognized request will immediately be serviced. If DREQ is negated before DACK is asserted, a new request is not recognized, and the DMA channel releases ownership of the bus. 6.3.2.2 EXTERNAL CYCLE STEAL MODE. For external devices that generate a pulsed signal for each operand to be transferred, the cycle steal request mode uses the DREQ signal as a falling-edge-sensitive input. The DREQ pulse generated by the device must be asserted during two consecutive falling edges of the clock to be recognized as valid. Therefore, if a peripheral generates it asynchronously, it must be at least two clock periods long. The DMA channel responds to cycle steal requests the same as all other requests. However, if subsequent DREQ pulses are generated before DACK is asserted in response to each request, they are ignored. If DREQ is asserted after the DMA channel asserts DACK for the previous request but before DACK is negated, then the new request is serviced before bus ownership is released. If a new request is not generated by the time DACK is negated, the bus is released. 6.3.2.3 EXTERNAL REQUEST WITH OTHER MODULES. The DMA controller can be externally connected to the serial module and used in conjunction with the serial module to send or receive data. The DMA takes the place of a separate service routine for accessing or storing data that is sent or received by the serial module. Using the DMA also lowers the CPU32 overhead required to handle the data transferred by the serial module. Figure 6-4 shows the external connections required for using the DMA with the serial module.
DMA MODULE DREQ1 DREQ2
.. .... .
SERIAL MODULE TxRDYA RxRDYA
Figure 6-4. DMA External Connections to Serial Module For serial receive, the DMA reads data from the serial receive buffer register (when the serial module has filled the buffer on input) and writes data to memory. For serial transmit, the DMA reads data from memory and writes data to the serial transmit buffer register. Only dual-address mode can be used with the serial module. The MC68341 on-chip peripherals do not support single-address transfers.
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6.4 DATA TRANSFER MODES
The DMA channel supports single- and dual-address transfers. The single-address transfer mode consists of one DMA bus cycle, which allows either a read or a write cycle to occur. The dual-address transfer mode consists of a source operand read and a destination operand write. Two DMA bus cycles are executed for the dual-address mode: a DMA read cycle and a DMA write cycle.
6.4.1 Single-Address Mode
The single-address DMA bus cycle allows data to be transferred directly between a device and memory without going through the DMA. In this mode, the operand transfer takes place in one bus cycle, where only the memory is explicitly addressed. The DMA bus cycle may be either a read or a write cycle. The DMA provides the address and control signals required for the operation. The requesting device either sends or receives data to or from the specified address. Only external requests can be used to start a transfer when the single-address mode is selected. An external device uses DREQ to request a transfer. Each DMA channel can be independently programmed to provide single-address transfers. The CCR ECO bit controls whether a source read or a destination write cycle occurs on the data bus. If the ECO bit is set, the external handshake signals are used with the source operand and a single-address source read occurs. If the ECO bit is cleared, the external handshake signals are used with the destination operand, and a single-address destination write occurs. The channel can be programmed to operate in either burst transfer mode or cycle steal mode. See 6.7 Register Description for more information. 6.4.1.1 SINGLE-ADDRESS READ. During the single-address source (read) cycle, the DMA controls the transfer of data from memory to a device. The memory selected by the address specified in the source address register (SAR), the source function codes in the function code register (FCR), and the source size in the CCR provides the data and control signals on the data bus. This bus cycle operates like a normal read bus cycle. The DMA control signals (DACK and DONE) are asserted in the source (read) cycle. See Figures 6-5 and 6-6 for timing diagrams single-address read for external burst and cycle steal modes.
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CPU CYCLE S0 CLKOUT A31-A0 S2 S4 S0
DMA READ S2 S4 S0
DMA READ S2 S4
CPU CYCLE S0
FC3-FC0
SIZ1-SIZ0 AS
DS
R/W
D31-D0
DSACKx
DREQx
DONEx (INPUT)
.... .. ..
DACKx DONEx (OUTPUT) NOTES: 1. Timing to generate more than one DMA request. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized.
Figure 6-5. Single-Address Read Timing (External Burst)
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CPU CYCLE S0 CLKOUT A31-A0 S2 S4 S0
CPU CYCLE S2 S4 S0
DMA READ S2 S4 S0
CPU CYCLE S2 S4 S0
DMA READ S2 S4
Figure 6-6. Single-Address Read Timing (Cycle Steal)
FC3-FC0 SIZ1-SIZ0
AS DS R/W
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D15-D0
DSACKx
DREQx DONEx (INPUT) DACKx DONEx (OUTPUT) NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.
6.4.1.2 SINGLE-ADDRESS WRITE. During the single-address destination (write) cycle, the DMA controls the transfer of data from a device to memory. The data is written to memory selected by the address specified in the destination address register (DAR), the destination function codes in the FCR, and the size in the CCR. The destination (write) DMA bus cycle has timing identical to a write bus cycle. The DMA control signals (DACK and DONE) are asserted in the destination (write) cycle. See Figures 6-7 and 6-8 for timing diagrams of single-address write for external burst and cycle steal modes.
CPU CYCLE S0 CLKOUT S2 S4 S0
DMA WRITE S2 S4 S0
DMA WRITE S2 S4
CPU CYCLE S0
A31-A0
FC3-FC0
SIZ1-SIZ0 AS
DS
R/W
D31-D0
DSACKx
DREQx
DONEx (INPUT)
.... .. .. .. . .. .
DACKx DONEx (OUTPUT) NOTES: 1. Timing to generate more than one DMA request. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 3. DREQx must be asserted while DACKx is asserted, and meet the setup and hold times for more than one DMA transfer to be recognized.
Figure 6-7. Single-Address Write Timing (External Burst)
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CPU CYCLE S0 CLKOUT S2 S4 S0
CPU CYCLE S2 S4 S0
DMA WRITE S2 S4 S0
CPU CYCLE S2 S4 S0
DMA WRITE S2 S4
A31-A0
Figure 6-8. Single-Address Write Timing (Cycle Steal)
FC3-FC0
SIZ1-SIZ0 AS
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DS
R/W
D15-D0
DSACKx
DREQx DONEx (INPUT) DACKx DONEx (OUTPUT) NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the destination (write) DMA cycle.
6.4.2 Dual-Address Mode
The dual-address DMA bus cycle transfers data between a device or memory and the DMA internal data holding register (DHR). In this mode, any operand transfer takes place in two DMA bus cycles, one where a device is addressed and one where memory is addressed. The data transferred during a dual-address operation is either read from the data bus into the DHR or written from the DHR to the data bus. Each DMA channel can be programmed to operate in the dual-address transfer mode. In this mode, the operand is read from the source address specified in the SAR and placed in the DHR. The operand read may take up to four bus cycles to complete because of differences in operand sizes of the source and destination. The operand is then written to the address specified in the DAR. This transfer may also be up to four bus cycles long. In this manner, various combinations of peripheral, memory, and operand sizes may be used. See 6.7 Register Description for more information. The dual-address transfers can be started by either the internal request mode or by an external device using the DREQ input signal. When the external device uses DREQ, the channel can be programmed to operate in either burst transfer mode or cycle steal mode. 6.4.2.1 DUAL-ADDRESS READ. During the dual-address read cycle, the DMA reads data from a device or memory into the internal DHR. The device or memory is selected by the address specified in the SAR, the source function codes in the FCR, and the source size in the CCR. Data is read from the memory or peripheral and placed in the DHR when the bus cycle is terminated. When the complete operand has been read, the SAR is incremented by 0, 1, 2, or 4, according to the size and increment information specified by the SSIZE and SAPI bits of the CCR. The DMA control signals (DACK and DONE) are asserted in the source (read) cycle when the source device makes a request. See Figures 6-9 and 6-10 for timing diagrams of dual-address reads for external burst and cycle steal modes.
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CPU CYCLE
DMA READ S4 S0 S2 S4 S0
DMA WRITE S2 S4 S0
DMA READ S2 S4 S0
DMA WRITE S2 S4 S0
CPU CYCLE S2 S4
Figure 6-9. Dual-Address Read Timing (External Burst-Source Requesting)
S0 CLKOUT A31-A0
S2
FC3-FC0
SIZ1-SIZ0
AS
DS
R/W
D15-D0
DSACKx
DREQx DONEx (INPUT) DACKx DONEx (OUTPUT) NOTE: 1. Timing to generate more than one DMA transfer. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized. 4. DONEx (input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one.
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S0 CLKOUT A31-A0
CPU CYCLE S2 S4 S0
CPU CYCLE S2 S4 S0
DMA READ S2 S4 S0
DMA WRITE S2 S4 S0
CPU CYCLE S2 S4 S0
DMA READ S2 S4 S0
DMA WRITE S2 S4
Figure 6-10. Dual-Address Read Timing (Cycle Steal-Source Requesting)
FC3-FC0
SIZ1-SIZ0
AS DS R/W
MC68341 USER'S MANUAL MOTOROLA
D15-D0
DSACKx
DREQx DONEx (INPUT) DACKx DONEx (OUTPUT) NOTE 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, the DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 4. DONEx (input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one.
6.4.2.2 DUAL-ADDRESS WRITE. During the dual-address write cycle, the DMA writes data to a device or memory from the internal DHR. The data in the DHR is written to the device or memory selected by the address in the DAR, the destination function codes in the FCR, and the size in the CCR. When the complete operand is written, the DAR is incremented by 0, 1, 2, or 4, according to the increment and size information specified by the DAPI and DSIZE bits of the CCR, and the byte transfer count register (BTC) is decremented by the number of bytes transferred. If the BTC is equal to zero and there were no errors, the channel status register (CSR) DONE bit is set, and the DONE signal for the DMA handshake is asserted. The DMA control signals (DACK and DONE) are asserted in the destination (write) cycle when the destination device makes a request. See Figures 6-11 and 6-12 for timing diagrams of dual-address writes for external burst and cycle steal modes.
MOTOROLA
MC68341 USER'S MANUAL
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6-16 MC68341 USER'S MANUAL MOTOROLA
Figure 6-11. Dual-Address Write Timing (External Burst-Destination Requesting)
CPU CYCLE S0 CLKOUT S2 S4 S0
DMA READ S2 S4 S0
DMA WRITE S2 S4 S0
DMA READ S2 S4 S0
DMA WRITE S2 S4 S0
CPU CYCLE S2 S4
A31-A0
FC3-FC0
SIZ1-SIZ0 AS DS
R/W
D15-D0
DSACKx
DREQx DONEx (INPUT) DACKx DONEx (OUTPUT) NOTE: 1. Timing to generate more than one DMA transfer. 2. DACKx and DONEx (DMA control signals) are asserted in the destination (write) DMA cycle. 3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized. 4. DONEx (input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one.
.... .
MOTOROLA MC68341 USER'S MANUAL 6-17
Figure 6-12. Dual-Address Write Timing (Cycle Steal-Destination Requesting)
CPU CYCLE S0 CLKOUT A31-A0 S2 S4 S0
CPU CYCLE S2 S4 S0
DMA READ S2 S4 S0
DMA WRITE S2 S4 S0
CPU CYCLE S2 S4 S0
DMA READ S2 S4 S0
DMA WRITE S2 S4
FC3-FC0
SIZ1-SIZ0 AS
DS
R/W
D15-D0 DSACKx
DREQx DONEx (INPUT) DACKx DONEx (OUTPUT) NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the destination (write) DMA cycle. 4. DONEx (Input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one.
6.5 BUS ARBITRATION
The DMA controller module uses the 68000 bus arbitration protocol to request bus mastership for DMA transfers. Each channel arbitrates for the bus independently. The source (read) DMA bus cycle has timing identical to a read bus cycle. The destination (write) DMA bus cycle has timing identical to a write bus cycle. However, the DMA channel transfers are unique in that the FC3 signal can be asserted during the source operand bus cycle and remain asserted until the end of the destination operand bus cycle. For internal request generation, as soon as the CCR STR bit is set, the DMA channel arbitrates for the bus and begins to transfer data when it becomes bus master. For external request generation, the STR bit must be set and a DREQ signal must be asserted before the channel arbitrates for the bus and begins a transfer.
6.6 DMA CHANNEL OPERATION
The following paragraphs describe the programmable channel functions available for the DMA channel, the data transfer operations, and behavior during cycle termination. This description applies to both channels. Any DMA channel operation adheres to the following basic sequence: 1. Channel Initialization and Startup--The channel registers are initialized. The channel is then started by setting the CCR STR bit. The first operand transfer request (either internally or externally generated) is recognized. 2. Data Transfer--After a channel is started, it transfers one operand in response to each request until an entire data block is transferred. 3. Channel Termination--The channel can terminate by normal completion or from an error. The CSR indicates the status of the operation.
6.6.1 Channel Initialization and Startup
Before starting a block transfer operation, the channel registers must be initialized with information describing the channel configuration, request generation method, and data block. This initialization is accomplished by programming the appropriate information into the channel registers. The SAR is loaded with the source (read) address. If the transfer is from a peripheral device to memory, the source address is the location of the peripheral data register. If the transfer is from memory to a peripheral device or memory to memory, the source address is the starting address of the data block. This address may be any byte address. In the single-address mode with the destination (write) device requesting mode of operation, this register is not used. The DAR should contain the destination (write) address. If the transfer is from a peripheral device to memory or memory to memory, the DAR is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, the DAR is
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MOTOROLA
loaded with the address of the peripheral data register. This address may be any byte address. In the single-address mode with the source (read) device requesting mode of operation, this register is not used. The manner in which the SAR and DAR change after each cycle depends upon the values in the CCR SSIZE and DSIZE fields and SAPI and DAPI bits, and the starting address in the SAR and DAR. If programmed to increment, the increment value is 1, 2, or 4 for byte, word, or long-word operands, respectively. If the address register is programmed to remain unchanged (no count), the register is not incremented after the operand transfer. The SAR and DAR are incremented if a bus error terminates the transfer. Therefore, either the SAR or the DAR contain the next address after the one that caused the bus error. The BTC must be loaded with the number of byte transfers that are to occur. This register is decremented by 1, 2, or 4 at the end of each transfer. The FCR must be loaded with the source and destination function codes. Although these function codes may not be used in the address decode for the memory or peripheral, they are provided if needed. The CSR must be cleared for channel startup. Once the channel has been initialized, it is started by writing a one to the STR bit in the CCR. Programming the channel for internal request causes the channel to request the bus and start transferring data immediately. If the channel is programmed for external request, DREQ must be asserted before the channel requests the bus. The DREQ input is ignored until the channel is started, since the channel does not recognize transfer requests until it is active. If any fields in the CCR are modified while the channel is active, that change is effective immediately. To avoid any problems with changing the setup for the DMA channel, a zero should be written to the STR bit in the CCR to halt the DMA channel at the end of the current bus cycle.
6.6.2 Data Transfers
Each operand transfer requires from one to five bus cycles to complete. Once a bus request is recognized and the operand transfer begins, both the source (read) cycle and/or the destination (write) cycle occur before a new bus request may be honored, even if the new bus request is of higher priority. 6.6.2.1 INTERNAL REQUEST TRANSFERS. The percentage of bus bandwidth utilization can be limited for internal request transfers. 6.6.2.2 EXTERNAL REQUEST TRANSFERS. In single-address mode, only one bus cycle is run for each request. Since the operand size must be equal to the device port size in single-address mode, the number of normally terminated bus cycles executed during a transfer operation is always equal to the value programmed into the corresponding size field of the CCR. The sequencing of the address bus follows the programming of the CCR and address register (SAR or DAR) for the channel. Each operand transfer in dual-address mode requires from two to five bus cycles in response to each operand transfer request. If the source and destination operands are the
MOTOROLA MC68341 USER'S MANUAL 6-19
same size, two cycles will transfer the complete operand. If the source and destination operands are different sizes, the number of cycles will vary. If the source is a long-word and the destination is a byte, there would be one bus cycle for the read and four bus cycles for the write. Once the DMA channel has started a dual-address operand transfer, it must complete that transfer before releasing ownership of the bus or servicing a request for another channel of equal or higher priority, unless one of the bus cycles is terminated with a bus error during the transfer.
6.6.3 Channel Termination
The channel can terminate by normal completion or as the result of an error. The status of a DMA operation can be determined by reading the CSR. The DMA channel can also interrupt the processor to inform it of errors, normal transfer completion, or breakpoints. The fast termination option can also be used to provide a two-clock access for external requests. 6.6.3.1 CHANNEL TERMINATION. The channel operation can be terminated for several reasons: the BTC is decremented to zero, a peripheral device asserts DONE during an operand transfer, the STR bit is cleared in the CCR, a bus cycle is terminated with a bus error, or a reset occurs. 6.6.3.2 INTERRUPT OPERATION. Interrupts can be generated by error termination of a bus cycle or by normal channel completion. Specifically, if the CCR interrupt error (INTE) bit is set and a bus error on source (CCR BES) bit, bus error on destination (CCR BED) bit, or configuration error (CCR CONF) bit is set, the CCR IRQ bit is set. In this case, clearing the INTE, BES, BED, or CONF bits causes the IRQ bit to be cleared. If the interrupt normal (CCR INTN) bit is set and the CCR DONE bit is set, the IRQ bit is set. In this case, clearing the INTN or the DONE bit causes the IRQ bit to be cleared. If the interrupt breakpoint (CCR INTB) and the CSR BRKP bits are set, the IRQ bit is set. Clearing INTB or BRKP clears IRQ.
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6.6.3.3 FAST TERMINATION OPTION. Using the system integration module (SIM41) chip select logic, the fast termination option (Figure 6-13) can be employed to give a fast bus access of two clock cycles rather than the standard three-cycle access time for external requests. The fast termination option is described in Section 3 Bus Operation and Section 4 System Integration Module.
CPU CYCLE S0 CLKOUT S2 S4 DMA READ S0 S4 S0 CPU CYCLE S2 S4 DMA READ S0 S2
A31-A0
FC3-FC0 SIZ1-SIZ0 AS
DS R/W
D31-D0
DSACKx
DREQx
DACKx DONEx (OUTPUT) NOTES: 1. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.
Figure 6-13. Fast Termination Option Timing (Cycle Steal) If the fast termination option is used with external burst request mode (Figure 6-14), an extra DMA cycle may result on every burst transfer. Normally, DREQ is negated when DACK is returned. In the burst mode with fast termination selected, a new cycle starts even if DREQ is negated simultaneously with DACK assertion.
MOTOROLA
MC68341 USER'S MANUAL
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CPU CYCLE S0 CLKOUT A31-A0 S2 S4
DMA READ S0 S4
DMA WRITE S0 S4 S0
CPU CYCLE S2
. . ......... . .
DMA READ S4 S0 S4
DMA WRITE S0 S4 S0
FC3-FC0
SIZ1-SIZ0
AS
DS
R/W
D31-D0
DSACKx
DREQx
DACKx DONEx (OUTPUT) NOTES: 1. To cause another DMA transfer, the DREQx is asserted after DACKx is asserted and before DACKx is negated. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.
Figure 6-14. Fast Termination Option Timing (External Burst-Source Requesting)
6.7 REGISTER DESCRIPTION
The following paragraphs contain a detailed description of each register and its specific function. Figure 6-15 is a programmer's model (register map) of all registers in the DMA module. Each channel has an independent set of registers. For more information about a particular register, refer to the individual register description. The ADDRESS column indicates the offset of the register from the base address of the DMA channel. The FC column designation of S indicates that register access is restricted to supervisor only. A designation of S/U indicates that access is governed by the SUPV bit in the module configuration register (MCR). Unimplemented memory locations return logic zero when accessed. All registers support byte, word, and long-word transfers. The register interface from the IMB is 16 bits, which forces long-word accesses to complete as two successive word accesses.
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MOTOROLA
ADDRESS CH1 780 782 784 786 788 78A 78C 78E 790 792 794 796 798 79A 79C 79E CH2 7A0 7A2 7A4 7A6 7A8 7AA 7AC 7AE 7B0 7B2 7B4 7B6 7B8 7BA 7BC 7BE
FC 15 S S S S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U 8 7 0 MODULE CONFIGURATION REGISTER RESERVED INTERRUPT REGISTER RESERVED CHANNEL CONTROL REGISTER CHANNEL STATUS REGISTER FUNCTION CODE REGISTER SOURCE ADDRESS REGISTER MSBs SOURCE ADDRESS REGISTER LSBs DESTINATION ADDRESS REGISTER MSBs DESTINATION ADDRESS REGISTER LSBs BYTE TRANSFER COUNTER MSBs BYTE TRANSFER COUNTER LSBs RESERVED RESERVED RESERVED RESERVED
Figure 6-15. DMA Module Programming Model The registers are discussed in the following paragraphs in alphabetical order. The numbers in the upper right-hand corner of the register diagrams indicate the offset of the register from the base address specified by the module base address register (MBAR) in the SIM41. The first number is the offset for channel 1; the second number is the offset for channel 2. The numbers above the register represent the bit position in the register. The register contains the mnemonic for the bit. The value of these bits after a hardware reset is shown below the register. The access privilege is shown in the lower right-hand corner. NOTE A CPU32 RESET instruction will not affect the MCR but will reset all other registers in the DMA module as though a hardware reset occurred. The term DMA is used to reference either channel 1 or channel 2, since the two are functionally equivalent.
MOTOROLA
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6.7.1 Byte Transfer Counter Register (BTC)
The BTC is a 32-bit register that contains the number of bytes left to transfer in a given block. This register is accessible in either supervisor or user space. The BTC can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). BTC1, BTC2
31 A31 RESET: U 30 A30 29 A29 28 A28 27 A27 26 A26 25 A25 24 A24 23 A23 22 A22 21 A21 20 A20 19 A19 18 A18
$794, $7B4
17 A17 16 A16
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
15 A15 RESET: U
14 A14
13 A13
12 A12
11 A11
10 A10
9 A9
8 A8
7 A7
6 A6
5 A5
4 A4
3 A3
2 A2
1 A1
0 A0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U = Unaffected by reset
Supervisor/User
This register is decremented by 1, 2, or 4 for each successful operand transfer from source to destination locations. When the BTC decrements to zero and no error has occurred, the CSR DONE bit is set. In the external request mode, the DONE handshake line is also asserted when the BTC is decremented to zero. If the operand size is byte, then the register is always decremented by 1. If the operand size is word and the starting count is even word, the register is decremented by 2. If the operand size is word and the byte count is not a multiple of 2, the CSR CONF bit is set, and a transfer does not occur. If the operand size is long word and the count is a multiple of four, then the register is decremented by 4. If the operand size is long word and the byte count is not a multiple of 4, the CSR CONF bit is set, and a transfer does not occur. If the STR bit is set with a zero count in the BTC, the CONF bit is set, and the STR bit is cleared. When read, this register always contains the count for the next access. If a bus error terminates the transfer, this register contains the count for the next access that would have been run had the error not occurred.
6.7.2 Channel Control Register (CCR)
The CCR controls the configuration of the DMA channel. This register is accessible in either supervisor or user space. The CCR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). CCR1, CCR2
15 INTB RESET: U 14 INTN 13 INTE 12 ECO 11 SAPI 10 DAPI 9 SSIZE 8 7 DSIZE 6 5 REQ 4 3 BB 2
$788, $7A8
1 S/D 0 STR
U
U
U
U
U
U
U
U
U
U
U
U
U
U
0
U = Unaffected by reset
Supervisor/User
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INTB--Interrupt Breakpoint Setting the interrupt breakpoint bit sets the BRKP bit in the CSR. The logic AND of INTB and BRKP generates an interrupt request. 1 = Enables an IRQ when a breakpoint is recognized and the channel is the bus master. 0 = Does not enable an IRQ when a breakpoint is recognized and the channel is the bus master. INTN--Interrupt Normal 1 = Enables IRQ when the channel finishes a transfer without an error condition (CSR DONE bit is set). 0 = Does not enable IRQ when the channel finishes a transfer without an error condition. INTE--Interrupt Error 1 = Enables IRQ when the channel encounters an error on source read (CSR BES bit is set), destination write (CSR BED bit is set), or configuration for channel setup (CSR CONF bit is set). 0 = Does not enable IRQ when the channel encounters an error on source read, destination write, or configuration for channel setup. ECO--External Control Option If request generation is programmed to be internal (REQ bits = 00), this bit has no effect. Single-Address Mode--This bit defines the direction of transfer. 1 = If request generation is programmed to be external (REQ = 1x), the requesting device receives the data (read from memory), and the control signals (DREQ, DACK , and DONE) are used by the requesting device to write data during the source (read) portion of the transfer. 0 = If request generation is programmed to be external (REQ = 1x), the requesting device provides the data (write to memory), and the control signals (DREQ, DACK , and DONE) are used by the requesting device to provide data during the destination (write) portion of the transfer. Dual-Address Mode--This bit defines which device generates requests. 1 = If request generation is programmed to be external (REQ = 1x), the source device generates the request, and the control signals (DREQ, DACK , and DONE) are part of the source (read) portion of the transfer. 0 = If request generation is programmed to be external (REQ = 1x), the destination device generates the request, and the control signals (DREQ, DACK , and DONE) are part of the destination (write) portion of the transfer.
MOTOROLA
MC68341 USER'S MANUAL
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SAPI--Source Address Pointer Increment 1 = The SAR is incremented by 1, 2, or 4 after each transfer, according to the source size. The address that is written into the SAR points to a memory block and is incremented to complete the data transfer. 0 = The SAR is not incremented during operand transfer. The address that is written into the SAR points to a peripheral device and is used for the complete data transfer. DAPI--Destination Address Pointer Increment 1 = The DAR is incremented by 1, 2, or 4 after each transfer, according to the source size. The address that is written into the DAR points to a memory block and is incremented to complete the data transfer. 0 = The DAR is not incremented during operand transfer. The address that is written into the DAR points to a peripheral device and is used for the complete data transfer. SSIZE--Source Size Control Field This field controls the size of the source (read) bus cycle that the DMA channel is running. Table 6-1 defines these bits. Table 6-1. SSIZEx Encoding
Bit 9 0 0 1 1 Bit 8 0 1 0 1 Definition Long Word Byte Word Not Used
DSIZE--Destination Size Control Field This field controls the size of the destination (write) bus cycle that the DMA channel is running. Table 6-2 defines these bits. Table 6-2. DSIZEx Encoding
Bit 7 0 0 1 1 Bit 6 0 1 0 1 Definition Long Word Byte Word Not Used
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MOTOROLA
REQ--Request Generation Field This field controls the mode of operation the DMA channel uses to make an operand transfer request. Table 6-3 defines these bits. Table 6-3. REQx Encoding
Bit 5 0 0 1 1 Bit 4 0 1 0 1 Reserved External Request Burst Transfer Mode External Request Cycle Steal Definition Internal Request at Programmable Rate
BB--Bus Bandwidth Field This field controls the percentage of 1024 clock periods of the IMB that the DMA channel can use during internal requests only (REQx = 00). Table 6-4 defines these bits. Table 6-4. BBx Encoding and Bus Bandwidth
BB Field Bit 3 0 0 1 1 Bit 2 0 1 0 1 Definition 25% 50% 75% 100% Bus Bandwidth (Clock Periods) 256 512 768 1024
S/D--Single-/Dual-Address Transfer 1 = The DMA channel runs single-address transfers from a peripheral to memory or from memory to a peripheral. The destination holding register is not used for these transfers because the data is transferred directly into the destination location. The MC68341 on-chip peripherals do not support single-address transfers. 0 = The DMA channel runs dual-address transfers. STR--Start This bit is cleared by a hardware/software reset, writing a logic zero, or setting one of the following CSR bits: DONE, BES, BED, CONF, or BRKP. The STR bit cannot be set when the CSR IRQ bit is set. The DMA channel cannot be started until the CSR DONE, BES, BED, CONF, and BRKP bits are cleared. Internal Request Mode: 1 = The DMA transfer starts as soon as this bit is set. 0 = The DMA transfer can be stopped by clearing this bit. External Request Mode: 1 = Setting this bit allows the DMA to start the transfer when a DREQ input is received from an external device. 0 = The DMA transfer can be stopped by clearing this bit.
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NOTE If any fields in the CCR are modified while the channel is active, that change is effective immediately. To avoid any problems with changing the setup for the DMA channel, a zero should be written to the STR bit in the CCR to halt the DMA channel at the end of the current bus cycle.
6.7.3 Channel Status Register (CSR)
The CSR contains the channel status information. This register is accessible in either supervisor or user space. The CSR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). CSR1, CSR2
7 IRQ RESET 0 6 DONE 5 BES 4 BED 3 CONF 2 BRKP
$78A, $7AA
1 0 0 0
0
0
0
0
0
0
0
Supervisor/User IRQ--Interrupt Request This bit is the logical OR of the DONE, BES, BED, CONF, and BRKP bits and is cleared when they are all cleared. IRQ is positioned to allow conditional testing as a signed binary integer. The state of this bit is not affected by the interrupt enable bits in the CCR. The STR bit in the CCR cannot be set when this bit is set; all error status bits, except the BRKP bit, must be cleared before the STR bit can be set. 1 = An interrupt condition has occurred. 0 = An interrupt condition has not occurred. DONE--DMA Done 1 = The DMA channel has terminated normally. 0 = The DMA channel has not terminated normally. This bit is cleared by writing a logic one or by a hardware reset. Writing a zero has no effect. BES--Bus Error on Source 1 = The DMA channel has terminated with a bus error during the read bus cycle. 0 = The DMA channel has not terminated with a bus error during the read bus cycle. This bit is cleared by writing a logic one or by a hardware reset. Writing a zero has no effect. BED--Bus Error on Destination 1 = The DMA channel has terminated with a bus error during the write bus cycle. 0 = The DMA channel has not terminated with a bus error during the write bus cycle. This bit is cleared by writing a logic one or by a hardware reset. Writing a zero has no effect.
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CONF--Configuration Error A configuration error results when either the SAR or the DAR contains an address that does not match the port size specified in the CCR and the BTC register does not match the larger port size or is zero. 1 = The CCR STR bit is set, and a configuration error is present. 0 = The CCR STR bit is set, and no configuration error exists. This bit is cleared by writing a logic one or by a hardware reset. Writing a zero has no effect. BRKP--Breakpoint 1 = The breakpoint signal was set during a DMA transfer. 0 = The breakpoint signal was not set during a DMA transfer. This bit is cleared by writing a logic one or by a hardware reset. Writing a zero has no effect. Bits 1, 0--Reserved by Motorola NOTE The CSR is cleared by writing $7C to its location. The DMA channel cannot be started until the CSR DONE, BES, BED, CONF and BRKP bits are cleared.
6.7.4 Destination Address Register (DAR)
The DAR is a 32-bit register that contains the address of the destination operand used by the DMA to write to memory or peripheral registers. This register is accessible in either supervisor or user space. The DAR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). DAR1, DAR2
31 A31 RESET: U 30 A30 29 A29 28 A28 27 A27 26 A26 25 A25 24 A24 23 A23 22 A22 21 A21 20 A20 19 A19 18 A18
$790, $7B0
17 A17 16 A16
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
15 A15 RESET: U
14 A14
13 A13
12 A12
11 A11
10 A10
9 A9
8 A8
7 A7
6 A6
5 A5
4 A4
3 A3
2 A2
1 A1
0 A0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U = Unaffected by reset
Supervisor/User
During the DMA write cycle, this register drives the address on the address bus. This register can be programmed to increment (CCR DAPI bit set) or remain constant (CCR DAPI bit cleared) after each operand transfer. The register is incremented using unsigned arithmetic and will roll over if overflow occurs. For example, if a register contains $FFFFFFFF and is incremented by 1, it will roll over to $00000000. This register can be incremented by 1, 2, or 4, depending on the size of the operand and the starting address. If the operand size is byte, the register is always incremented by 1. If the operand size is word and the starting address is word aligned, the
MOTOROLA MC68341 USER'S MANUAL 6-29
register is incremented by 2. If the operand size is long word and the address is word aligned, the register is incremented by 4. The DAR value must be aligned to an word boundary if the transfer size is word or long word; otherwise, the CSR CONF bit is set, and the transfer does not occur. When read, this register always contains the next destination address. If a bus error terminates the transfer, this register contains the next destination address that would have been run had the error not occurred.
6.7.5 Function Code Register (FCR)
The FCR contains the source and destination function codes for the channel. This register is accessible in either supervisor or user space. The FCR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). FCR1, FCR2
7 6 SFC RESET: U 5 4 3 2 DFC
$78B, $7AB
1 0
U
U
U
U
U
U
U
U = Unaffected by reset
Supervisor/User
SFC--Source Function Code Field This field specifies the source access to a certain address space type. The source function code bits 3-0 are defined in Table 6-5. DFC--Destination Function Code Field This field specifies the destination access to a certain address space type. The destination function code bits 3-0 are defined in Table 6-5. Table 6-5. Address Space Encoding
Source/Destination Function Code Bits 3 0 0 0 0 0 0 0 0 1 2 0 0 0 0 1 1 1 1 x 1 0 0 1 1 0 0 1 1 x 0 0 1 0 1 0 1 0 1 x Address Spaces Reserved (Motorola) User Data Space User Program Space Reserved (User) Reserved (Motorola) Supervisor Data Space Supervisor Program Space CPU Space DMA Space
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NOTE Although SFC3/DFC3 can be set for DMA transfers to distinguish the source or destination space from other data or program spaces, it is not required to be set. Since the CPU32 currently has only 3-bit SFC and DFC capability, it cannot emulate SFC3 = 1 or DFC3 = 1 at this time. However, it is recommended that SFC3/DFC3 be set to one to distinguish DMA and CPU accesses during debug.
6.7.6 Interrupt Register (INTR)
The INTR contains the priority level for the channel interrupt request and the 8-bit vector number of the interrupt. The register can be read or written to at any time while in supervisor mode and while the DMA module is enabled (i.e., the STP bit in the MCR is cleared). INTR1, INTR2
15 0 RESET: 0 14 0 13 0 12 0 11 0 10 9 INTL 8 7 6 5 4 INTV 3 2
$784, $7A4
1 0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Supervisor Only Bits 15-11--Reserved by Motorola INTL--Interrupt Level Bits Each module that can generate interrupts has an interrupt level field. The interrupt level field contains the priority level of the interrupt for its associated channel. The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQ signal. The CPU32 uses this value to determine servicing priority. See Section 5 CPU030 for more information. INTV--Interrupt Vector Bits Each module that can generate interrupts has an interrupt vector field. The interrupt vector field contains the vector number of the interrupt for its associated channel. This 8bit field indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. The INTV field is reset to $0F, which indicates an uninitialized interrupt condition. See Section 5 CPU030 for more information.
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6.7.7 Module Configuration Register (MCR)
The MCR controls the DMA channel configuration. Each DMA channel has an MCR. This register can be either read or written when the channel is enabled and is in the supervisor state. The MCR is not affected by a CPU32 RESET instruction. MCR1, MCR2
15 STP RESET: 0 14 FRZ1 13 FRZ0 12 SE 11 0 10 9 ISM 8 7 SUPV 6 5 MAID 4 3 2 IARB
$780, $7A0
1 0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Supervisor Only STP--Stop Bit 1 = Setting the STP bit stops all clocks within the DMA module except for the clock from the IMB. The clock from the IMB remains active to allow the CPU32 access to the MCR. The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to DMA module registers while in stop mode produce a bus error. The DMA module should be disabled in a known state before setting the STP bit. The STP bit should be set prior to executing the LPSTOP instruction to reduce overall power consumption. 0 = The channel operates in normal mode. NOTE The DMA module uses only one STP bit for both channels. A read or write to either MCR accesses the same STP control bit. FRZ1, FRZ0--Freeze These bits determine the action taken when the FREEZE signal is asserted on the IMB when the CPU32 has entered background debug mode. The DMA module negates BR and keeps it negated until FREEZE is negated or reset. Table 6-6 lists the action taken for each bit combination. Table 6-6. FRZx Control Bits
FRZ1 0 0 1 1 FRZ0 0 1 0 1 Action Ignore FREEZE Reserved Freeze on Boundary* Reserved
*The boundary is defined as any bus cycle by the DMA module.
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NOTE The DMA module uses only one set of FRZx bits for both channels. A read or write to either MCR accesses the same FRZx control bits. SE--Single-Address Enable This bit is implemented for future M68300 family compatibility. 1 = In single-address mode, the external data bus is driven during a DMA transfer. 0 = In single-address mode, the external data bus remains in a high-impedance state during a DMA transfer (used for intermodule DMA). In dual-address mode, the SE bit has no effect. Bit 11--Reserved by Motorola ISM2-ISM0--Interrupt Service Mask These bits contain the interrupt service mask level for the channel. When the interrupt service level on the IMB is greater than the interrupt service mask level, the DMA vacates the bus and negates BR until the interrupt service level is less than or equal to the interrupt service mask level. NOTE When the CPU32 status register (SR) interrupt priority mask bits I2-I0 are at a higher level than the DMA ISM bits, the DMA channel will not start. The channel will begin operation when the level of the SR I2-I0 bits is less than or equal to the level of the DMA ISM bits. SUPV--Supervisor/User The value of this bit has no effect on registers permanently defined as supervisor-only access. 1 = The DMA channel registers defined as supervisor/user reside in supervisor data space and are only accessible from supervisor programs. 0 = The DMA channel registers defined as supervisor/user reside in user data space and are accessible from either supervisor or user programs. MAID--Master Arbitration ID These bits establish bus arbitration priority level among modules that have the capability of becoming bus master. For the MC68341, the MAID bits are used to arbitrate between DMA channel 1 and channel 2. If both channels are programmed with the same MAID level, channel 1 will have priority. These bits are implemented for future M68300 family compatibility. In the MC68341, only the SIM and the DMA can be bus masters. However, future versions of the M68300 family may incorporate other modules that may also be bus masters. For these devices, the MAID bits will be required. For the MAID bits, zero is the lowest priority and seven is the highest priority.
MOTOROLA MC68341 USER'S MANUAL 6-33
IARB -- Interrupt Arbitration ID Each module that generates interrupts has an IARB field. These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level. No two modules can share the same IARB value. The reset value of the IARB field is $0, which prevents the DMA module from arbitrating during the interrupt acknowledge cycle. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). NOTE The DMA module uses only one set of IARB bits for both channels. A read or write to either MCR accesses the same IARB control bits.
6.7.8 Source Address Register (SAR)
The SAR is a 32-bit register that contains the address of the source operand used by the DMA to access memory or peripheral registers. This register is accessible in either supervisor or user space. The SAR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). SAR1, SAR2
31 A31 RESET: U 30 A30 29 A29 28 A28 27 A27 26 A26 25 A25 24 A24 23 A23 22 A22 21 A21 20 A20 19 A19 18 A18
$78C, $7AC
17 A17 16 A16
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
15 A15 RESET: U
14 A14
13 A13
12 A12
11 A11
10 A10
9 A9
8 A8
7 A7
6 A6
5 A5
4 A4
3 A3
2 A2
1 A1
0 A0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U = Unaffected by reset
Supervisor/User
During the DMA read cycle, the SAR drives the address on the address bus. This register can be programmed to increment (CCR SAPI bit set) or remain constant (CCR SAPI bit cleared) after each operand transfer. The register is incremented using unsigned arithmetic and will roll over if overflow occurs. For example, if the register contains $FFFFFFFF and is incremented by 1, it will roll over to $00000000. This register is incremented by 1, 2, or 4, depending on the size of the operand and the memory starting address. If the operand size is byte, then the register is always incremented by 1. If the operand size is word and the starting address is word aligned, then the register is incremented by 2. If the operand size is long word and the address is word aligned, then the register is incremented by 4. The SAR value must be aligned to an word boundary if the transfer size is word or long word; otherwise, the CSR CONF bit is set, and the transfer does not occur.
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When read, this register always contains the next source address. If a bus error terminates the transfer, this register contains the next source address that would have been run had the error not occurred.
6.8 DATA PACKING
The internal DHR is a 32-bit register that can serve as a buffer register for the data being transferred during dual-address DMA cycles. No address is specified since this register can not be addressed by the programmer. The DHR allows the data to be packed and unpacked by the DMA during the dual-address transfer. For example, if the source operand size is byte and the destination operand size is word, then for each DMA request two byte read cycles occur, followed by one word write cycle (see Figure 6-16). The two bytes of data are buffered in the DHR until the destination (write) word cycle occurs. The DHR allows for packing and unpacking of operands for the following sizes: bytes to words, bytes to long words, words to long words, words to bytes, long words to bytes, and long words to words.
SOURCE/DESTINATION BYTE0 BYTE1 BYTE0 BYTE1 DESTINATION/SOURCE
..... ..... ..... . .
BYTE0 BYTE1 BYTE2 BYTE3 BYTE0 BYTE1 BYTE2 BYTE3
BYTE0 BYTE2
BYTE1 BYTE3 BYTE0 BYTE1 BYTE2 BYTE3
Figure 6-16. Packing and Unpacking of Operands For normal transfers aligned with the size and address, only two bus cycles are required for each transfer: a read from the source and a write to the destination.
6.9 DMA CHANNEL INITIALIZATION SEQUENCE
The following paragraphs describe DMA channel initialization and operation. If the DMA capability of the MC68341 is being used, the initialization steps should be performed during the part initialization sequence. The mode operation steps should be performed to start a DMA transfer. The DONE pin requires an external pullup resistor even if operating only in the internal request mode.
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6.9.1 DMA Channel Configuration
The following steps can be accomplished in any order when initializing the DMA channel. These steps need to be performed for each channel used. Module Configuration Register (MCR) * Clear the stop bit (STP) for normal operation. (Only one STP bit exists for both channels.) * Select whether to respond to or ignore FREEZE (FRZx bits). (Only one set of FRZx bits exists for both channels.) * If desired, enable the external data bus operation in single-address mode (SE bit). * Program the interrupt service mask to set the level below which interrupts are ignored during a DMA transfer (ISM bits). The channel will begin operation when the level of the CPU32 SR I2-I0 bits is less than or equal to the level of the DMA ISM bits. * Select the access privilege for the supervisor/user registers (SUPV bit). * Program the master arbitration ID (MAID) to establish priority on the IMB between both DMA channels. Note that the two DMA channels should have distinct MAIDs if both channels are being used. (If they are programmed the same, channel 1 has priority.) * Select the interrupt arbitration level for the DMA channel (IARB bits). (Only one set of IARB bits exists for both channels.) Interrupt Register (INTR) * Program the interrupt priority level for the channel interrupt (INTL bits). * Program the vector number for the channel interrupt (INTV bits). Channel Control Register (CCR) * If desired, enable the interrupt when breakpoint is recognized and the channel is the bus master (INTB bit). * If desired, enable the interrupt when done without an error condition (INTN bit). * If desired, enable the interrupt when the channel encounters an error (INTE bit). * Select the direction of transfer if in single-address mode (ECO bit), or select which device generates requests if in dual-address mode.
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6.9.1.1 DMA CHANNEL OPERATION IN SINGLE-ADDRESS MODE. The following steps are required to begin a DMA transfer in single-address mode. Channel Control Register (CCR) * Write a zero to the start bit (STR) to prevent the channel from starting the transfer prematurely. * Select the amount by which to increment the source address for a read cycle (SAPI bit) or the destination address for a write cycle (DAPI bit). * Define the transfer size by selecting the source size for a read cycle (SSIZE field) or by selecting the destination size for a write cycle (DSIZE field). * Select external burst request mode or external cycle steal request mode (REQ field). * Set the S/D bit for signal-address transfer. Channel Status Register (CSR) * Clear the CSR by writing $7C into it. The DMA cannot be started until the DONE, BES, BED, CONF, and BRKP bits are cleared. Function Code Register (FCR) * Encode the source function code for a read cycle or the destination function code for a write cycle. Address Register (SAR or DAR) * Write the source address for a read cycle or the destination address for a write cycle. Byte Transfer Counter (BTC) * Encode the number of bytes to be transferred. Channel Control Register (CCR) * Write a one to the start bit (STR) to allow the transfer to begin.
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6.9.1.2 DMA CHANNEL OPERATION IN DUAL-ADDRESS MODE. The following steps are required to begin a DMA transfer in dual-address mode. Channel Control Register (CCR) * Write a zero to the start bit (STR) to prevent the channel from starting the transfer prematurely. * Select the amount by which to increment the source and destination addresses (SAPI and DAPI bits). * Select the source and destination sizes (SSIZE and DSIZE fields). * Select internal request, external burst request mode, or external cycle steal request mode (REQ field). * If using internal request, select the amount of bus bandwidth to be used by the DMA (BB field). * Clear the S/D bit for dual-address transfer. Channel Status Register (CSR) * Clear the CSR by writing $7C into it. The DMA cannot be started until the DONE, BES, BED, CONF, and BRKP bits are cleared. Function Code Register (FCR) * Encode the source and destination function codes. Address Registers (SAR and DAR) * Write the source and destination addresses. Byte Transfer Counter (BTC) * Encode the number of bytes to be transferred. Channel Control Register (CCR) * Write a one to the start bit (STR) to allow the transfer to begin.
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6.9.2 DMA Channel Example Configuration Code
The following are examples of configuration sequences for a DMA channel in single- and dual-addressing modes. This common set of equates is used by all of the following examples:
*************************************************************************** * SIM41 equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM41 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM41 MBAR address value PPARC EQU $29 Port C pin assignment register *************************************************************************** * DMA Channel 1 equates DMACH1 EQU $780 Offset from MBAR for channel 1 regs DMAMCR1 EQU $0 MCR for channel 1 * Channel 1 register offsets from channel 1 base address DMAINT1 EQU $4 interrupt register channel 1 DMACCR1 EQU $8 control register channel 1 DMACSR1 EQU $A status register channel 1 DMAFCR1 EQU $B function code register channel 1 DMASAR1 EQU $C source address register channel 1 DMADAR1 EQU $10 destination address register channel 1 DMABTC1 EQU $14 byte transfer count register channel 1 ***************************************************************************
In addition to the initialization shown in each example, the Port C Pin Assignment Register should also be configured if DTC, RDYx, or delayed DACKx signals are used:
*************************************************************************** * PPARC initialization for DMA signal functionality * The following example selects RDY1 and delayed DACKx functionality for * DMA channel 1 - other pins unchanged: OR.B #$50,MODBASE+PPARC Select RDY1 & delayed DACK1 funct ***************************************************************************
Example 1: External Burst Request Generation, Single-Address Transfers.
*************************************************************************** * MC68341 basic DMA channel register initialization example code. * This code is used to initialize the 68341's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for external burst request generation, * single-address mode, long word size transfers. * Control signals are asserted on the DMA read cycle. *************************************************************************** * Equates *************************************************************************** SARADD EQU $10000 source address MOTOROLA MC68341 USER'S MANUAL 6-39
NUMBYTE EQU
$C
number of bytes to transfer
*************************************************************************** * Initialize DMA Channel 1 *************************************************************************** LEA MODBASE+DMACH1,A0 Pointer to channel 1 * Initialize DMA channel 1 MCR * Normal Operation, ignore FREEZE, single-address mode. ISM field at 2. Make * sure SR I2-I0 bits are less than or equal to ISM bits for channel startup. * Supervisor/user reg. unrestricted, MAID field at 7. IARB priority at 1. MOVE.W #$1271,(A0) * Clear channel control reg. * Clear STR (start) bit to prevent the channel from starting a transfer early. CLR.W DMACCR1(A0) * Initialize interrupt reg. * Interrupt priority at 7, interrupt vector at $42. MOVE.W #$0742,DMAINT1(A0) * Initialize channel status reg. * Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup. MOVE.B #$7C,DMACSR1(A0) * Initialize function code reg. * DMA space, user data space for source. MOVE.B #$99,DMAFCR1(A0) * Initialize source operand address * Source address is equal to $10000. MOVE.L SARADD,DMASAR1(A0) * Initialize the byte transfer count reg. * The number of bytes to be transferred is $C or 3 long words MOVE.L NUMBYTE,DMABTC1(A0) * Channel control reg. init. and Start DMA transfers * No interrupts are enabled, source (read) cycle. Increment source * address, source size is long word, REQ is external burst request. * Single-address mode, start the DMA transfers. MOVE.W #$1823,DMACCR1(A0) END ***************************************************************************
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Example 2: Internal Request Generation, Memory to Memory Transfers.
*************************************************************************** * MC68341 basic DMA channel register initialization example code. * This code is used to initialize the 68341's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for internal request generation * memory to memory transfers. *************************************************************************** * Equates *************************************************************************** SARADD EQU $6000 source address DARADD EQU $8000 destination address NUMBYTE EQU $E number of bytes to transfer *************************************************************************** * Initialize DMA Channel 1 *************************************************************************** LEA MODBASE+DMACH1,A0 Pointer to channel 1 * Initialize DMA channel 1 MCR * Normal Operation, ignore FREEZE, dual-address mode. ISM field at 3. CPU32 * SR I2-I0 bits must be less than or equal to ISM bits for channel startup. * Supervisor/user reg. unrestricted, MAID field at 3. IARB priority at 4. MOVE.W #$0334,(A0) * Clear channel control reg. * Clear STR (start) bit to prevent the channel from starting a transfer early. CLR.W DMACCR1(A0) * Initialize interrupt reg. * Interrupt priority at 7, interrupt vector at $42. MOVE.W #$0742,DMAINT1(A0) * Initialize channel status reg. * Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup. MOVE.B #$7C,DMACSR1(A0) * Initialize function code reg. * DMA space, supervisor data space for source and destination. MOVE.B #$DD,DMAFCR1(A0) * Initialize source operand address * Source address is equal to $6000. MOVE.L SARADD,DMASAR1(A0) * Initialize destination operand address * Destination address is equal to $8000.
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MOVE.L
DARADD,DMADAR1(A0)
* Initialize the byte transfer count reg. * The number of bytes to be transferred is $E or 7 words MOVE.L NUMBYTE,DMABTC1(A0) * Channel control reg. init. and Start DMA transfers * No interrupts are enabled, destination (write) cycle. Increment source and * destination addresses,source size is word, destination size is word. * REQ is internal. 100% of bus bandwidth, dual-address transfers, * start the DMA transfers. MOVE.W #$0E8D,DMACCR1(A0) END ***************************************************************************
Example 3: Internal Request Generation, Memory Block Initialization.
*************************************************************************** * MC68341 basic DMA channel register initialization example code. * This code is used to initialize the 68341's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for internal request generation * to perform a memory block initialization for 100 bytes. *************************************************************************** * Equates *************************************************************************** SARADD EQU $6000 source address DARADD EQU $8000 destination address NUMBYTE EQU $64 number of bytes to transfer *************************************************************************** * Initialize DMA Channel 1 *************************************************************************** LEA MODBASE+DMACH1,A0 Pointer to channel 1 * Initialize DMA channel 1 MCR * Normal Operation, ignore FREEZE, dual-address mode. ISM field at 3. CPU32 * SR I2-I0 bits must be less than or equal to ISM bits for channel startup. * Supervisor/user reg. unrestricted, MAID field at 3. * IARB priority at 4. MOVE.W #$0334,(A0) * Clear channel control reg. * Clear STR (start) bit to prevent the channel from starting a transfer early. CLR.W DMACCR1(A0) * Initialize interrupt reg. 6-42 MC68341 USER'S MANUAL MOTOROLA
* Interrupt priority at 7, interrupt vector at $42. MOVE.W #$0742,DMAINT1(A0) * Initialize channel status reg. * Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup. MOVE.B #$7C,DMACSR1(A0) * Initialize function code reg. * DMA space, supervisor data space for source and destination. MOVE.B #$DD,DMAFCR1(A0) * Initialize source operand address * Source address is equal to $6000. MOVE.L SARADD,DMASAR1(A0) * Initialize destination operand address * Destination address is equal to $8000. MOVE.L DARADD,DMADAR1(A0) * Initialize the byte transfer count register * The number of bytes to be transferred is $64 or 50 words MOVE.L NUMBYTE,DMABTC1(A0) * Channel control reg. init. and Start DMA transfers * No interrupts are enabled, destination (write) cycle. * Source address is not incremented. Increment the destination address. * Source size is word, destination size is word. REQ is internal. * 100% of bus bandwidth, dual-address transfers, start the DMA transfers. MOVE.W #$068D,DMACCR1(A0) END ***************************************************************************
Example 4: Cycle Steal Request Generation, Dual-Address Transfers.
*************************************************************************** * MC68341 basic DMA channel register initialization example code. * This code is used to initialize the 68341's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for external cycle steal request generation, * dual-address transfers. DMA 16-bit wide data from an odd address to an * even address. Control signals are asserted on the DMA read cycle. *************************************************************************** * Equates *************************************************************************** SARADD EQU $6001 source address is an ODD address DARADD EQU $10000 destination address is and EVEN address NUMBYTE EQU $14 number of bytes to transfer MOTOROLA MC68341 USER'S MANUAL 6-43
*************************************************************************** * Initialize DMA Channel 1 *************************************************************************** LEA MODBASE+DMACH1,A0 Pointer to channel 1 * Initialize DMA channel 1 MCR * Normal Operation, ignore FREEZE, dual-address mode. ISM field at 0. CPU32 * SR I2-I0 bits must be less than or equal to ISM bits for channel startup. * Supervisor/user reg. unrestricted, MAID field at 4. IARB priority at 8. MOVE.W #$00C8,(A0) * Clear channel control reg. * Clear STR (start) bit to prevent the channel from starting a transfer early. CLR.W DMACCR1(A0) * Initialize interrupt reg. * Interrupt priority at 7, interrupt vector at $42. MOVE.W #$0742,DMAINT1(A0) * Initialize channel status reg. * Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup. MOVE.B #$7C,DMACSR1(A0) * Initialize function code reg. * DMA space, supervisor data space for source and destination. MOVE.B #$DD,DMAFCR1(A0) * Initialize source operand address * Source address is equal to $6001, and odd address. MOVE.L SARADD,DMASAR1(A0) * Initialize destination operand address * Destination address is equal to $10000, and even address. MOVE.L DARADD,DMADAR1(A0) * Initialize the byte transfer count register * The number of bytes to be transferred is $14 or 20 bytes MOVE.L NUMBYTE,DMABTC1(A0) * Channel control reg. init. and Start DMA transfers * No interrupts are enabled, source (read) cycle. * Increment the source and destination addresses. * Source size is byte, destination size is word. REQ is external cycle steal. * dual-address transfers, start the DMA transfers. MOVE.W #$1DB1,DMACCR1(A0) END *************************************************************************** 6-44 MC68341 USER'S MANUAL MOTOROLA
6.10 MC68341 DMA ENHANCEMENTS
The MC68341 DMA module implementation adds three new signals - RDY1 , RDY2, and DTC - and a new delayed DACK operating mode to the original MC68340 DMA. These changes provide additional handshaking flexibility and minimize additional glue logic for single address transfers. RDY1 and RDY2 are multiplexed with timer signals TGATE and TIN, and DTC is multiplexed with FC3. Selection of these multiplexed pin functions, and normal versus delayed DACK assertion, is controlled by programming the Port C Pin Assignment Register in the SIM41. Refer to the PPARC register description in Section 4 SIM for initialization information.
6.10.1
RDY
Configuring TGATE/ RDY1 or TIN/ RD Y2 as a RDY input for single address transfers automatically enables the ready handshake function for that channel. In this mode, termination of the DMA transfer requires the assertion of both DSACK and RDY , instead of just DSACK. This feature allows a slow external peripheral device to delay termination of the DMA transfer until it has supplied data or is ready to receive data from memory. Like DSACK , RDY is an asynchronous input which is sampled on the falling edge of CLKOUT, but must be recognized one clock cycle sooner than DSACK to provide the same termination timing. If RDY is asserted for the same clock falling edge or a later edge than DSACK , termination of the bus cycle is controlled by RDY and will occur two clocks after RDY is recognized. An early internal DSACK termination (M68300 fast termination or 68000 3-clock termination) is delayed to the earliest external DSACK recognition point, forcing a minimum three clock bus cycle for M68300 transfers, and four clock for 68000 transfers. RDY can be held asserted between DMA cycles to allow DSACK to control termination of the cycle. Note that fast termination M68300 and 3-clock 68000 cycles are still forced to 3 clocks and 4 clocks, respectively. Note that RDY should not be enabled during dual address mode transfers.
6.10.2 Delayed DACK
Delayed DACK operation can be selected during single address transfers to delay assertion of DACK to the peripheral device on reads until memory has provided valid data on the data bus. For transfers from memory to device, DACK is asserted after DSACK is recognized. On device to memory transfers, DACK is asserted with AS. Delayed DACK programmed without RDY generates a one clock assertion of the DACK pin (except on fast termination cycles). Typically, delayed DACK is programmed with RDY to allow the peripheral to delay termination of the cycle and negation of DACK.
6.10.3
DTC
DTC is asserted for one clock at the end of all MC68341 bus cycles when selected (CPU or DMA) to indicate the bus transfer is complete. DTC does not assert for bus cycles terminated with a normal bus error or retry, but does assert for cycles terminated with late bus error or late retry.
MOTOROLA MC68341 USER'S MANUAL 6-45
DTC can be used by device or memory control logic during DMA transfers with RDY to detect the last clock of a bus cycle, before the address or data strobes negate. Since termination of the bus cycle is dependent on two different termination sources (DSACK and RDY ), neither the device nor the memory can deterministically predict the end of the bus cycle unless the alternate termination is also taken into account. DTC provides a direct end-of-transfer indication.
6.10.4 Timing Examples
Figures 6-17--6-20 show timing examples of the the DMA handshake signals used with M68300 bus cycles. DREQ timing is not shown in these examples. Figure 6-17 shows single-address burst reads from two-clock memory with RDY enabled. Although the memory interface in this example is configured for internal fast termination, enabling RDY delays termination until two clocks after RDY is recognized. The first bus cycle shows RDY asserted for the S2 falling edge - this causes the bus cycle to terminate two clocks later for a four clock bus cycle. If RDY remains asserted into the next DMA transfer, it is recognized asserted on the falling edge of S0 and the bus cycle ends two clocks later for a three clock bus cycle. A single address write with RDY enabled is shown in Figure 6-18. The memory interface in this example again uses fast termination, but end of the bus cycle is delayed by RDY . The assertion of DS and UWE /LWE is delayed until one clock after RDY is recognized to allow write data from the device to become valid before data strobes are asserted to memory. Figure 6-19 shows a single address read with both delayed DACK and RDY enabled. DACK remains negated until after DSACK from memory is recognized, allowing memory to place valid data on the bus before DACK is asserted to the peripheral device. The device asserts RDY to signal readiness to complete the transfer. In Figure 6-20, a single address write with delayed DACK and RDY is shown. DACK asserts immediately with AS in this example to select the device and gate its data onto the bus for the memory write. RDY asserts before DSACK , delaying the bus cycle until DSACK asserts.
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S0 CLOCK
S1
S2
S3
S4
S3
S4
S5
S0
S1
S2
S3
S4
S5
S0
FC/ADDR/SIZ R/W AS AS68K DS LDS/UDS LWE/UWE
D15-D0
DSACK1 RDYx, DACKx
DTC
BERR
Figure 6-17. M68300 Single Address Read with RDY
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S0 CLOCK
S1
S2
S3
S4
S3
S4
S5
S0
S1
S2
S3
S4
S5
S0
FC/ADDR/SIZ R/W AS AS68K DS LDS/UDS LWE/UWE
D15-D0
DSACK1 RDYx, DACKx
DTC
BERR
Figure 6-18. M68300 Single Address Write with
RDY
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S0 CLOCK
S1
S2
S3
S4
S3
S4
S3
S4
S3
S4
S5
S0
FC/ADDR/SIZ R/W AS
AS68K DS LDS/UDS LWE/UWE
D15-D0
DSACKx DACKx RDYx
DTC
BERR
Figure 6-19. M68300 Single Address Read with Delayed DACK and
RDY
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SECTION 7 SERIAL MODULE
The MC68341 serial module is a dual universal asynchronous/synchronous receiver/transmitter that interfaces directly to the CPU32 processor via the intermodule bus (IMB). The serial module, shown in Figure 7-1, consists of the following major functional areas: * Two Independent Serial Communication Channels (A and B) * Baud Rate Generator Logic * Internal Channel Control Logic * Interrupt Control Logic
CTSA RTSA RxDA TxDA RxRDYA TxRDYA CTSB RTSB RxDB TxDB
.. .
SERIAL COMMUNICATIONS CHANNELS A AND B
BAUD RATE GENERATOR LOGIC
X1 X2 SCLK
INTERNAL CHANNEL CONTROL LOGIC
INTERRUPT CONTROL LOGIC
Figure 7-1. Simplified Block Diagram
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7.1 MODULE OVERVIEW
Features of the serial module are as follows: * Two, Independent, Full-Duplex Asynchronous/Synchronous Receiver/Transmitter Channels * Quadruple-Buffered Receiver * Double-Buffered Transmitter * Independently Programmable Baud Rate for Each Receiver and Transmitter Selectable from: --19 Fixed Rates: 50 to 76.8k Baud --External 1x Clock or 16x Clock * Programmable Data Format: --Five to Eight Data Bits Plus Parity --Odd, Even, No Parity, or Force Parity --Nine-Sixteenths to Two Stop Bits Programmable in One-Sixteenth Bit Increments * Programmable Channel Modes: --Normal (Full Duplex) --Automatic Echo --Local Loopback --Remote Loopback * Automatic Wakeup Mode for Multidrop Applications * Seven Maskable Interrupt Conditions * Parity, Framing, and Overrun Error Detection * False Start-Bit Detection * Line-Break Detection and Generation * Detection of Breaks Originating in the Middle of a Character * Start/End Break Interrupt/Status * On-Chip Crystal Oscillator
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7.1.1 Serial Communication Channels A and B
Each communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter using an operating frequency independently selected from a baud rate generator or an external clock input. The transmitter accepts parallel data from the IMB, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits, then outputs a composite serial data stream on the channel transmitter serial data output (TxDx). Refer to 7.3.2.1 Transmitter for additional information. The receiver accepts serial data on the channel receiver serial data input (RxDx), converts it to parallel format, checks for a start bit, stop bit, parity (if any), or break condition, and transfers the assembled character onto the IMB during read operations. Refer to 7.3.2.2 Receiver for additional information.
7.1.2 Baud Rate Generator Logic
The crystal oscillator operates directly from a 3.6864-MHz crystal connected across the X1 input and the X2 output or from an external clock of the same frequency connected to X1. The clock serves as the basic timing reference for the baud rate generator and other internal circuits. The baud rate generator operates from the oscillator or external TTL clock input and is capable of generating 19 commonly used data communication baud rates ranging from 50 to 76.8k by producing internal clock outputs at 16 times the actual baud rate. Refer to 7.2 Serial Module Signal Definitions and 7.3.1 Baud Rate Generator for additional information. The external clock input (SCLK), which bypasses the baud rate generator, provides a synchronous clock mode of operation when used as a divide-by-1 clock and an asynchronous clock mode when used as a divide-by-16 clock. The external clock input allows the user to use SCLK as the only clock source for the serial module if multiple baud rates are not required.
7.1.3 Internal Channel Control Logic
The serial module receives operation commands from the CPU32 and, in turn, issues appropriate operation signals to the internal serial module control logic. This mechanism allows the registers within the module to be accessed and various commands to be performed. Refer to 7.4 Register Description and Programming for additional information.
7.1.4 Interrupt Control Logic
Seven interrupt request (IRQ7-IRQ1) signals are provided to notify the CPU32 that an interrupt has occurred. These interrupts are described in 7.4 Register Description and Programming. The interrupt status register (ISR) is read by the CPU32 to determine all
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currently active interrupt conditions. The interrupt enable register (IER) is programmable to mask any events that can cause an interrupt.
7.1.5 Comparison of the Serial Module to the MC68681
The serial module is code compatible with the MC68681 with some modifications. The following paragraphs describe the differences. The programming model is slightly altered. The supervisor/user block in the MC68341 closely follows the MC68681. The supervisor-only block has the following changes: * The interrupt vector register is moved from supervisor/user to supervisor only at a new address. * MR2A and MR2B are moved from a hidden address location to a location at the bottom of the programming model. The timer/counter is eliminated as well as all associated command and status registers. Only certain output port pins are available. There are no IP pins on the MC68341. RxRTS is more automated on the MC68341. The XTAL_RDY bit in the ISR should be polled until it is cleared to prevent an unstable frequency from being applied to the baud rate generator. The following pseudocode is an example: if (XTAL_RDY==0) begin write CSR end else begin wait jump loop end
7.2 SERIAL MODULE SIGNAL DEFINITIONS
The following paragraphs contain a brief description of the serial module signals. Figure 72 shows both the external and internal signal groups. NOTE The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false.
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ADDRESS BUS X1 INTERNAL CONTROL LOGIC S E R I A L M O D U L E I N T E R N A L B U S BAUD RATE GENERATOR LOGIC X2 SCLK
CONTROL IMB INTERFACE SIGNALS
DATA BUS D31-D0
DATA DATA BUS MUX D7-D0
CHANNEL A
FOUR-CHARACTER RECEIVE BUFFER
RxDA
TWO-CHARACTER TRANSMIT BUFFER
TxDA RTSA CTSA TxRDYA RxRDYA
.
EXTERNAL INTERFACE SIGNALS
CHANNEL B FOUR-CHARACTER RECEIVE BUFFER TWO-CHARACTER TRANSMIT BUFFER RxDB
TxDB RTSB CTSB
Figure 7-2. External and Internal Interface Signals
7.2.1 Crystal Input or External Clock (X1)
This input is one of two connections to a crystal or a single connection to an external clock. A crystal or an external clock signal, at 3.6864 MHz, must be supplied when using the baud rate generator. If a crystal is used, a capacitor of approximately 10 pF should be connected from this signal to ground. If this input is not used, it must be connected to VCC or GND. Refer to Section 11 Applications for an example of a clock driver circuit.
7.2.2 Crystal Output (X2)
This output is the additional connection to a crystal. If a crystal is used, a capacitor of approximately 5 pF should be connected from this signal to ground. If an external TTLlevel clock is used on X1, the X2 output must be left open. Refer to Section 11 Applications for an example of a clock driver circuit.
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7.2.3 External Input (SCLK)
This input can be used as the clock input for channel A and/or channel B and is programmable in the clock-select registers (CSR). When used as the receiver clock, received data is sampled on the rising edge of the clock. When used as the transmitter clock, data is output on the falling edge of the clock. If this input is not used, it must be connected to VCC or GND.
7.2.4 Channel A Transmitter Serial Data Output (TxDA)
This signal is the transmitter serial data output for channel A. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal on the falling edge of the clock source, with the least significant bit transmitted first.
7.2.5 Channel A Receiver Serial Data Input (RxDA)
This signal is the receiver serial data input for channel A. Data received on this signal is sampled on the rising edge of the clock source, with the least significant bit received first.
7.2.6 Channel B Transmitter Serial Data Output (TxDB)
This signal is the transmitter serial data output for channel B. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal at the falling edge of the clock source, with the least significant bit transmitted first.
7.2.7 Channel B Receiver Serial Data Input (RxDB)
This signal is the receiver serial data input for channel B. Data on this signal is sampled on the rising edge of the clock source, with the least significant bit received first.
7.2.8 Channel A Request-To-Send (RTSA)
This active-low output signal is programmable as the channel A request-to-send or as a dedicated parallel output. RTSA When used for this function, this signal can be programmed to be automatically negated and asserted by either the receiver or transmitter. When connected to the clear-to-send (CTS) input of a transmitter, this signal can be used to control serial data flow. OP0 When used for this function, this output is controlled by bit 0 in the output port data register (OP).
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7.2.9 Channel B Request-To-Send (RTSB)
This active-low output signal is programmable as the channel B request-to-send or as a dedicated parallel output. RTSB When used for this function, this signal can be programmed to be automatically negated and asserted by either the receiver or transmitter. When connected to the CTS input of a transmitter, this signal can be used to control serial data flow. OP1 When used for this function, this output is controlled by bit 1 in the OP.
7.2.10 Channel A Clear-To-Send (CTSA )
This active-low input is the channel A clear-to-send.
7.2.11 Channel B Clear-To-Send (CTSB )
This active-low input is the channel B clear-to-send.
7.2.12 Channel A Transmitter Ready (TRDYA )
This active-low output signal is programmable as the channel A transmitter ready or as a dedicated parallel output and cannot be masked by the IER. TRDYA When used for this function, this signal reflects the complement of the status of bit 2 of the channel A status register (SRA). This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character. OP6 When used for this function, this output is controlled by bit 6 in the OP.
7.2.13 Channel A Receiver Ready (RRDYA )
This active-low output signal is programmable as the channel A receiver ready, channel A first-in-first-out (FIFO) full indicator, or a dedicated parallel output and cannot be masked by the IER. RRDYA When used for this function, this signal reflects the complement of the status of bit 1 of the ISR. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver contains a character.
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FFULLA When used for this function, this signal reflects the complement of the status of bit 1 of the ISR. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver FIFO is full. OP4 When used for this function, this output is controlled by bit 4 in the OP.
7.3 OPERATION
The following paragraphs describe the operation of the baud rate generator, transmitter and receiver, and other functional operating modes of the serial module.
7.3.1 Baud Rate Generator
The baud rate generator consists of a crystal oscillator, baud rate generator, and clock selectors (see Figure 7-3). The crystal oscillator operates directly from a 3.6864-MHz crystal or from an external clock of the same frequency. The SCLK input bypasses the baud rate generator and provides a synchronous clock mode of operation when used as a divide-by-1 clock and an asynchronous clock mode when used as a divide-by-16 clock. The clock is selected by programming the CSR for each channel.
BAUD RATE GENERATOR LOGIC CRYSTAL OSCILLATOR
.. .. .
EXTERNAL INTERFACE X1
BAUD RATE GENERATOR
X2 SCLK
CLOCK SELECTORS
Figure 7-3. Baud Rate Generator Block Diagram
7.3.2 Transmitter and Receiver Operating Modes
The functional block diagram of the transmitter and receiver, including command and operating registers, is shown in Figure 7-4. The paragraphs that follow contain descriptions for both these functions in reference to this diagram. For detailed register information, refer to 7.4 Register Description and Programming.
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CHANNEL A COMMAND REGISTER (CRA) W
EXTERNAL INTERFACE
MODE REGISTER A (MR1A) MODE REGISTER B (MR2A)
R/W R/W
STATUS REGISTER (SRA)
R
TRANSMIT BUFFER (TBA) (2 REGISTERS)
TRANSMIT HOLDING REGISTER TRANSMIT SHIFT REGISTER
W TxDA
RECEIVER HOLDING REGISTER 1 RECEIVER HOLDING REGISTER 2 RECEIVE BUFFER (RBA) (4 REGISTERS) RECEIVER HOLDING REGISTER 3 RECEIVER SHIFT REGISTER
R
FIFO
RxDA
CHANNEL B COMMAND REGISTER (CRB) W
MODE REGISTER 1 (MR1B) MODE REGISTER 2 (MR2B)
R/W R/W
STATUS REGISTER (SRB)
R
TRANSMIT BUFFER (TBB) (2 REGISTERS)
TRANSMIT HOLDING REGISTER TRANSMIT SHIFT REGISTER
W
TxDB
RECEIVER HOLDING REGISTER 1 RECEIVER HOLDING REGISTER 2 RECEIVE BUFFER (RBB) (4 REGISTERS) NOTE: R/W = READ/WRITE R = READ W = WRITE RECEIVER HOLDING REGISTER 3 RECEIVER SHIFT REGISTER
R
FIFO
RxDB
.. .. . . .
Figure 7-4. Transmitter and Receiver Functional Diagram
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7.3.2.1 TRANSMITTER. The transmitters are enabled through their respective command registers (CR) located within the serial module. The serial module signals the CPU32 when it is ready to accept a character by setting the transmitter-ready bit (TxRDY) in the channel's status register (SR). Functional timing information for the transmitter is shown in Figure 7-5. The transmitter converts parallel data from the CPU32 to a serial bit stream on TxDx. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Data is shifted from the transmitter output on the falling edge of the clock source.
C1 IN TRANSMISSION
TxDx
C1
C2
C3
BREAK
C4
C6
TRANSMITTER ENABLED
TxRDY (SR2)
CS
W C1
W C2
W C3
W START BREAK
W C4
W STOP BREAK
W C5 NOT TRANSMITTED
W C6
CTS 1
RTS 2
MANUALLY ASSERTED BY BIT- SET COMMAND
MANUALLY ASSERTED
.. .. . . . ..
NOTES: 1. TIMING SHOWN FOR MR2(4) = 1 2. TIMING SHOWN FOR MR2(5) = 1 3. CN = TRANSMIT CHARACTER 4. W = WRITE
Figure 7-5. Transmitter Timing Diagram
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Following transmission of the stop bits, if a new character is not available in the transmitter holding register, the TxDx output remains high ('mark' condition), and the transmitter empty bit (TxEMP) in the SR is set. Transmission resumes and the TxEMP bit is cleared when the CPU32 loads a new character into the transmitter buffer (TB). If a disable command is sent to the transmitter, it continues operating until the character in the transmit shift register, if any, is completely sent out. If the transmitter is reset through a software command, operation ceases immediately (refer to 7.4.1.3 Command Register (CR)). The transmitter is re-enabled through the CR to resume operation after a disable or software reset. If clear-to-send operation is enabled, CTS must be asserted for the character to be transmitted. If CTS is negated in the middle of a transmission, the character in the shift register is transmitted, and TxDx remains in the 'mark' state until CTS is asserted again. If the transmitter is forced to send a continuous low condition by issuing a send break command, the state of CTS is ignored by the transmitter. The transmitter can be programmed to automatically negate request-to-send (RTS) outputs upon completion of a message transmission. If the transmitter is programmed to operate in this mode, RTS must be manually asserted before a message is transmitted. In applications in which the transmitter is disabled after transmission is complete and RTS is appropriately programmed, RTS is negated one bit time after the character in the shift register is completely transmitted. The transmitter must be manually re-enabled by reasserting RTS before the next message is to be sent. 7.3.2.2 RECEIVER. The receivers are enabled through their respective CRs located within the serial module. Functional timing information for the receiver is shown in Figure 7-6. The receiver looks for a high-to-low (mark-to-space) transition of the start bit on RxDx. When a transition is detected, the state of RxDx is sampled each 16x clock for eight clocks, starting one-half clock after the transition (asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). If RxDx is sampled high, the start bit is invalid, and the search for the valid start bit begins again. If RxDx is still low, a valid start bit is assumed, and the receiver continues to sample the input at one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. Data on the RxDx input is sampled on the rising edge of the programmed clock source. The least significant bit is received first. The data is then transferred to a receiver holding register, and the RxRDY bit in the appropriate SR is set. If the character length is less than eight bits, the most significant unused bits in the receiver holding register are cleared. After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a nonzero character is received without a stop bit (framing error) and RxDx remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit is detected. The parity error (PE), framing error (FE), overrun error (OE), and received break (RB) conditions (if any) set error and break flags in the appropriate SR at the received character boundary and are valid only when the RxRDY bit in the SR is set.
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RxD
C1
C2
C3
C4
C5
C6
C7
C8
C6, C7, C8 ARE LOST
RECEIVER ENABLED
RxRDY (SR0)
FFULL (SR1)
RxRDYA
CS R R STATUS DATA C1 OVERRUN (SR4) C5 LOST RR R RRR STATUS DATA STATUS DATA STATUS DATA C2 C3 C4
RTS 1
RESET BY COMMAND
OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1 2. Timing shown for OPCR(4) = 1 and MR1(6) = 0 3. R = Read 4. C N = Received Character
Figure 7-6. Receiver Timing Diagram If a break condition is detected (RxDx is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register, and the receive buffer (RB) and RxRDY bits in the SR are set. The RxDx signal must return to a high condition for at least one-half bit time before a search for the next start bit begins. The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. When the break begins in the middle of a character, the receiver places the damaged character in the receiver FIFO stack and sets the corresponding error conditions and RxRDY bit in the SR. Then, if the break persists
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until the next character time, the receiver places an all-zero character into the receiver FIFO and sets the corresponding RB and RxRDY bits in the SR. 7.3.2.3 FIFO STACK. The FIFO stack is used in each channel's receiver buffer logic. The stack consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the RxDx (refer to Figure 7-4). Data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO. Thus, data flowing from the receiver to the CPU32 is quadruple buffered. In addition to the data byte, three status bits, PE, FE, and RB, are appended to each data character in the FIFO; OE is not appended. By programming the ERR bit in the channel's mode register (MR1), status is provided in character or block modes. The RxRDY bit in the SR is set whenever one or more characters are available to be read by the CPU32. A read of the receiver buffer produces an output of data from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and its associated status bits are 'popped', and new data can be added at the bottom of the stack by the receiver shift register. The FIFO-full status bit (FFULL) is set if all three stack positions are filled with data. Either the RxRDY or FFULL bit can be selected to cause an interrupt. In the character mode, status provided in the SR is given on a character-by-character basis and thus applies only to the character at the top of the FIFO. In the block mode, the status provided in the SR is the logical OR of all characters coming to the top of the FIFO stack since the last reset error command. A continuous logical OR function of the corresponding status bits is produced in the SR as each character reaches the top of the FIFO stack. The block mode is useful in applications where the software overhead of checking each character's error cannot be tolerated. In this mode, entire messages are received, and only one data integrity check is performed at the end of the message. This mode allows a data-reception speed advantage, but does have a disadvantage since each character is not individually checked for error conditions by software. If an error occurs within the message, the error is not recognized until the final check is performed, and no indication exists as to which character in the message is at fault. In either mode, reading the SR does not affect the FIFO. The FIFO is 'popped' only when the receive buffer is read. The SR should be read prior to reading the receive buffer. If all three of the FIFO's receiver holding registers are full when a new character is received, the new character is held in the receiver shift register until a FIFO position is available. If an additional character is received during this state, the contents of the FIFO are not affected. However, the character previously in the receiver shift register is lost, and the OE bit in the SR is set when the receiver detects the start bit of the new overrunning character. To support control flow capability, the receiver can be programmed to automatically negate and assert RTS. When in this mode, RTS is automatically negated by the receiver when a valid start bit is detected and the FIFO stack is full. When a FIFO position
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becomes available, RTS is asserted by the receiver. Using this mode of operation, overrun errors are prevented by connecting the RTS to the CTS input of the transmitting device. If the FIFO stack contains characters and the receiver is disabled, the characters in the FIFO can still be read by the CPU32. If the receiver is reset, the FIFO stack and all receiver status bits, corresponding output ports, and interrupt request are reset. No additional characters are received until the receiver is re-enabled.
7.3.3 Looping Modes
Each serial module channel can be configured to operate in various looping modes as shown in Figure 7-7. These modes are useful for local and remote system diagnostic functions. The modes are described in the following paragraphs with further information available in 7.4 Register Description and Programming. The channel's transmitter and receiver should both be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. 7.3.3.1 AUTOMATIC ECHO MODE. In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU32-to-receiver communication continues normally, but the CPU32-to-transmitter link is disabled. While in this mode, received data is clocked on the receiver clock and retransmitted on TxDx. The receiver must be enabled, but the transmitter need not be enabled. Since the transmitter is not active, the SR TxEMP and TxRDY bits are inactive, and data is transmitted as it is received. Received parity is checked, but not recalculated for transmission. Character framing is also checked, but stop bits are transmitted as received. A received break is echoed as received until the next valid start bit is detected. 7.3.3.2 LOCAL LOOPBACK MODE. In this mode, TxDx is internally connected to RxDx. This mode is useful for testing the operation of a local serial module channel by sending data to the transmitter and checking data assembled by the receiver. In this manner, correct channel operations can be assured. Also, both transmitter and CPU32-to-receiver communications continue normally in this mode. While in this mode, the RxDx input data is ignored, the TxDx is held marking, and the receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be enabled. 7.3.3.3 REMOTE LOOPBACK MODE. In this mode, the channel automatically transmits received data on the TxDx output on a bit-by-bit basis. The local CPU32-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote channel. While in this mode, the receiver clock is used for the transmitter. Since the receiver is not active, received data cannot be read by the CPU32, and the error status conditions are inactive. Received parity is not checked and is not recalculated for transmission. Stop bits are transmitted as received. A received break is echoed as received until the next valid start bit is detected.
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Rx CPU DISABLED Tx DISABLED
RxDx INPUT
TxDx OUTPUT
(a) Automatic Echo
Rx CPU Tx
DISABLED
RxDx INPUT
DISABLED
TxDx OUTPUT
(b) Local Loopback
DISABLED CPU DISABLED
Rx
DISABLED
RxDx INPUT
Tx
DISABLED
TxDx OUTPUT
(c) Remote Loopback
Figure 7-7. Looping Modes Functional Diagram
7.3.4 Multidrop Mode
A channel can be programmed to operate in a wakeup mode for multidrop or multiprocessor applications. Functional timing information for the multidrop mode is shown in Figure 7-8. The mode is selected by setting bits 3 and 4 in mode register 1 (MR1). This mode of operation allows the master station to be connected to several slave stations (maximum of 256). In this mode, the master transmits an address character followed by a block of data characters targeted for one of the slave stations. The slave stations have their channel receivers disabled. However, they continuously monitor the data stream sent out by the master station. When an address character is sent by the master, the slave receiver channel notifies its respective CPU by setting the RxRDY bit in the SR and generating an interrupt (if programmed to do so). Each slave station CPU then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station. Slave stations not addressed continue to monitor the data stream for the next address character. Data fields in the data stream are separated by an address character. After a slave receives a block of data, the slave station's CPU disables the receiver and initiates the process again.
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MASTER STATION TxD
A/D ADDR 1 1 C0
A/D 0
A/D ADDR 1 2
TRANSMITTER ENABLED
TxRDY (SR2)
CS W MR1(4:3) = 11 MR1(2) = 1 PERIPHERAL STATION RxD A/D 0 W W ADDR1 W MR1(2) = 0 MR1(2) = 1 W W ADDR2
A/D ADDR 1 1 C0
A/D 0
A/D ADDR 1 2
A/D 0
RECEIVER ENABLED
RxRDY (SR0)
W ENABLE
CS W MR1(4-3) = 11 R ADDR R R STATUS DATA C0 R R STATUS DATA ADDR
Figure 7-8. Multidrop Mode Timing Diagram A transmitted character from the master station consists of a start bit, a programmed number of data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. The A/D bit identifies the type of character being transmitted to the slave station. The character is interpreted as an address character if the A/D bit is set or as a data character if the A/D bit is cleared. The polarity of the A/D bit is selected by programming bit 2 of the MR1. The MR1 should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer. In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and loads the character into the receiver holding register FIFO stack provided the received A/D bit is a one (address tag). The character is discarded if the received A/D bit is a zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU32 via the receiver holding register stack during read operations.
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In either case, the data bits are loaded into the data portion of the stack while the A/D bit is loaded into the status portion of the stack normally used for a parity error (SR bit 5). Framing error, overrun error, and break detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this mode may still contain error detection and correction information. One way to provide error detection, if 7-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character.
7.3.5 Bus Operation
This section describes the operation of the IMB during read, write, and interrupt acknowledge cycles to the serial module. All serial module registers must be accessed as bytes. 7.3.5.1 READ CYCLES. The serial module is accessed by the CPU32 with no wait states. The serial module responds to byte reads. Reserved registers return logic zero during reads. 7.3.5.2 WRITE CYCLES. The serial module is accessed by the CPU32 with no wait states. The serial module responds to byte writes. Write cycles to read-only registers and reserved registers complete in a normal manner without exception processing; however, the data is ignored. 7.3.5.3 INTERRUPT ACKNOWLEDGE CYCLES. The serial module is capable of arbitrating for interrupt servicing and supplying the interrupt vector when it has successfully won arbitration. The vector number must be provided if interrupt servicing is necessary; thus, the interrupt vector register (IVR) must be initialized. If the IVR is not initialized, a spurious interrupt exception will be taken if interrupts are generated.
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7.4 REGISTER DESCRIPTION AND PROGRAMMING
This section contains a detailed description of each register and its specific function as well as flowcharts of basic serial module programming.
7.4.1 Register Description
The operation of the serial module is controlled by writing control bytes into the appropriate registers. A list of serial module registers and their associated addresses are shown in Figure 7-9. The mode, status, command, and clock-select registers are duplicated for each channel to provide independent operation and control. NOTE All serial module registers are only accessible as bytes. The contents of the mode registers (MR1 and MR2), CSR, and the auxiliary control register (ACR) bit 7 should only be changed after the receiver/transmitter is issued a software RESET command--i.e., channel operation must be disabled. Care should also be taken if the register contents are changed during receiver/transmitter operations, as undesirable results may be produced. The registers of the serial module are discussed in the following paragraphs in alphabetical order. The numbers in the upper right-hand corner indicate the offset of the register from the base address specified in the module base address register (MBAR) in the SIM41. The numbers above the register description represent the bit position in the register. The register description contains the mnemonic for the bit. The values shown below the register description are the values of those register bits after a hardware reset. A value of U indicates that the bit value is unaffected by reset. The read/write status and the access privilege are shown in the last line. NOTE A CPU32 RESET instruction will not affect the MCR, but will reset all the other serial module registers as though a hardware reset had occurred. The module is enabled when the STP bit in the MCR is cleared. The module is disabled when the STP bit in the MCR is set.
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Address 700 701 702 703 704 705
FC S1 S S S S S S/U2 S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U
Register Read (R/W = 1) MCR (HIGH BYTE) MCR (LOW BYTE) DO NOT ACCESS3 DO NOT ACCESS3 INTERRUPT LEVEL (ILR) INTERRUPT VECTOR (IVR)
Register Write (R/W = 0) MCR (HIGH BYTE) MCR (LOW BYTE) DO NOT ACCESS3 DO NOT ACCESS3 INTERRUPT LEVEL (ILR) INTERRUPT VECTOR (IVR)
710 711 712 713 714 715 716 717 718 719 71A 71B 71C 71D 71E 71F 720 721
MODE REGISTER 1A (MR1A) STATUS REGISTER A (SRA) DO NOT ACCESS3 RECEIVER BUFFER A (RBA) INPUT PORT CHANGE REGISTER (IPCR) INTERRUPT STATUS REGISTER (ISR) DO NOT ACCESS3 DO NOT ACCESS3 MODE REGISTER 1B (MR1B) STATUS REGISTER B (SRB) DO NOT ACCESS3 RECEIVER BUFFER B (RBB) DO NOT ACCESS3 INPUT PORT REGISTER (IP) DO NOT ACCESS3 DO NOT ACCESS3 MODE REGISTER 2A (MR2A) MODE REGISTER 2B (MR2B)
MODE REGISTER 1A (MR1A) CLOCK-SELECT REGISTER A (CSRA) COMMAND REGISTER A (CRA) TRANSMITTER BUFFER A (TBA) AUXILIARY CONTROL REGISTER (ACR) INTERRUPT ENABLE REGISTER (IER) DO NOT ACCESS3 DO NOT ACCESS3 MODE REGISTER 1B (MR1B) CLOCK-SELECT REGISTER B (CSRB) COMMAND REGISTER B (CRB) TRANSMITTER BUFFER B (TBB) DO NOT ACCESS3 OUTPUT PORT CONTROL REGISTER (OPCR) OUTPUT PORT (OP)4 BIT SET OUTPUT PORT (OP)4 BIT RESET MODE REGISTER 2A (MR2A) MODE REGISTER 2B (MR2B)
NOTES: 1. S = Register permanently defined as supervisor-only access 2. S/U = Register programmable as either supervisor or user access 3. A read or write to these locations currently has no effect. 4. Address-triggered commands
Figure 7-9. Serial Module Programming Model
MOTOROLA
MC68341 USER'S MANUAL
7-19
7.4.1.1 AUXILIARY CONTROL REGISTER (ACR). The ACR selects which baud rate is used and controls the handshake of the transmitter/receiver. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). ACR
7 BRG RESET: 0 6 0 5 0 4 0 3 0 2 0 1 IECB
$714
0 IECA
0
0
0
0
0
0
0
Write Only
Supervisor/User
BRG--Baud Rate Generator Set Select 1 = Set 2 of the available baud rates is selected. 0 = Set 1 of the available baud rates is selected. Refer to 7.4.1.2 Clock-Select Register (CSR) for more information on the baud rates. IECB, IECA--Input Enable Control 1 = ISR bit 7 will be set and an interrupt will be generated when the corresponding bit in the IPCR (COSB or COSA) is set by an external transition on the channel's CTS input (if bit 7 of the IER) is set to enable interrupts). 0 = Setting the corresponding bit in the IPCR has no effect on ISR bit 7. 7.4.1.2 CLOCK-SELECT REGISTER (CSR). The CSR selects the baud rate clock for the channel receiver and transmitter. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). NOTE This register should only be written after the external crystal is stable (XTAL_RDY bit of the ISR is zero). CSRA, CSRB
7 RCS3 RESET: 0 6 RCS2 5 RCS1 4 RCS0 3 TCS3 2 TCS2
$711, $719
1 TCS1 0 TCS0
0
0
0
0
0
0
0
Write Only
Supervisor/User
RCS3-RCS0--Receiver Clock Select These bits select the baud rate clock for the channel receiver from a set of baud rates listed in Table 7-1. The baud rate set selected depends upon the ACR bit 7. Set 1 is selected if ACR bit 7 = 0, and set 2 is selected if ACR bit 7 = 1. The receiver clock is always 16 times the baud rate shown in this list, except when SCLK is used.
7-20
MC68341 USER'S MANUAL
MOTOROLA
Table 7-1. RCSx Control Bits
RCS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RCS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RCS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RCS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Set 1 50 110 134.5 200 300 600 1200 1050 2400 4800 7200 9600 38.4k 76.8k SCLK/16 SCLK/1 Set 2 75 110 134.5 150 300 600 1200 2000 2400 4800 1800 9600 19.2k 38.4k SCLK/16 SCLK/1
TCS3-TCS0--Transmitter Clock Select These bits select the baud rate clock for the channel transmitter from a set of baud rates listed in Table 7-2. The baud rate set selected depends upon ACR bit 7. Set 1 is selected if ACR bit 7 = 0, and set 2 is selected if ACR bit 7 = 1. The transmitter clock is always 16 times the baud rate shown in this list, except when SCLK is used.
MOTOROLA
MC68341 USER'S MANUAL
7-21
Table 7-2 . TCSx Control Bits
TCS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TCS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TCS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TCS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Set 1 50 110 134.5 200 300 600 1200 1050 2400 4800 7200 9600 38.4k 76.8k SCLK/16 SCLK/1 Set 2 75 110 134.5 150 300 600 1200 2000 2400 4800 1800 9600 19.2k 38.4k SCLK/16 SCLK/1
7.4.1.3 COMMAND REGISTER (CR). The CR is used to supply commands to the channel. Multiple commands can be specified in a single write to the CR if the commands are not conflicting--e.g., reset transmitter and enable transmitter commands cannot be specified in a single command. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). CRA, CRB
7 MISC3 RESET: 0 6 MISC2 5 MISC1 4 MISC0 3 TC1 2 TC0
$712, $71A
1 RC1 0 RC0
0
0
0
0
0
0
0
Write Only
Supervisor/User
MISC3-MISC0--Miscellaneous Commands These bits select a single command as listed in Table 7-3.
7-22
MC68341 USER'S MANUAL
MOTOROLA
Table 7-3. MISCx Control Bits
MISC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MISC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MISC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MISC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Command No Command No Command Reset Receiver Reset Transmitter Reset Error Status Reset Break-Change Interrupt Start Break Stop Break Assert RTS Negate RTS No Command No Command No Command No Command No Command No Command
Reset Receiver--The reset receiver command resets the channel receiver. The receiver is immediately disabled, the FFULL and RxRDY bits in the SR are cleared, and the receiver FIFO pointer is reinitialized. All other registers are unaltered. This command should be used in lieu of the receiver disable command whenever the receiver configuration is changed because it places the receiver in a known state. Reset Transmitter--The reset transmitter command resets the channel transmitter. The transmitter is immediately disabled, and the TxEMP and TxRDY bits in the SR are cleared. All other registers are unaltered. This command should be used in lieu of the transmitter disable command whenever the transmitter configuration is changed because it places the transmitter in a known state. Reset Error Status--The reset error status command clears the channel's RB, FE, PE, and OE bits (in the SR). This command is also used in the block mode to clear all error bits after a data block is received. Reset Break-Change Interrupt--The reset break-change interrupt command clears the delta break (DBx) bits in the ISR.
MOTOROLA
MC68341 USER'S MANUAL
7-23
Start Break--The start break command forces the channel's TxDx low. If the transmitter is empty, the start of the break conditions can be delayed up to one bit time. If the transmitter is active, the break begins when transmission of the character is complete. If a character is in the transmitter shift register, the start of the break is delayed until the character is transmitted. If the transmitter holding register has a character, that character is transmitted after the break. The transmitter must be enabled for this command to be accepted. The state of the CTS input is ignored for this command. Stop Break--The stop break command causes the channel's TxDx to go high (mark) within two bit times. Characters stored in the transmitter buffer, if any, are transmitted. Assert RTS --The assert RTS command forces the channel's RTS output low. Negate RTS --The negate RTS command forces the channel's RTS output high. TC1-TC0--Transmitter Commands These bits select a single command as listed in Table 7-4. Table 7-4. TCx Control Bits
TC1 0 0 1 1 TC0 0 1 0 1 Command No Action Taken Enable Transmitter Disable Transmitter Do Not Use
No Action Taken--The no action taken command causes the transmitter to stay in its current mode. If the transmitter is enabled, it remains enabled; if disabled, it remains disabled. Transmitter Enable--The transmitter enable command enables operation of the channel's transmitter. The TxEMP and TxRDY bits in the SR are also set. If the transmitter is already enabled, this command has no effect. Transmitter Disable--The transmitter disable command terminates transmitter operation and clears the TxEMP and TxRDY bits in the SR. However, if a character is being transmitted when the transmitter is disabled, the transmission of the character is completed before the transmitter becomes inactive. If the transmitter is already disabled, this command has no effect. Do Not Use--Do not use this bit combination because the result is indeterminate. RC1-RC0--Receiver Commands These bits select a single command as listed in Table 7-5.
7-24
MC68341 USER'S MANUAL
MOTOROLA
Table 7-5. RCx Control Bits
RC1 0 0 1 1 RC0 0 1 0 1 Command No Action Taken Enable Receiver Disable Receiver Do Not Use
No Action Taken--The no action taken command causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled. Receiver Enable--The receiver enable command enables operation of the channel's receiver. If the serial module is not in multidrop mode, this command also forces the receiver into the search-for-start-bit state. If the receiver is already enabled, this command has no effect. Receiver Disable--The receiver disable command disables the receiver immediately. Any character being received is lost. The command has no effect on the receiver status bits or any other control register. If the serial module is programmed to operate in the local loopback mode or multidrop mode, the receiver operates even though this command is selected. If the receiver is already disabled, this command has no effect. Do Not Use--Do not use this bit combination because the result is indeterminate. 7.4.1.4 INPUT PORT CHANGE REGISTER (IPCR). The IPCR shows the current state and the change-of-state for the CTSA and CTSB pins. This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared). IPCR
7 0 RESET: 0 6 0 5 COSB 4 COSA 3 0 2 0 1 CTSB
$714
0 CTSA
0
0
0
0
0
U
U
Read Only Bits 7, 6, 3, 2--Reserved by Motorola
Supervisor/User
COSB, COSA--Change-of-State 1 = A change-of-state (high-to-low or low-to-high transition), lasting longer than 25- 50 s when using a crystal as the sampling clock or longer than one or two periods when using SCLK, has occurred at the corresponding CTS input (MCR ICCS bit controls selection of the sampling clock for clear-to-send operation). When these bits are set, the ACR can be programmed to generate an interrupt to the CPU32. 0 = The CPU32 has read the IPCR. No change-of-state has occurred. A read of the IPCR also clears the ISR COS bit.
MOTOROLA MC68341 USER'S MANUAL 7-25
CTSB, CTSA--Current State Starting two serial clock periods after reset, the CTS bits reflect the state of the CTS pins. If a CTS pin is detected as asserted at that time, the associated COSx bit will be set, which will initiate an interrupt if the corresponding IECx bit of the ACR register is enabled. 1 = The current state of the respective CTS input is negated. 0 = The current state of the respective CTS input is asserted. 7.4.1.5 INPUT PORT REGISTER (IP). The IP shows the current state of the CTS inputs. This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared). IP
7 0 RESET: 0 6 0 5 0 4 0 3 0 2 0 1 CTSB
$71D
0 CTSA
0
0
0
0
0
U
U
Read Only
Supervisor/User
CTSB, CTSA--Current State 1 = The current state of the respective CTS input is negated. 0 = The current state of the respective CTS input is asserted. The information contained in these bits is latched and reflects the state of the input pins at the time that the IP is read. NOTE These bits have the same function and value of the IPCR bits 1 and 0.
7-26
MC68341 USER'S MANUAL
MOTOROLA
7.4.1.6 INTERRUPT ENABLE REGISTER (IER). The IER selects the corresponding bits in the ISR that cause an interrupt output (IRQ). If one of the bits in the ISR is set and the corresponding bit in the IER is also set, the IRQ output is asserted. If the corresponding bit in the IER is zero, the state of the bit in the ISR has no effect on the IRQ output. The IER does not mask the reading of the ISR. The ISR XTAL_RDY bit cannot be enabled to generate an interrupt. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). IER
7 COS RESET: 0 6 DBB 5 4 3 0 2 DBA 1 RxRDYB TxRDYB
$715
0 RxRDYA TxRDYA
0
0
0
0
0
0
0
Write Only COS--Change-of-State 1 = Enable interrupt 0 = Disable interrupt DBB--Delta Break B 1 = Enable interrupt 0 = Disable interrupt RxRDYB--Channel B Receiver Ready or FIFO full 1 = Enable interrupt 0 = Disable interrupt TxRDYB--Channel B Transmitter Ready 1 = Enable interrupt 0 = Disable interrupt Bit 3--Reserved by Motorola DBA--Delta Break A 1 = Enable interrupt 0 = Disable interrupt RxRDYA--Channel A Receiver Ready or FIFO full 1 = Enable interrupt 0 = Disable interrupt TxRDYA--Channel A Transmitter Ready 1 = Enable interrupt 0 = Disable interrupt
Supervisor/User
MOTOROLA
MC68341 USER'S MANUAL
7-27
7.4.1.7 INTERRUPT LEVEL REGISTER (ILR). The ILR contains the priority level for the serial module interrupt request. When the serial module is enabled (i.e., the STP bit in the MCR is cleared), this register can be read or written to at any time while in supervisor mode. ILR
7 0 RESET: 0 6 0 5 0 4 0 3 0 2 IL2 1 IL1
$704
0 IL0
0
0
0
0
0
0
0
Read/Write Bits 7-3--Reserved by Motorola
Supervisor Only
IL2-IL0--Interrupt Level Bits Each module that can generate interrupts has an interrupt level field. The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQ signal. The CPU32 uses this value to determine servicing priority. The hardware reset value of $00 will not generate any interrupts. See Section 5 CPU030 for more information. 7.4.1.8 INTERRUPT STATUS REGISTER (ISR). The ISR provides status for all potential interrupt sources. The contents of this register are masked by the IER. If a flag in the ISR is set and the corresponding bit in IER is also set, the IRQ output is asserted. If the corresponding bit in the IER is cleared, the state of the bit in the ISR has no effect on the output. This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared). NOTE The IER does not mask reading of the ISR. True status is provided regardless of the contents of IER. The contents of ISR are cleared when the serial module is reset. ISR
7 COS 6 DBB 5 4 3 2 DBA 1 RxRDYB TxRDYB XTAL_ RDY
$715
0 RxRDYA TxRDYA
RESET: 0
0
0
0
1
0
0
0
Read Only
Supervisor/User
COS--Change-of-State 1 = A change-of-state has occurred at one of the CTS inputs and has been selected to cause an interrupt by programming bit 1 and/or bit 0 of the ACR. 0 = The CPU32 has read the IPCR.
7-28
MC68341 USER'S MANUAL
MOTOROLA
DBB--Delta Break B 1 = The channel B receiver has detected the beginning or end of a received break. 0 = The CPU32 has issued a channel B reset break-change interrupt command. Refer to 7.4.1.3 Command Register (CR) for more information on the reset break-change interrupt command. RxRDYB--Channel B Receiver Ready or FIFO Full The function of this bit is programmed by MR1B bit 6. 1 = If programmed as receiver ready, a character has been received in channel B and is waiting in the receiver buffer FIFO. If programmed as FIFO full, a character has been transferred from the receiver shift register to the FIFO, and the transfer has caused the channel B FIFO to become full (all three positions are occupied). 0 = If programmed as receiver ready, the CPU32 has read the RB. After this read, if more characters are still in the FIFO, the bit is set again after the FIFO is 'popped'. If programmed as FIFO full, the CPU32 has read the RB. If a character is waiting in the receiver shift register because the FIFO is full, the bit will be set again when the waiting character is loaded into the FIFO. TxRDYB--Channel B Transmitter Ready This bit is the duplication of the TxRDY bit in SRB. 1 = The transmitter holding register is empty and ready to be loaded with a character. This bit is set when the character is transferred to the transmitter shift register. This bit is also set when the transmitter is first enabled. Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted. 0 = The transmitter holding register was loaded by the CPU32, or the transmitter is disabled. XTAL_RDY--Serial Clock Running This bit is always read as a zero when the X1 clock is running. This bit cannot be enabled to generate an interrupt. 1 = This bit is set at reset. 0 = This bit is cleared after the baud rate generator is stable. The CSR should not be accessed until this bit is zero. DBA--Delta Break A 1 = The channel A receiver has detected the beginning or end of a received break. 0 = The CPU32 has issued a channel A reset break-change interrupt command. Refer to 7.4.1.3 Command Register (CR) for more information on the reset break-change interrupt command.
MOTOROLA
MC68341 USER'S MANUAL
7-29
RxRDYA--Channel A Receiver Ready or FIFO Full The function of this bit is programmed by MR1A bit 6. 1 = If programmed as receiver ready, a character has been received in channel A and is waiting in the receiver buffer FIFO. If programmed as FIFO full, a character has been transferred from the receiver shift register to the FIFO, and the transfer has caused the channel A FIFO to become full (all three positions are occupied). 0 = If programmed as receiver ready, the CPU32 has read the receiver buffer. After this read, if more characters are still in the FIFO, the bit is set again after the FIFO is 'popped'. If programmed as FIFO full, the CPU32 has read the receiver buffer. If a character is waiting in the receiver shift register because the FIFO is full, the bit will be set again when the waiting character is loaded into the FIFO. TxRDYA--Channel A Transmitter Ready This bit is the duplication of the TxRDY bit in SRA. 1 = The transmitter holding register is empty and ready to be loaded with a character. This bit is set when the character is transferred to the transmitter shift register. This bit is also set when the transmitter is first enabled. Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted. 0 = The transmitter holding register was loaded by the CPU32, or the transmitter is disabled. 7.4.1.9 INTERRUPT VECTOR REGISTER (IVR). The IVR contains the 7-bit vector number of the interrupt. When the serial module is enabled (i.e., the STP bit in the MCR is cleared), this register can be read or written to at any time while in supervisor mode. IVR
7 IVR7 RESET: 0 6 IVR6 5 IVR5 4 IVR4 3 IVR3 2 IVR2 1 IVR1
$705
0 IVR0
0
0
0
1
1
1
1
Read /Write
Supervisor Only
IVR7-IVR0--Interrupt Vector Bits Each module that generates interrupts has an interrupt vector field. This 7-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. The IVR is reset to $0F, which indicates an uninitialized interrupt condition. See Section 5 CPU32 for more information.
7-30
MC68341 USER'S MANUAL
MOTOROLA
7.4.1.10 MODULE CONFIGURATION REGISTER (MCR). The MCR controls the serial module configuration. This register can be either read or written when the module is enabled and is in the supervisor state. The MCR is not affected by a CPU32 RESET instruction. Only the MCR can be accessed when the module is disabled (i.e., the STP bit in the MCR is set). MCR
15 STP RESET: 0 14 FRZ1 13 FRZ0 12 ICCS 11 0 10 0 9 0 8 0 7 SUPV 6 0 5 0 4 0 3 2 IARB 1
$700
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Read/Write
Supervisor Only
STP--Stop Mode Bit 1 = The serial module will be disabled. Setting the STP bit stops all clocks within the serial module (including the crystal or external clock and SCLK), except for the clock from the IMB. The clock from the IMB remains active to allow CPU32 access to the MCR. The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to serial module registers while in stop mode produce a bus error. The serial module should be disabled in a known state prior to setting the STP bit; otherwise, unpredictable results may occur. The STP bit should be set prior to executing the LPSTOP instruction to reduce overall power consumption. 0 = The serial module is enabled and will operate in normal mode. When STP = 0, make sure the external crystal is stable (XTAL_RDY bit (bit 3) of the ISR is zero) before continuing. NOTE The serial module should be disabled (i.e., the STP bit in the MCR is set) before executing the LPSTOP instruction to obtain the lowest power consumption. The X1/X2 oscillator will continue to run during LPSTOP if STP = 0. FRZ1-FRZ0--Freeze These bits determine the action taken when the FREEZE signal is asserted on the IMB when the CPU32 has entered background debug mode. Table 7-6 lists the action taken for each combination of bits. Table 7-6. FRZx Control Bits
FRZ1 0 0 1 1 FRZ0 0 1 0 1 Action Ignore FREEZE Reserved (FREEZE Ignored) Freeze on Character Boundary Freeze on Character Boundary
MOTOROLA
MC68341 USER'S MANUAL
7-31
If FREEZE is asserted, channel A and channel B freeze independently of each other. The transmitter and receiver freeze at character boundaries. The transmitter does not freeze in the send break mode. Communications can be lost if the channel is not programmed to support flow control. See Section 5 CPU32 for more information on FREEZE. ICCS--Input Capture Clock Select 1 = Selects SCLK as the clear-to-send input capture clock for both channels. Clearto-send operation is enabled by setting bit 4 in MR2. The data is captured on the CTS pins on the rising edge of the clock. 0 = The crystal clock is the clear-to-send input capture clock for both channels. Bits 11-8, 6-4--Reserved by Motorola SUPV--Supervisor/User The value of this bit has no affect on registers permanently defined as supervisor only. 1 = The serial module registers, which are defined as supervisor or user, reside in supervisor data space and are only accessible from supervisor programs. 0 = The serial module registers, which are defined as supervisor or user, reside in user data space and are accessible from either supervisor or user programs. IARB3-IARB0--Interrupt Arbitration Bits Each module that generates interrupts has an IARB field. These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level. No two modules can share the same IARB value. The reset value of the IARB field is $0, which prevents this module from arbitrating during the interrupt acknowledge cycle. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority).
7-32
MC68341 USER'S MANUAL
MOTOROLA
7.4.1.11 MODE REGISTER 1 (MR1). MR1 controls some of the serial module configuration. This register can be read or written at any time when the serial module is enabled (i.e., the STP bit in the MCR is cleared). MR1A, MR1B
7 RxRTS RESET: 0 6 R/F 5 ERR 4 PM1 3 PM0 2 PT
$710, $718
1 B/C1 0 B/C0
0
0
0
0
0
0
0
Read/Write
Supervisor/User
RxRTS--Receiver Request-to-Send Control 1 = Upon receipt of a valid start bit, RTS is negated if the channel's FIFO is full. RTS is reasserted when the FIFO has an empty position available. 0 = RTS is asserted by setting bit 1 or 0 in the OP and negated by clearing bit 1 or 0 in the OP. This feature can be used for flow control to prevent overrun in the receiver by using the RTS output to control the CTS input of the transmitting device. If both the receiver and transmitter are programmed for RTS control, RTS control will be disabled for both since this configuration is incorrect. See 7.4.1.12 Mode Register 2 for information on programming the transmitter RTS control. R/F--Receiver-Ready Select 1 = Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel FIFO full status. These ISR bits are set when the receiver FIFO is full and are cleared when a position is available in the FIFO. 0 = Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel receiverready status. These ISR bits are set when a character has been received and are cleared when the CPU32 reads the receive buffer. ERR--Error Mode This bit controls the meaning of the three FIFO status bits (RB, FE, and PE) in the SR for the channel. 1 = Block mode--The values in the channel SR are the accumulation (i.e., the logical OR) of the status for all characters coming to the top of the FIFO since the last reset error status command for the channel was issued. Refer to 7.4.1.3 Command Register (CR) for more information on serial module commands. 0 = Character mode--The values in the channel SR reflect the status of the character at the top of the FIFO. NOTE ERR = 0 must be used to get the correct A/D flag information when in multidrop mode.
MOTOROLA
MC68341 USER'S MANUAL
7-33
PM1-PM0--Parity Mode These bits encode the type of parity used for the channel (see Table 7-2). The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. These bits can alternatively select multidrop mode for the channel. PT--Parity Type This bit selects the parity type if parity is programmed by the parity mode bits, and if multidrop mode is selected, it configures the transmitter for data character transmission or address character transmission. Table 7-7 lists the parity mode and type or the multidrop mode for each combination of the parity mode and the parity type bits. Table 7-7. PMx and PT Control Bits
PM1 0 0 0 0 1 1 1 PM0 0 0 1 1 0 1 1 Parity Mode With Parity With Parity Force Parity Force Parity No Parity Multidrop Mode Multidrop Mode PT 0 1 0 1 X 0 1 Parity Type Even Parity Odd Parity Low Parity High Parity No Parity Data Character Address Character
B/C1-B/C0--Bits per Character These bits select the number of data bits per character to be transmitted. The character length listed in Table 7-8 does not include start, parity, or stop bits. Table 7-8. B/Cx Control Bits
B/C1 0 0 1 1 B/C0 0 1 0 1 Bits/Character Five Bits Six Bits Seven Bits Eight Bits
7-34
MC68341 USER'S MANUAL
MOTOROLA
7.4.1.12 MODE REGISTER 2 (MR2). MR2 controls some of the serial module configuration. This register can be read or written at any time the serial module is enabled (i.e., the STP bit in the MCR is cleared). MR2A, MR2B
7 CM1 RESET: 0 6 CM0 5 TxRTS 4 TxCTS 3 SB3 2 SB2
$720, $721
1 SB1 0 SB0
0
0
0
0
0
0
0
Read/Write
Supervisor/User
CM1, CM0--Channel Mode These bits select a channel mode as listed in Table 7-9. See 7.3.3 Looping Modes for more information on the individual modes. Table 7-9. CMx Control Bits
CM1 0 0 1 1 CM0 0 1 0 1 Mode Normal Automatic Echo Local Loopback Remote Loopback
TxRTS--Transmitter Ready-to-Send This bit controls the negation of the RTSA or RTSB signals. The output is normally asserted by setting OP0 or OP1 in the OPCR and negated by clearing OP0 or OP1 in the OPCR (see 7.4.1.14 Output Port Control Register (OPCR)). 1 = In applications where the transmitter is disabled after transmission is complete, setting this bit causes the particular OP bit to be cleared automatically one bit time after the characters, if any, in the channel transmit shift register and the transmitter holding register are completely transmitted, including the programmed number of stop bits. This feature is used to automatically terminate transmission of a message. If both the receiver and the transmitter in the same channel are programmed for RTS control, RTS control is disabled for both since this is an incorrect configuration. 0 = Clearing this bit has no effect on the transmitter RTS. TxCTS--Transmitter Clear-to-Send 1 = Enables clear-to-send operation. The transmitter checks the state of the CTS input each time it is ready to send a character. If CTS is asserted, the character is transmitted. If CTS is negated, the channel TxDx remains in the high state, and the transmission is delayed until CTS is asserted. Changes in CTS while a character is being transmitted do not affect transmission of that character. If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the transmitter. 0 = The CTS has no effect on the transmitter.
MOTOROLA
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SB3-SB0--Stop-Bit Length Control These bits select the length of the stop bit appended to the transmitted character as listed in Table 7-10. Stop-bit lengths of nine-sixteenth to two bits, in increments of onesixteenth bit, are programmable for character lengths of six, seven, and eight bits. For a character length of five bits, one and one-sixteenth to two bits are programmable in increments of one-sixteenth bit. In all cases, the receiver only checks for a high condition at the center of the first stop-bit position--i.e., one bit time after the last data bit or after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, MR2 bit 3 = 0 selects one stop bit, and MR2 bit 3 = 1 selects two stop bits for transmission. Table 7-10. SBx Control Bits
SB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Length 6-8 Bits 0.563 0.625 0.688 0.750 0.813 0.875 0.938 1.000 1.563 1.625 1.688 1.750 1.813 1.875 1.938 2.000 Length 5 Bits 1.063 1.125 1.188 1.250 1.313 1.375 1.438 1.500 1.563 1.625 1.688 1.750 1.813 1.875 1.938 2.000
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7.4.1.13 OUTPUT PORT DATA REGISTER (OP). The bits in the OP register are set by performing a bit set command (writing to offset $71E) and are cleared by performing a bit reset command (writing to offset $71F). This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). Bit Set OP
7 OP7 RESET: 0 6 OP6 5 OP5 4 OP4 3 OP3 2 OP2 1 OP1
$71E
0 OP0
0
0
0
0
0
0
0
Write Only NOTE
Supervisor/User
OP bits 7, 5, 3, and 2 are not pinned out on the MC68341; thus, changing these bits has no effect. OP6, OP4, OP1, OP0 --Output Port Parallel Outputs The state of these register bits is the complement of the output signal level (e.g., a reset clears these bits (logic 0), while the output signals are asserted (logic 1)) 1 = These bits can be set by writing a one to the bit position(s) at this address. 0 = These bits are not affected by writing a zero to this address. Bit Reset OP
7 OP7 RESET: 0 6 OP6 5 OP5 4 OP4 3 OP3 2 OP2 1 OP1
$71F
0 OP0
0
0
0
0
0
0
0
Write Only NOTE
Supervisor/User
OP bits 7, 5, 3, and 2 are not pinned out on the MC68341; thus, changing these bits has no effect. OP6, OP4, OP1, OP0 --Output Port Parallel Outputs The state of these register bits is the complement of the output signal level (e.g., a reset clears these bits (logic 0), while the output signals are asserted (logic 1)) 1 = These bits can be cleared by writing a one to the bit position(s) at this address. 0 = These bits are not affected by writing a zero to this address.
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7.4.1.14 OUTPUT PORT CONTROL REGISTER (OPCR). The OPCR individually configures four bits of the 7-bit parallel OP for general-purpose use or as an auxiliary function serving the communication channels. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). OPCR
7 6 5 4 3 OP3 2 OP2 1 OP1 RTSB OP7 OP6 OP5 OP4 TRDYB TRDYA RRDYB RRDYA RESET: 0
$71D
0 OP0 RTSA
0
0
0
0
0
0
0
Write Only NOTE
Supervisor/User
OP bits 7, 5, 3, and 2 are not pinned out on the MC68341; thus, changing these bits has no effect. OP6--Output Port 6/TRDYA 1 = The OP6/TRDYA pin functions as the transmitter-ready signal for channel A. The signal reflects the complement of the value of bit 2 of the SRA; thus, TRDYA is a logic zero when the transmitter is ready. 0 = The OP6/TRDYA pin functions as a dedicated output. The signal reflects the complement of the value of bit 6 of the OP. OP4--Output Port 4/RRDYA 1 = The OP4/RRDYA pin functions as the FIFO-full or receiver-ready signal for channel A (depending on the value of bit 6 of MR1A). The signal reflects the complement of the value of ISR bit 1; thus, RRDYA is a logic zero when the receiver is ready. 0 = The OP4/RRDYA pin functions as a dedicated output. The signal reflects the complement of the value of bit 4 of the OP. OP1--Output Port 1/RTSB 1 = The OP1/RTSB pin functions as the ready-to-send signal for channel B. The signal is asserted and negated according to the configuration programmed by RxRTS bit 7 in the MR1B for the receiver and TxRTS bit 5 in the MR2B for the transmitter. 0 = The OP1/RTSB pin functions as a dedicated output. The signal reflects the complement of the value of bit 1 of the OP.
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OP0--Output Port 0/RTSA 1 = The OP0/RTSA pin functions as the ready-to-send signal for channel A. The signal is asserted and negated according to the configuration programmed by RxRTS bit 7 in the MR1A for the receiver and TxRTS bit 5 in the MR2A for the transmitter. 0 = The OP0/RTSA pin functions as a dedicated output. The signal reflects the complement of the value of bit 0 of the OP. 7.4.1.15 RECEIVER BUFFER (RB). The RB contains three receiver holding registers and a serial shift register. The channel's RxDx pin is connected to the serial shift register. The holding registers act as a FIFO. The CPU32 reads from the top of the stack while the receiver shifts and updates from the bottom of the stack when the shift register has been filled (see Figure 7-4). This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared). RBA, RBB
7 RB7 RESET: 0 6 RB6 5 RB5 4 RB4 3 RB3 2 RB2
$713, $71B
1 RB1 0 RB0
0
0
0
0
0
0
0
Read Only
Supervisor/User
RB7-RB0--These bits contain the character in the RB. 7.4.1.16 STATUS REGISTER (SR). The SR indicates the status of the characters in the FIFO and the status of the channel transmitter and receiver. This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared). SRA, SRB
7 RB RESET: 0 6 FE 5 PE 4 OE 3 TxEMP 2 TxRDY
$711, $719
1 FFULL 0 RxRDY
0
0
0
0
0
0
0
Read Only
Supervisor/User
RB--Received Break 1 = An all-zero character of the programmed length has been received without a stop bit. The RB bit is only valid when the RxRDY bit is set. Only a single FIFO position is occupied when a break is received. Further entries to the FIFO are inhibited until the channel RxDx returns to the high state for at least one-half bit time, which is equal to two successive edges of the internal or external 1x clock or 16 successive edges of the external 16x clock. The received break circuit detects breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must persist until the end of the next detected character time. 0 = No break has been received.
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FE--Framing Error 1 = A stop bit was not detected when the corresponding data character in the FIFO was received. The stop-bit check is made in the middle of the first stop-bit position. The bit is valid only when the RxRDY bit is set. 0 = No framing error has occurred. PE--Parity Error 1 = When the with parity or force parity mode is programmed in the MR1, the corresponding character in the FIFO was received with incorrect parity. When the multidrop mode is programmed, this bit stores the received A/D bit. This bit is valid only when the RxRDY bit is set. 0 = No parity error has occurred. OE--Overrun Error 1 = One or more characters in the received data stream have been lost. This bit is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. This bit is cleared by the reset error status command in the CR. 0 = No overrun has occurred. TxEMP--Transmitter Empty 1 = The channel transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty). This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission. 0 = The transmitter buffer is not empty. The transmitter holding register is loaded by the CPU32, or the transmitter is disabled. The transmitter is enabled/disabled by programming the TCx bits in the CR. TxRDY--Transmitter Ready This bit is duplicated in the ISR; bit 0 for channel A and bit 4 for channel B. 1 = The transmitter holding register is empty and ready to be loaded with a character. This bit is set when the character is transferred to the transmitter shift register. This bit is also set when the transmitter is first enabled. Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted and are lost. 0 = The transmitter holding register was loaded by the CPU32, or the transmitter is disabled.
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FFULL--FIFO Full 1 = A character was transferred from the receiver shift register to the receiver FIFO and the transfer caused the FIFO to become full (all three FIFO holding register positions are occupied). 0 = The CPU32 has read the receiver buffer and one or more FIFO positions are available. Note that if there is a character in the receiver shift register because the FIFO is full, this character will be moved into the FIFO when a position is available, and the FIFO will remain full. RxRDY--Receiver Ready 1 = A character has been received and is waiting in the FIFO to be read by the CPU32. This bit is set when a character is transferred from the receiver shift register to the FIFO. 0 = The CPU32 has read the receiver buffer, and no characters remain in the FIFO after this read. 7.4.1.17 TRANSMITTER BUFFER (TB). The TB consists of two registers, the transmitter holding register and the transmitter shift register (see Figure 7-4). The holding register accepts characters from the bus master if the TxRDY bit in the channel's SR is set. A write to the TB clears the TxRDY bit, inhibiting any more characters until the shift register is ready to accept more data. When the shift register is empty, it checks to see if the holding register has a valid character to be sent (TxRDY bit cleared). If there is a valid character, the shift register loads the character and reasserts the TxRDY bit in the channel's SR. Writes to the TB when the channel's SR TxRDY bit is clear and when the transmitter is disabled have no effect on the TB. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). TBA, TBB
7 TB7 RESET: 0 6 TB6 5 TB5 4 TB4 3 TB3 2 TB2
$713, $71B
1 TB1 0 TB0
0
0
0
0
0
0
0
Write Only
Supervisor/User
TB7-TB0--These bits contain the character in the TB.
7.4.2 Programming
The basic interface software flowchart required for operation of the serial module is shown in Figure 7-10. The routines are divided into three categories: * Serial Module Initialization * I/O Driver * Interrupt Handling
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7.4.2.1 SERIAL MODULE INITIALIZATION. The serial module initialization routines consist of SINIT and CHCHK. SINIT is called at system initialization time to check channel A and channel B operation. Before SINIT is called, the calling routine allocates two words on the system stack. Upon return to the calling routine, SINIT passes information on the system stack to reflect the status of the channels. If SINIT finds no errors in either channel A or channel B, the respective receivers and transmitters are enabled. The CHCHK routine performs the actual channel checks as called from the SINIT routine. When called, SINIT places the specified channel in the local loopback mode and checks for the following errors: * Transmitter Never Ready * Receiver Never Ready * Parity Error * Incorrect Character Received 7.4.2.2 I/O DRIVER EXAMPLE. The I/O driver routines consist of INCH, OUTCH, and POUTCH. INCH is the terminal input character routine and gets a character from the channel A receiver and places it in the lower byte of register D0. OUTCH is used to send the character in the lower byte of register D0 to the channel A transmitter. POUTCH sends the character in the lower byte of D0 to the channel B transmitter. 7.4.2.3 INTERRUPT HANDLING. The interrupt handling routine consists of SIRQ, which is executed after the serial module generates an interrupt caused by a channel A changein-break (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor.
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SERIAL MODULE SINIT ENABLA
INITIATE: CHANNEL A CHANNEL B INTERRUPTS CHK1 POINT TO CHANNEL A
ANY ERRORS IN CHANNEL A ? N
Y
ENABLE CHANNEL A'S RECEIVER
CALL CHCHK
ASSERT CHANNEL A REQUEST TO SEND ENABLB
SAVE CHANNEL A STATUS CHK2 POINT TO CHANNEL B ANY ERRORS IN CHANNEL B ? N CALL CHCHK ENABLE CHANNEL B'S TRANSMITTER SINITR SAVE CHANNEL B STATUS RETURN Y
Figure 7-10. Serial Module Programming Flowchart (1 of 5)
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CHCHK CHCHK
PLACE CHANNEL IN LOCAL LOOPBACK MODE
ENABLE CHANNEL'S TRANSMITTER CLEAR CHANNEL STATUS WORD TxCHK N IS TRANSMITTER READY ? SNDCHR N Y WAITED TOO LONG ? Y
SET TRANSMITTERNEVER-READY FLAG
SEND CHARACTER TO TRANSMITTER RxCHK N HAS RECEIVER RECEIVED CHARACTER ? Y N Y
WAITED TOO LONG ?
SET RECEIVERNEVER-READY FLAG
A
B
Figure 7-10. Serial Module Programming Flowchart (2 of 5)
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A FRCHK RSTCHN
B
HAVE FRAMING ERROR ? Y
N
DISABLE CHANNEL'S TRANSMITTER
RESTORE CHANNEL TO ORIGINAL MODE SET FRAMING ERROR FLAG PRCHK RETURN
HAVE PARITY ERROR ? Y SET PARITY ERROR FLAG A CHRCHK GET CHARACTER FROM RECEIVER
N
SAME AS CHARACTER TRANSMITTED ? N SET INCORRECT CHARACTER FLAG
Y
B
Figure 7-10. Serial Module Programming Flowchart (3 of 5)
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SIRQ ABRKI WAS IRQx CAUSED BY BEGINNING OF A BREAK ? Y CLEAR CHANGE-INBREAK STATUS BIT ABRKI1 HAS END-OF-BREAK IRQx ARRIVED YET ? Y CLEAR CHANGE-INBREAK STATUS BIT
INCH
N
DOES CHANNEL A RECEIVER HAVE A CHARACTER ? Y PLACE CHARACTER IN D0
N
RETURN N
REMOVE BREAK CHARACTER FROM RECEIVER FIFO
REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR RTE
Figure 7-10. Serial Module Programming Flowchart (4 of 5)
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OUTCH
POUTCH
IS CHANNEL A TRANSMITTER READY ? Y
N
IS CHANNEL B TRANSMITTER READY ? Y
N
SEND CHARACTER IN D0 TO CHANNEL A TRANSMITTER
SEND CHARACTER IN D0 TO CHANNEL B TRANSMITTER
WAS CHARACTER A CARRIAGE RETURN ? Y OUTCHI
N
WAS CHARACTER A CARRIAGE RETURN ? Y POUTCHI
N
IS CHANNEL A TRANSMITTER READY ? Y
N
IS CHANNEL B TRANSMITTER READY ? Y
N
SEND A LINE FEED CHARACTER TO CHANNEL A TRANSMITTER OUTCHR
SEND A LINE FEED CHARACTER TO CHANNEL B TRANSMITTER POUTCHR
RETURN
RETURN
Figure 7-10. Serial Module Programming Flowchart (5 of 5)
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7.5 SERIAL MODULE INITIALIZATION SEQUENCE
The following paragraphs discuss a suggested method for initializing the serial module.
7.5.1 Serial Module Configuration
If the serial capability of the MC68341 is being used, the following steps are required to properly initialize the serial module. NOTE The serial module registers can only be accessed by byte operations. Command Register (CR) * Reset the receiver and transmitter for each channel. The following steps program both channels: Module Configuration Register (MCR) * Initialize the stop bit (STP) for normal operation. * Select whether to respond to or ignore FREEZE (FRZx bits). * Select the input capture clock (ICCS bit). * Select the access privilege for the supervisor/user registers (SUPV bit). * Select the interrupt arbitration level for the serial module (IARBx bits). Interrupt Vector Register (IVR) * Program the vector number for a serial module interrupt. Interrupt Level Register (ILR) * Program the interrupt priority level for a serial module interrupt. Interrupt Enable Register (IER) * Enable the desired interrupt sources. Auxiliary Control Register (ACR) * Select baud rate set (BRG bit). * Initialize the input enable control (IEC bits). Output Port Control Register (OPCR) * Select the function of the output port pins. Interrupt Status Register (ISR) * The XTAL_RDY bit should be polled until it is cleared to ensure that an unstable crystal input is not applied to the baud rate generator.
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The following steps are channel specific: Clock Select Register (CSR) * Select the receiver and transmitter clock. Mode Register 1 (MR1) * If desired, program operation of receiver ready-to-send (RxRTS bit). * Select receiver-ready or FIFO-full notification (R/F bit). * Select character or block error mode (ERR bit). * Select parity mode and type (PM and PT bits). * Select number of bits per character (B/Cx bits). Mode Register 2 (MR2) * Select the mode of channel operation (CMx bits). * If desired, program operation of transmitter ready-to-send (TxRTS bit). * If desired, program operation of clear-to-send (TxCTS bit). * Select stop-bit length (SBx bits). Command Register (CR) * Enable the receiver and transmitter.
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7.5.2 Serial Module Example Configuration Code
The following code is an example of a configuration sequence for the serial module.
*************************************************************************** * MC68341 basic serial module register initialization example code. * This code is used to initialize the 68341's internal serial module registers, * providing basic functions for operation. * It sets up serial channel A for communication with a 9600 baud terminal. * Note: All serial module registers must be accessed as bytes. *************************************************************************** *************************************************************************** * equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM41 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM41 MBAR address value *************************************************************** * Serial module equates SERIAL EQU $700 Offset from MBAR for serial module regs MCRH EQU $0 serial MCR high byte MCRL EQU $1 serial MCR low byte * Serial register offsets from serial base address MR1A EQU $10 Mode register 1 A MR2A EQU $20 Mode register 2 A SRA EQU $11 Status register A CSRA EQU $11 Clock select reg A CRA EQU $12 Command reg A ACR OPCR OP_BS OP_BR EQU EQU EQU EQU $14 $1D $1E $1F Auxiliary control reg Output port control reg Output port bit set (write 1 to set) Output port bit reset (write 1 to clear)
*************************************************************************** *************************************************************************** * Initialize Serial channel A *************************************************************************** LEA MODBASE+SERIAL,A0 Pointer to serial channel A * * * * Module configuration register: Enable serial module for normal operation, ignore FREEZE, select the crystal clock. Supervisor/user serial registers unrestricted. Interrupt arbitration at priority $02. MOVE.B #$00,MCRH(A0) MOVE.B #$02,MCRL(A0)
* WAIT FOR TRANSMITTER EMPTY (OR TIMEOUT) MOVE.W #$2000,D0 init loop counter XBMTWAIT EQU * BTST #3,SRA(A0) TX empty in status reg? NOP DBNE D0,XBMTWAIT loop until set or timeout
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* NEGATE RTSA SIGNAL OUTPUT MOVE.B #0,OPCR(A0) MOVE.B #$01,OP_BR(A0) * RESET RECEIVER/TRANSMITTER MOVE.B #$20,CRA(A0) MOVE.B #$30,CRA(A0) * SET BAUD RATE SET 2 MOVE.B #$80,ACR(A0) * MODE REGISTER 1 MOVE.B #$93,MR1A(A0) * MODE REGISTER 2 MOVE.B #$07,MR2A(A0)
make OP0-7 general purpose clear RTSA/OP0 output
Issue reset receiver command Issue reset transmitter command
8 bits, no parity, auto RTS control
Normal, 1 stop bit
* SET UP BAUD RATE FOR PORT IN CLOCK SELECT REGISTER MOVE.B #$BB,CSRA(A0) Set 9600 baud for RX and TX * SET RTSA ACTIVE MOVE.B #$01,OP_BS(A0) * ENABLE PORT MOVE.B
set RTSA/OP0 output
#$45,CRA(A0)
Reset error status, enable RX & TX
*************************************************************************** END ***************************************************************************
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SECTION 8 TIMER MODULE
The MC68341 timer module contains a counter/timer as shown in Figure 8-1. The timer interfaces directly to the CPU32 via the intermodule bus (IMB). The timer consists of the following major areas: * A General-Purpose Counter/Timer * Internal Control Logic * Interrupt Control Logic
TIN COUNTER/ TIMER TOUT TGATE
INTERRUPT CONTROL LOGIC
IMB INTERFACE
Figure 8-1. Simplified Block Diagram
8.1 MODULE OVERVIEW
The timer module consists of the following functional features: * Versatile General-Purpose Timer * 8-Bit Prescaler/16-Bit Counter * Programmable Timer Modes: -- Input Capture/Output Compare -- Square-Wave Generation -- Variable Duty-Cycle Square-Wave Generation -- Variable-Width Single-Shot Pulse Generation -- Pulse-Width Measurement
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-- Period Measurement -- Event Counting * Seven Maskable Interrupt Conditions Based on Programmable Events
8.1.1 Timer and Counter Functions
The timer can perform virtually any application traditionally assigned to timers and counters. The timer can be used to generate timed events that are independent of the timing errors to which real-time programmed microprocessors are susceptible--for example, those of dynamic memory refreshing, DMA cycle steals, and interrupt servicing. The timer has several functional areas: an 8-bit countdown prescaler, a 16-bit down counter, time-out logic, compare logic, and clock selection logic. Figure 8-2 shows a functional diagram of the timer module. 8.1.1.1 PRESCALER AND COUNTER. The counter can be driven directly by the selected clock or the prescaler output. Both the counter and prescaler are updated on the falling edge of the clock. During reset, the prescaler is set to $FF, and the counter is set to $0000. The counter is loaded with a programmed value on the first falling edge of the counter clock after the timer is enabled and again when a time-out occurs (counter reaches $0000). The prescaler and counter can be used as one 24-bit counter by enabling the prescaler and selecting the divide-by-256 prescaler output. Refer to 8.4 Register Description for additional information on how to program the timer. 8.1.1.2 TIME-OUT DETECTION. Time-out is achieved when all 16 stages of the counter transition to zero, a counter value of $0000. Time-out is a defined counter event which triggers specific actions depending upon the programmed mode of operation. Refer to 8.3 Operating Modes for descriptions of the individual modes. 8.1.1.3 COMPARATOR. The comparator block compares the value in the 16-bit compare register (COM) with the output of the 16-bit counter. When an exact match is detected, bits in the status register (SR) are set to indicate this condition. When in the input capture/output compare mode, a match is a defined counter event that can affect the output of the timer (TOUT). Refer to 8.3.1 Input Capture/Output Compare for additional information on this mode.
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TIMER
EXTERNAL INTERFACE MODULE CONFIGURATION REGISTER
INTERRUPT REGISTER
CONTROL REGISTER
STATUS REGISTER
PRELOAD 1 REGISTER
I M B
CLOCK
(SYSTEM CLOCK) PRELOAD 2 REGISTER
CLOCK LOGIC SELECTED CLOCK
TIN TGATE
MUX
16-BIT COUNTER
COUNTER CLOCK
MUX 8-BIT PRESCALER
COUNTER REGISTER
TIMEOUT
TOUT
COMPARE REGISTER
16-BIT COMPARATOR
Figure 8-2. Timer Functional Diagram 8.1.1.4 CLOCK SELECTION LOGIC. The clock selection logic consists of two multiplexers that select the clocks applied to the prescaler and counter. The first multiplexer (labeled clock logic in Figure 8-2) selects between the clock input to the timer (TIN) or one-half the frequency of the system clock (CLKOUT). This output of the first multiplexer (called selected clock) is applied to both the 8-bit prescaler and the second multiplexer. The second multiplexer selects the clock for the 16-bit counter, which is either the selected clock or the 8-bit prescaler output.
8.1.2 Internal Control Logic
The timer receives operation commands on the IMB and, in turn, issues appropriate operation signals to the internal timer control logic. This mechanism allows the timer registers to be accessed and programmed. Refer to 8.4 Register Description for additional information.
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8.1.3 Interrupt Control Logic
The timer provides seven interrupt request outputs (IRQ7 -IRQ1 ) to notify the CPU32 that an interrupt has occurred. The interrupts are described in 8.4 Register Description. Bits in the SR indicate all currently active interrupt conditions. The interrupt enable (IE) bits in the control register (CR) are programmable to mask any events that may cause an interrupt.
8.2 TIMER MODULES SIGNAL DEFINITIONS
This section contains a brief description of the timer module signals (see Figure 8-3). NOTE The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false.
TIN CLOCK LOGIC TGATE
PRESCALER EXTERNAL INTERFACE SIGNALS COUNTER
I M B
OUTPUT CONTROL
TOUT
INTERRUPT CONTROL
Figure 8-3. External and Internal Interface Signals
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8.2.1 Timer Input (TIN)
This input can be programmed to be the clock that causes events to occur in the counter and prescaler. TIN is internally synchronized to the system clock to guarantee that a valid TIN level is recognized. Additionally, the high and low levels of TIN must each be stable for at least one system clock period plus the sum of the setup and hold times for TIN. Refer to Section 12 Electrical Characteristics, for additional information.
8.2.2 Timer Gate (TGATE )
This active-low input can be programmed to enable and disable the counter and prescaler. TGATE may also be programmed to be a simple input. For more information on the modes of operation, refer to 8.3 OPERATING MODES. To guarantee that the timer recognizes a valid level on TGATE, the signal is synchronized with the system clock. Additionally, the high and low levels of this input must each be stable for at least one system clock period plus the sum of the setup and hold times for TGATE. Refer to Section 12 Electrical Characteristics, for additional information.
8.2.3 Timer Output (TOUT)
This output drives the various output waveforms generated by the timer. The initial level and transitions can be programmed by the output control (OC) bits in the CR.
8.3 OPERATING MODES
The following paragraphs contain a detailed description of each timer operation mode and of the IMB operation during accesses to the timer. Changing the contents of the CR should only be attempted when the timer is disabled (the software reset (SWR) bit in the CR is cleared). Changing the CR while the timer is running may produce unpredictable results.
8.3.1 Input Capture/Output Compare
This mode has the capability of capturing a counter value by holding the value in the counter register (CNTR). Additionally, this mode can provide compare information via TOUT to indicate when the counter has reached the compare value. This mode can be used for square-wave generation, pulse-width modulation, or periodic interrupt generation. This mode can be selected by programming the operation mode bits (MODEx) in the CR to 000. The timer is enabled when the counter prescaler enable (CPE) and SWRx bits in the CR are set. Once enabled, the counter enable (ON) bit in the SR is set, and the next falling edge of the counter clock causes the counter to be loaded with the value in the preload 1 register (PREL1). The TGATE signal functions differently in this mode than it does in the other modes. TGATE does not enable or disable the counter/prescaler input clock; instead, it is used to disable shadowing. Normally, the counter is decremented on the falling edge of the counter clock, and the CNTR is updated on the next rising edge of the system clock; thus,
MOTOROLA MC68341 USER'S MANUAL 8-5
the CNTR shadows the actual value of the counter. The timer gate interrupt (TG) bit in the SR must be cleared for shadowing to occur. TGATE is used to set the TG bit and disable shadowing. If the timing gate is enabled (TGE bit of the CR is set), the TG bit is set by the rising edge of TGATE. Shadowing is disabled until the TG bit is cleared by writing a one to its location in the SR. See Figure 8-4 for a depiction of this mode. If the timing gate is disabled (CR TGE bit is cleared), TGATE has no effect on the operation of the timer; thus the input capture function is inoperative. At all times, the TGATE level bit (TGL) in the SR reflects the level of the TGATE signal.
COUNTER CLOCK COUNTER COUNTER REGISTER TGATE TG SET TOUT ENABLE TC SET TIMEOUT TC SET TG CLEARED TG SET 0 0 0 0 0 0 8 0 8 8 7 8 7 7 6 7 6 6 5 6 5 6 4 6 4 6 3 6 3 6 2 3 2 2 1 2 1 1 0 1 0 0 8 0 8 8 7 8 7 8
Modex Bits in Control Register = 000 Preload 1 Register = 8 Compare Register = 7 TGE Bit of Status Register = 1 TG Bit in Status Register Initially = 0 OCx Bits in Control Register = 10
Figure 8-4. Input Capture/Output Compare Mode Since the counter is not affected by TGATE, it continues to decrement on the falling edge of the counter clock and load from the PREL1 at time-out, regardless of the value of TGATE. When the counter counts down to the value contained in the COM, this condition is reflected by setting the timer compare (TC) and compare (COM) bits in the SR. TOUT responds as selected by the OCx bits in the CR. The output level (OUT) bit in the SR reflects the value on TOUT. Shadowing does not affect this operation. If the counter counts down to $0000, a time-out is detected, causing the SR time-out interrupt (TO) bit to be set and the SR COM bit to be cleared. On the next falling edge of the counter clock after the time-out is detected, the value in PREL1 is again loaded into the counter. TOUT responds as selected by the CR OCx bits. A square-wave generator can be implemented by programming the CR OCx bits to toggle mode. The value in the COM should be one-half the value in PREL1 to cause an event to happen twice in the countdown.
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This mode can be used as a pulse-width modulator by programming the CR OCx bits to zero mode or one mode. The value in the PREL1 specifies the frequency, and the COM determines the pulse width. The pulse widths can be changed by writing a new value to the COM. Periodic interrupt generation can be accomplished by enabling the TO, TG, and/or TC bits in the SR to generate interrupts by programming the IE bits of the CR. When enabled, the programmed IRQ signal is asserted whenever the specified bits are set. TOUT signal transitions can be controlled by writing new values into the COM. Caution must be exercised when accessing the COM. If it were to be accessed simultaneously by the compare logic and by a write, the old compare value may actually get compared to the counter value.
8.3.2 Square-Wave Generator
This mode can be used for generating both square-wave output and periodic interrupts. The square wave is generated by counting down from the value in the PREL1 to time-out (counter value of $0000). TOUT changes state on each time-out as programmed. This mode can be selected by programming the CR MODEx bits to 001. The timer is enabled by setting the SWR and CPE bits in the CR and, if TGATE is programmed to control the enabling and disabling of the counter (TGE bit set in the CR), then asserting TGATE. When the timer is enabled, the ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL1 (N). With each successive falling edge of the counter clock, the counter decrements. The time between enabling the timer and the first time-out can range from N to N + 1 periods. When TGATE is used to enable the timer, the enabling of the timer is asynchronous; however, if timing is carefully considered, the time to the first time-out can be known. For additional details on timing, see Section 12 Electrical Characteristics. TOUT behaves as a square wave when the OCx bits of the CR are programmed for toggle mode. A time-out occurs every N + 1 periods (allowing for the zero cycle), resulting in a change of state on TOUT (see Figure 8-5). The SR OUT bit reflects the level of TOUT. If this mode is used to generate periodic interrupts, TOUT may be enabled if a square wave is also desired.
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COUNTER CLOCK COUNTER TOUT 0 0 3 N: N + 1 ENABLE MODEx Bits in Control Register = 001 Preload 1 Register = N = 3 OCx Bits in Control Register = 01 TIMEOUT TIMEOUT 2 1 0 3 2 N+1 1 0 3 2 N+1 TIMEOUT 1 0 3
Figure 8-5. Square-Wave Generator Mode If TGATE is negated when it is enabled to control the timer (TGE = 1), the prescaler and counter are disabled. Additionally, the SR TG bit is set, indicating that TGATE was negated. The SR ON bit is cleared, indicating that the timer is disabled. If TGATE is reasserted, the timer is re-enabled and begins counting from the value attained when TGATE was negated. The SR ON bit is set again. If TGATE is disabled (TGE = 0), TGATE has no effect on the operation of the timer. In this case, the counter begins counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. The TG bit of the SR cannot be set. At all times, TGL in the SR reflects the level of TGATE. If the counter counts down to the value stored in the COM register, then the COM and TC bits in the SR are set. The counter continues counting down to time-out. At this time, the SR TO bit is set, and the SR COM bit is cleared. The next falling edge of the counter clock after time-out causes the value in PREL1 to be loaded back into the counter, and the counter begins counting down from this value. The period of the square-wave generator can be changed dynamically by writing a new value into the PREL1. Caution must be used because, if PREL1 is accessed simultaneously by the counting logic and a CPU32 write, the old PREL1 value may actually get loaded into the counter at time-out. Periodic interrupt generation can be accomplished by enabling the TO, TG, and/or TC bits in the SR to generate interrupts by programming the CR IE bits. When enabled, the programmed IRQ signal is asserted whenever the specified bits are set.
8.3.3 Variable Duty-Cycle Square-Wave Generator
In this mode, both the PREL1 and PREL2 registers are used to generate a square wave with virtually any duty cycle. The square wave is generated by counting down from the value in the PREL1 to time-out (count value $0000), then loading that value from PREL2 and again counting down to time-out. When this second time-out occurs, the value from PREL1 is loaded into the counter, and the cycle repeats. TOUT can be programmed to change state with every time-out, thus generating a variable duty-cycle square wave. This mode can be selected by programming the MODE bits in the CR to 010.
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The timer is enabled by setting both the SWR and CPE bits in the CR and, if TGATE is enabled (CR TGE bit is set), then asserting TGATE . When the timer is enabled, the ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL1 register (N1). With each successive falling edge of the counter clock, the counter decrements. The time between enabling the timer and the first time-out can range from N1 to N1+1 periods. When TGATE is used to enable the timer, the enabling of the timer is asynchronous; however, if timing is carefully considered, the time to the first time-out can be known. For additional details on timing, see the Section 12 Electrical Characteristics. If the counter counts down to the value stored in the COM register, the COM and timer compare interrupt (TC) bits in the SR are set. The counter continues counting down to time-out. At this time, the TO bit in the SR is set, and the COM bit is cleared. The next falling edge of the counter clock after time-out causes the value in PREL2 (N2) to be loaded into the counter, and the counter begins counting down from this value. Each successive time-out causes the counter to be loaded alternately with the values from PREL1 and PREL2. TOUT behaves as a variable duty-cycle square wave when the CR OC bits are programmed for toggle mode. The second time-out occurs after N2 + 1 periods (allowing for the zero cycle), resulting in a change of state on TOUT. The third time-out occurs after N1 + 1 periods, resulting in a change of state on TOUT, and so on (see Figure 8-6). The OUT bit in the SR reflects the level of TOUT.
COUNTER CLOCK COUNTER TOUT 0 0 4 3 2 1 0 2 N2 + 1 TIMEOUT TIMEOUT 1 0 4 3 2 N1 + 1 TIMEOUT 1 0 2 N2 + 1 TIMEOUT 1 0
N1: N1 + 1 ENABLE
MODEx Bits in Control Register = 010 Preload 1 Register = N1 = 4 Preload 2 Register = N2 = 2 OCx Bits in Control Register = 01
Figure 8-6. Variable Duty-Cycle Square-Wave Generator Mode If TGATE is negated when it is enabled (TGE = 1), the prescaler and counter are disabled. Additionally, the TG bit of the SR is set, indicating that TGATE was negated. The ON bit of the SR is cleared, indicating that the timer is disabled. If TGATE is reasserted, the timer is re-enabled and begins counting from the value attained when TGATE was negated. The ON bit is set again. If TGATE is not enabled (TGE = 0), TGATE has no effect on the operation of the timer. In this case, the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. The SR TG bit cannot be set. At all times, the TGL bit in the SR reflects the level of TGATE.
MOTOROLA MC68341 USER'S MANUAL 8-9
The duty cycle of the waveform generated on TOUT can be dynamically changed by writing new values into PREL1 and/or PREL2. If PREL1 or PREL2 is being accessed simultaneously by the counter logic and a CPU32 write, the old preload value may actually get loaded into the counter at time-out. If at time-out, the counting logic was accessing PREL2 and the CPU32 was writing to PREL1 (or vice versa), there would be no unexpected results.
8.3.4 Variable-Width Single-Shot Pulse Generator
This mode is used to produce a one-time pulse that has a delay controlled by the value stored in PREL1 and a duration controlled by the value stored in PREL2. With TOUT programmed to change state, this sequence creates a single pulse of variable width. This mode can be selected by programming the CR MODE bits to 011. The timer is enabled by setting both the SWR and CPE bits in the CR and, if TGATE is enabled (TGE bit in the CR is set), then asserting TGATE. When the timer is enabled, the ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL1 register (N1). With each successive falling edge of the counter clock, the counter decrements. The time between enabling the timer and the first time-out can range from N1 to N1 + 1 periods. When TGATE is used to enable the counter, the enabling of the timer is asynchronous; however, if timing is carefully considered, the time to the first time-out can be known. For additional details on timing, see Section 12 Electrical Characteristics. If the counter counts down to the value stored in the COM, the COM and TC bits in the SR are set. The counter continues counting down to time-out. At this time, the SR TO bit is set and the SR COM bit is cleared. The next falling edge of the counter clock after time-out causes the value in PREL2 (N2) to be loaded into the counter, and the counter begins counting down from this value. After the second time-out, the selected clock is held high, disabling the prescaler and counter. Additionally, the SR ON and COM bits are cleared. TOUT behaves as a variable-width pulse when the OCx bits of the CR are programmed for toggle mode. TOUT is a logic zero between the time that the timer is enabled and the first time-out. When this event occurs, TOUT transitions to a logic one. The second timeout occurs after N2 + 1 periods (allowing for the zero cycle), resulting in TOUT returning to a logic zero (see Figure 8-7). The OUT bit in the SR reflects the level of TOUT.
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COUNTER CLOCK COUNTER 0 TOUT ENABLE 0 2 N1: N1 + 1 TIMEOUT 1 0 5 4 3 N2 + 1 TIMEOUT 2 1 0
MODEx Bits in Control Register = 011 Preload 1 Register = N1 = 2 Preload 2 Register = N2 = 5 OCx bits in Control Register = 01
Figure 8-7. Variable-Width Single-Shot Pulse Generator Mode If TGATE is negated when it is enabled (TGE = 1), the prescaler and counter are disabled. Additionally, the SR TG bit is set, indicating that TGATE was negated. The SR ON bit is cleared, indicating that the timer is disabled. If TGATE is reasserted, the timer is re enabled and begins counting from the value attained when TGATE was negated. The ON bit is set again. If TGATE is not enabled (TGE = 0), TGATE has no effect on the operation of the timer. In this case, the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. The SR TG bit cannot be set. At all times, the TGL bit in the SR reflects the level of TGATE. The width of the pulse generated on TOUT (the value in PREL2) can be changed while the counter is counting down from the value in PREL1. Caution must be used because, if PREL2 is accessed simultaneously by the counting logic and a CPU32 write, the old PREL2 value may actually get loaded into the counter at time-out.
8.3.5 Pulse-Width Measurement
This mode is used to count the clock cycles during a particular event (see Figure 8-8). The event is defined by the assertion and negation of TGATE . When TGATE is asserted, the counter begins counting down from $FFFF. When TGATE is negated, the counter stops counting and holds the value at which it stopped. Further assertions and negations of TGATE have no effect on the counter. This mode can be selected by programming the CR MODEx bits to 100. The timer is enabled by setting the SWR, CPE, and TGE bits in the CR. Asserting TGATE starts the counter. When the timer is enabled, the SR ON bit is set. On the next falling edge of the counter clock, the counter is loaded with the value $FFFF. With each successive falling edge of the counter clock, the counter decrements. The PREL1 and PREL2 registers are not used in this mode. When TGATE is negated, the SR TG bit is set, the ON bit is negated, and the prescaler and counter are disabled. Subsequent transitions on TGATE do not re-enable the counter. The TGL bit in the SR reflects the level of TGATE at all times.
MOTOROLA MC68341 USER'S MANUAL 8-11
COUNTER CLOCK COUNTER
0
f f f f
f f f e
f f f d
f f f c
f f f b
f f f b
TGATE ENABLE START COUNTING
MEASURED PULSE
STOP COUNTING
NO EFFECT
MODEx Bits in Control Register = 100 TGE Bit of Control Register = 1
Figure 8-8. Pulse-Width Measurement Mode If the counter counts down to the value stored in the COM register, the COM and TC bits in the SR are set. If the counter counts down to $0000, a time-out is detected. This sets the SR TO, and the clears the COM bit. At time-out, the next falling edge of the counter clock causes the counter to reload with $FFFF. TOUT transitions at time-out or is disabled as programmed by the CR OCx bits. The SR OUT bit reflects the level on TOUT. To determine the number of cycles counted, the value in the CNTR must be read, inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count of zero). The counter counts in a true 216 fashion. For measuring pulses of even greater duration, the value in the POx bits in the SR is readable and can be thought of as an extension of the least significant bits in the CNTR. NOTE Once the timer has been enabled, do not clear the SR TG bit until the pulse has been measured and TGATE has been negated.
8.3.6 Period Measurement
This mode is used to count the period of a particular event. The event is defined by the assertion, negation, and subsequent reassertion of TGATE . When TGATE is asserted, the counter begins counting down from $FFFF. The negation of TGATE has no effect on the counter. When TGATE is reasserted, the counter stops counting and holds the value at which it stopped. Further assertions and negations of TGATE have no effect on the counter. This mode can be selected by programming the CR MODEx bits to 101. The timer is enabled by setting the SWR, CPE, and the TGE bits in the CR. The assertion of TGATE starts the counter. When the timer is enabled, the SR ON bit is set. On the next falling edge of the counter clock, the counter is loaded with the value of $FFFF. With each successive falling edge of the counter clock, the counter decrements. The PREL1 and PREL2 registers are not used in this mode.
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The first negation of TGATE is ignored, but on the second assertion of TGATE, the SR TG bit is set, the SR ON bit is negated, and the prescaler and counter are disabled. Subsequent transitions on TGATE do not re-enable the counter. See Figure 8-9 for a depiction of this mode. The SR TGL bit reflects the level of TGATE at all times.
COUNTER CLOCK COUNTER
0
f f f f
f f f e
f f f d
f f f c
f f f b
f f f a
f f f 9
f f f 9
TGATE ENABLE START COUNTING MODEx Bits in Control Register = 101 TGE Bit of Control Register = 1 PERIOD MEASURED STOP COUNTING NO EFFECT
Figure 8-9. Period Measurement Mode If the counter counts down to the value stored in the COM register, the COM and TC bits in the SR are set. If the counter counts down to $0000, a time-out is detected. This sets the SR TO bit, and clears the SR COM bit. At time-out, the next falling edge of the counter clock reloads the counter with $FFFF. TOUT transitions at time-out or is disabled as programmed by the OCx bits of the CR, and the OUT bit in the SR reflects the level on TOUT. To determine the number of cycles counted, the value in the CNTR must be read, inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count of zero). The counter counts in a true 216 fashion. For measuring pulses of even greater duration, the value in the POx bits in the SR are readable and can be thought of as an extension of the least significant bits in the CNTR. NOTE Once the timer has been enabled, do not clear the SR TG bit until the pulse has been measured and TGATE has been negated.
8.3.7 Event Count
This mode is used to count events by interpreting the falling edges of the counter clock as events (see Figure 8-10). These events may be external or internal to the chip--for example, counting the number of system clock cycles required to execute a sequence of instructions. As another example, by connecting AS to TIN, the number of bus cycles to complete a sequence of instructions could be counted. This mode can be selected by programming the CR MODEx bits to 110.
MOTOROLA MC68341 USER'S MANUAL 8-13
COUNTER CLOCK COUNTER
0
f f f f
f f f e
f f f d
f f f c
f f f b
0 0 0 2
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
f f f f
f f f e
TGATE ENABLE MODEx Bits in Control Register = 110 TGE Bit of the Control Register = 1 TG BIT SET TIMEOUT TO BIT SET
Figure 8-10. Event Count Mode The timer is enabled by setting the SWR and CPE bits in the CR and, if TGATE is enabled (TGE bit of the CR is set), then asserting TGATE . When the timer is enabled, the SR ON bit is set. On the next falling edge of the counter clock, the counter is loaded with the value of $FFFF. With each successive falling edge of the counter clock, the counter decrements. The PREL1 and PREL2 registers are not used in this mode. If TGATE is not enabled (CR TGE bit is cleared), then TGATE does not start or stop the timer or affect the TG bit of the SR. In this case, the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. If TGATE is enabled (CR TGE bit is set), then the assertion of TGATE starts the counter. The negation of TGATE disables the counter, sets the SR TG bit, and clears the ON bit in the SR. If TGATE is reasserted, the timer resumes counting from where it was stopped, and the ON bit is set again. Further assertions and negations of TGATE have the same effect. The TGL bit in the SR reflects the level of TGATE at all times. If the counter counts down to the value stored in the COM register, the COM and TC bits in the SR are set. If the counter counts down to $0000, a time-out is detected. This event sets the TO in the SR and clears the COM bit. At time-out, the next falling edge of the counter clock reloads the counter with $FFFF. TOUT transitions at time-out or is disabled as programmed by the CR OC bits. The SR OUT bit reflects the level on TOUT. To determine the number of cycles counted, the value in the CNTR must be read, inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count of zero). The counter counts in a true 216 fashion. For measuring pulses of even greater duration, the value in the POx bits in the SR are readable and can be thought of as an extension of the least significant bits in the CNTR.
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8.3.8 Timer Bypass
In this mode, the counter and prescaler cannot be enabled. However TGATE and TOUT can be used for I/O. This mode can be selected by programming the CR MODE bits to 111. TGATE can be used as a simple input port when the CR is configured as follows: CR
15 SWR 14 IE2 13 IE1 12 IE0 11 TGE 10 PCLK 9 CPE 8 CLK 7 POT2 6 POT1 5 POT0 4 3 2 1 OC1 0 OC0 MODE2 MODE1 MODE0
TGATE AS A SIMPLE INPUT
X X 0 X X X 1 X X X X 1 1 1 X X
X-Don't care When TGATE is asserted, the SR ON bit is set. When TGATE is negated, the ON bit is cleared. The value of the TGL bit in the SR reflects the level of TGATE . TGATE can also be used as an input port that generates interrupts on a low-to-high transition of TGATE when the CR is configured as follows: CR
15 SWR 14 IE2 13 IE1 12 IE0 11 TGE 10 PCLK 9 CPE 8 CLK 7 POT2 6 POT1 5 POT0 4 3 2 1 OC1 0 OC0 MODE2 MODE1 MODE0
TGATE AS AN INPUT/INTERRUPT
X X 1 X 1 X 1 X X X X 1 1 1 X X
When TGATE is negated, the SR TG bit is set, and the programmed IRQx signal is asserted to the CPU32. The TG bit can only be cleared by writing a one to this bit position. The value of the SR TGL bit reflects the level of TGATE . Additionally, TOUT can be used as a simple output port when the CR is configured as follows: CR
15 SWR 14 IE2 13 IE1 12 IE0 11 TGE 10 PCLK 9 CPE 8 CLK 7 POT2 6 POT1 5 POT0 4 3 2 1 OC1 0 OC0 MODE2 MODE1 MODE0
TGATE AS A SIMPLE OUTPUT
0 X X X X X 1 X X X X 1 1 1 OC1 OC0
SWR must be a zero to change the value of TOUT. Changing the value of the CR OCx bits determines the level of TOUT as shown in Table 8-1.
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Table 8-1. OCx Encoding
OC1 0 0 1 1 OC0 0 1 0 1 TOUT Hi-Z 0 0 1
A read of the SR while in this mode always shows the TO, TC, and COM bits cleared, and the PO bits as $FF. The SR OUT bit always indicates the level on the TOUT pin.
8.3.9 Bus Operation
The following paragraphs describe the operation of the IMB during read, write, and interrupt acknowledge cycles to the timer. 8.3.9.1 READ CYCLES. The timer is accessed with no wait states. The timer responds to byte, word, and long-word reads, and 16 bits of valid data are returned. Read cycles from reserved registers return logic zero. 8.3.9.2 WRITE CYCLES. The timer is accessed with no wait states. The timer responds to byte, word, and long-word writes. Write cycles to read-only registers and bits as well as reserved registers complete in a normal manner without exception processing; however, the data is ignored. 8.3.9.3 INTERRUPT ACKNOWLEDGE CYCLES. The timer is capable of arbitrating for interrupt servicing and supplying the interrupt vector when it has successfully won arbitration. The vector number must be provided if interrupt servicing is necessary; thus, the interrupt register (IR) must be initialized. If the IR is not initialized, a spurious interrupt exception will be taken if interrupt servicing is necessary.
8.4 REGISTER DESCRIPTION
The following paragraphs contain a detailed description of each register and its specific function. The operation of the timer is controlled by writing control words into the appropriate registers. Timer registers and their associated addresses are listed in Figure 8-11. For more information about a particular register, refer to the individual register description. The ADDR column indicates the offset of the register from the base address of the timer. An FC column designation of S indicates that register access is restricted to supervisor only. A designation of S/U indicates that access is governed by the SUPV bit in the module configuration register (MCR).
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ADDR $600 $602 $604 $606 $608 $60A $60C $60E $610 $612-$63F
FC S S S S/U S/U S/U S/U S/U S/U S/U
15
0
MODULE CONFIGURATION REGISTER (MCR) RESERVED INTERRUPT REGISTER (IR) CONTROL REGISTER (CR) STATUS/PRESCALER REGISTER (SR) COUNTER REGISTER (CNTR) PRELOAD 1 REGISTER (PREL1) PRELOAD 2 REGISTER (PREL2) COMPARE REGISTER (COM) RESERVED
Figure 8-11. Timer Module Programming Model In the registers discussed in the following paragraphs, the numbers in the upper righthand corner indicate the offset of the register from the base address specified by the module base address register (MBAR) in the SIM40. The numbers on the top line of the register represent the bit position in the register. The register contains the mnemonic for the bit. The value of these bits after a hardware reset is shown below the register. The access privilege is shown in the lower right-hand corner. NOTE A CPU32 RESET instruction will not affect the MCR, but will reset all other registers in the timer modules as though a hardware reset occurred.
8.4.1 Module Configuration Register (MCR)
The MCR controls the timer module configuration. This register can be either read or written when the module is enabled and is in the supervisor state. The MCR is not affected by a CPU32 RESET instruction. MCR
15 STP RESET: 0 14 FRZ1 13 FRZ0 12 0 11 0 10 0 9 0 8 0 7 SUPV 6 0 5 0 4 0 3 IARB3 2 IARB2 1 IARB1
$600
0 IARB0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Supervisor Only
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STP--Stop bit 1 = Setting the STP bit stops all clocks within the timer module except for the clock from the IMB. The clock from the IMB remains active to allow the CPU32 access to the MCR. The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to timer module registers while in stop mode produce a bus error. The timer module should be disabled in a known state prior to setting the STP bit; otherwise, unpredictable results may occur. The STP bit should be set prior to executing the LPSTOP instruction to reduce overall power consumption. 0 = The timer operates in normal mode. FRZ1, FRZ0--Freeze These bits determine the action taken when the FREEZE signal is asserted on the IMB, when the CPU32 has entered background debug mode. Table 8-2 lists the action taken for each bit combination. Table 8-2. FRZx Control Bits
FRZ1 0 0 1 1 FRZ0 0 1 0 1 ACTION Ignore FREEZE Reserved (FREEZE ignored) Execution Freeze Execution Freeze
Bits 12-8, 6-4--Reserved SUPV--Supervisor/User The value of this bit has no effect on registers permanently defined as supervisor-only access. 1 = The timer registers defined as supervisor/user reside in supervisor data space and are only accessible from supervisor programs. 0 = The timer registers defined as supervisor/user reside in user data space and are accessible from either supervisor or user programs. IARB3-IARB0--Interrupt Arbitration Bits Each module that generates interrupts has an IARB field. These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level. No two modules can share the same IARB value. The reset value of the IARB field is $0, which prevents this module from arbitrating during the interrupt acknowledge cycle. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority).
8.4.2 Interrupt Register (IR)
The IR contains the priority level for the timer interrupt request and the 8-bit vector number of the interrupt. The register can be read or written to at any time while in supervisor mode and while the timer module is enabled (i.e., the STP bit in the MCR is cleared).
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IR
15 0 RESET: 0 14 0 13 0 12 0 11 0 10 IL2 9 IL1 8 IL0 7 IVR7 6 IVR6 5 IVR5 4 IVR4 3 IVR3 2 IVR2 1 IVR1
$604
0 IVR0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Supervisor Only Bits 15-11--Reserved IL2-IL0--Interrupt Level Bits Each module that can generate interrupts has an interrupt level field. The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQ signal. The CPU32 uses this value to determine servicing priority. See Section 5 CPU32 for more information. IV7-IV0--Interrupt Vector Bits Each module that can generate interrupts has an interrupt vector (IV) field. This 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. The IV field is reset to $0F, which indicates an uninitialized interrupt condition. See Section 5 CPU32 for more information.
8.4.3 Control Register (CR)
The CR controls the operation of the timer. The register can always be read or written when the timer module is enabled (i.e., the STP bit in the MCR is cleared). Changing the contents of the CR should only be attempted when the timer is disabled (the SWR bit in the CR is cleared). Changing the CR while the timer is running may produce unpredictable results. CR
15 SWR RESET: 0 14 IE2 13 IE1 12 IE0 11 TGE 10 PCLK 9 CPE 8 CLK 7 POT2 6 POT1 5 POT0 4 3 2 1 OC1 MODE2 MODE1 MODE0
$606
0 OC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Supervisor/User SWR--Software Reset 1 = Removes the software reset. 0 = A software reset is performed by first clearing this bit and then clearing the TO, TG, and TC bits in the SR. The prescaler is loaded with $FF, the counter is set to $0000, and the SR COM bit is cleared. When this bit is zero, the timer is disabled. IE2-IE0--Interrupt Enable These bits determine which sources of interrupts, TO, TG, and TC, are enabled to generate an interrupt request to the CPU32. Table 8-3 lists which interrupts are enabled for all bit combinations.
MOTOROLA MC68341 USER'S MANUAL 8-19
Table 8-3. IEx Encoding
IE2 0 0 0 0 1 1 1 1 IE1 0 0 1 1 0 0 1 1 IE0 0 1 0 1 0 1 0 1 Enabled Interrupts Polling Mode (No Interrupts Enabled) TC Enabled TG Enabled TG and TC Enabled TO Enabled TO and TC Enabled TO and TG Enabled TO, TG, and TC Enabled
TGE--Timing Gate Enable 1 = The TGATE signal is enabled to control the enabling and disabling of the prescaler and counter, except in the input capture/output compare mode (see 8.3.1 Input Capture/Output Compare). 0 = The TGATE signal has no effect on the timer operation. PCLK--Prescaler Clock Select This bit selects which clock is used for the counter clock. 1 = The counter is decremented by the prescaler output tap as selected by the POT field in the CR. 0 = The counter is decremented by the selected clock. The prescaler continues to decrement regardless of how PCLK is set. CPE--Counter Prescaler Enable 1 = The selected clock is enabled. If the TGE bit is set, then TGATE must also be asserted (except in the input capture/output compare mode). 0 = The selected clock is held high, halting the prescaler and counter. CLK--Clock 1 = The selected clock is taken from the TIN input. 0 = The selected clock is one-half the system clock's frequency.
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POT2-POT0--Prescaler Output Tap If PCLK is set, these bits encode which of the prescaler's output taps act as the counter clock. A division of the selected clock is applied to the counter as listed in Table 8-4. Table 8-4. POT Encoding
POT2 0 0 0 1 1 1 1 0 POT1 0 1 1 0 0 1 1 0 POT0 1 0 1 0 1 0 1 0 Division of Selected Clock Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Divide by 128 Divide by 256
MODE2-MODE0--Operation Mode These bits select one of the eight modes of operation for the timer as listed in Table 8-5. Refer to 8.3 Operating Modes for more information on the individual modes. Table 8-5. MODEx Encoding
MODE2 0 0 0 0 1 1 1 1 MODE1 0 0 1 1 0 0 1 1 MODE0 0 1 0 1 0 1 0 1 OPERATION MODE Input Capture/Output Compare Square-Wave Generator Variable Duty-Cycle Square-Wave Generator Variable-Width Single-Shot Pulse Generator Pulse-Width Measurement Period Measurement Event Count Timer Bypass (Simple Test Mode)
OC1-OC0--Output Control These bits select the conditions under which TOUT changes (see Table 8-6). These bits may have a different effect when in the input capture/output compare mode. Caution should be used when modifying the OC bits near timer events. Table 8-6. OCx Encoding
OC1 0 0 1 1 OC0 0 1 0 1 TOUT MODE Disabled Toggle Mode Zero Mode One Mode
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Disabled--TOUT is disabled and three-stated. Toggle Mode--If the timer is disabled (SWR = 0) when this encoding is programmed, TOUT is immediately set to zero. If the timer is enabled (SWR = 1), time-out events (counter reaches $0000) toggle TOUT. In the input capture/output compare mode, TOUT is immediately set to zero if the timer is disabled (SWR = 0). If the timer is enabled (SWR = 1), timer compare events toggle TOUT. (Timer compare events occur when the counter reaches the value stored in the COM.) Zero Mode--If the timer is disabled (SWR = 0) when this encoding is programmed, TOUT is immediately set to zero. If the timer is enabled (SWR = 1), TOUT will be set to zero at the next time-out. In the input capture/output compare mode, TOUT is immediately set to zero if the timer is disabled (SWR = 0). If the timer is enabled (SWR = 1), TOUT will be set to zero at time-outs and set to one at timer compare events. If the COM is $0000, TOUT will be set to zero at the time-out/timer compare event. One Mode--If the timer is disabled (SWR = 0) when this encoding is programmed, TOUT is immediately set to one. If the timer is enabled (SWR = 1), TOUT will be set to one at the next time-out. In the input capture/output compare mode, TOUT is immediately set to one if the timer is disabled (SWR = 0). If the timer is enabled (SWR = 1), TOUT will be set to one at timeouts and set to zero at timer compare events. If the COM is $0000, TOUT will be set to one at the time-out/timer compare event.
8.4.4 Status Register (SR)
The SR contains timer status information as well as the state of the prescaler. This register is updated on the rising edge of the system clock when a read of its location is not in progress, allowing the most current information to be contained in this register. The register can be read, and the TO, TG, and TC bits can be written when the timer module is enabled (i.e., the STP bit in the MCR is cleared). SR
15 IRQ 14 TO 13 TG 12 TC 11 TGL 10 ON 9 OUT 8 COM 7 PO7 6 PO6 5 PO5 4 PO4 3 PO3 2 PO2 1 PO1
$608
0 PO0
RESET ( TGATE NEGATED):
0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1
RESET ( TGATE ASSERTED):
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Supervisor/User IRQ--Interrupt Request bit The positioning of this bit in the most significant location in this register allows it be conditionally tested as if it were a signed binary integer. 1 = An interrupt condition has occurred. This bit is the logical OR of the enabled TO, TG, and TC interrupt bits. 0 = The bit(s) that caused the interrupt condition has been cleared. If an IRQ signal has been asserted, it is negated when this bit is cleared.
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TO--Time-out Interrupt 1 = The counter has transitioned from $0001 to $0000, and the counter has rolled over. This bit does not affect the programmed IRQ signal if the IE2 bit in the CR is cleared. 0 = This bit is cleared by the timer whenever the RESET signal is asserted on the IMB, regardless of the mode of operation. This bit may also be cleared by writing a one to it. Writing a zero to this bit does not alter its contents. This bit is not affected by disabling the timer (SWR = 0). TG--Timer Gate Interrupt 1 = This bit is set whenever the CR TGE bit is set and the TGATE signal transitions in the manner to which the particular mode of operation responds. Refer to 8.3 Operating Modes for more details. This bit does not affect the programmed IRQ signal if the IE1 bit in the CR is cleared. 0 = This bit is cleared by the timer whenever the RESET signal is asserted on the IMB, regardless of the mode of operation. This bit may also be cleared by writing a one to it. Writing a zero to this bit does not alter its contents. This bit is not affected by disabling the timer (SWR = 0). TC--Timer Compare Interrupt 1 = This bit is set when the counter transitions (off a clock/event falling edge) to the value in the COM. This bit does not affect the programmed IRQ signal if the IE0 bit in the CR is cleared. 0 = This bit is cleared by the timer whenever the RESET signal is asserted on the IMB, regardless of the mode of operation. This bit may also be cleared by writing a one to it. Writing a zero to this bit does not alter its contents. This bit is not affected by disabling the timer (SWR = 0). TGL--TGATE Level 1 = The TGATE signal is negated. 0 = The TGATE signal is asserted. ON--Counter Enabled 1 = This bit is set whenever the SWR and CPE bits are set in the CR. If the CR TGE bit is set, TGATE must also be asserted (except in the input capture/output compare mode) since this signal then controls the enabling and disabling of the counter. If all these conditions are met, the counter is enabled and begins counting down. 0 = The counter is not enabled and does not begin counting down. OUT--Output Level 1 = TOUT is a logic one. 0 = TOUT is a logic zero, or the pin is three-stated. COM--Compare Bit This bit is used to indicate when the counter output value is at or between the value in the COM and $0000 (time-out).
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1 = This bit is set when the counter output equals the value in the COM. 0 = This bit is cleared when a time-out occurs, the COM register is accessed (read or write), the timer is reset with the SWR bit, or the RESET signal is asserted on the IMB. This bit is cleared regardless of the state of the TC bit. This bit can be used to indicate when a write to the PREL1 or PREL2 registers will not cause a problem during a counter reload at time-out. To ensure that the write to the PREL register is recognized at time-out, the latency between the read of the COM bit and the write to the PREL register must be considered. PO7-PO0--Prescaler Output These bits show the levels on each of the eight output taps of the prescaler. These values are updated every time that the system clock goes high and a read cycle of this byte in the SR is not in progress.
8.4.5 Counter Register (CNTR)
The CNTR reflects the value of the counter. This value can be reliably read at any time since it is updated on every rising edge of the system clock (except in the input capture/output compare mode) when a read of the register is not in progress. This readonly register can be read when the timer module is enabled (i.e., the STP bit in the MCR is cleared). CNTR
15 CNT15 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 CNT14 13 CNT13 12 CNT12 11 CNT11 10 CNT10 9 CNT9 8 CNT8 7 CNT7 6 CNT6 5 CNT5 4 CNT4 3 CNT3 2 CNT2 1 CNT1
$60A
0 CNT0
Supervisor/User All 24 bits of the prescaler and the counter may be obtained by one long-word read at the address of the SR, since the CNTR is contiguous to it. Any changes in the prescaler value due to the two cycles necessary to perform a long-word read should be considered. If this latency presents a problem, the TGATE signal may be used to disable the decrement function while the reads are occurring.
8.4.6 Preload 1 Register (PREL1)
The PREL1 stores a value that is loaded into the counter in some modes of operation. This value is loaded into the counter on the first falling edge of the counter clock after the counter is enabled. This register can be read and written when the timer module is enabled (i.e., the STP bit in the MCR is cleared). However, a write to this register must be completed before time-out for the new value to be reliably loaded into the counter.
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PREL1
15 14 13 12 11 10 9 PR1-9 8 PR1-8 7 PR1-7 6 PR1-6 5 PR1-5 4 PR1-4 3 PR1-3 2 PR1-2 1 PR1-1 PR1-15 PR1-14 PR1-13 PR1-12 PR1-11 PR1-10 RESET: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
$60C
0 PR1-0
1
Supervisor/User For some modes of operation, this register is also used to reload the counter one falling clock edge after a time-out occurs. Refer to 8.3 Operating Modes for more information on the individual modes.
8.4.7 Preload 2 Register (PREL2)
PREL2 is used in addition to PREL1 in the variable duty-cycle square-wave generator and variable-width single-shot pulse generator modes. When in either of these modes, the value in PREL1 is loaded into the counter on the first falling edge of the counter clock after the counter is enabled. After time-out, the value in PREL2 is loaded into the counter. This register can be read and written when the timer module is enabled (i.e., the STP bit in the MCR is cleared). However, a write to this register must be completed before time-out for the new value to be reliably loaded into the counter. PREL2
15 14 13 12 11 10 9 PR2-9 8 PR2-8 7 PR2-7 6 PR2-6 5 PR2-5 4 PR2-4 3 PR2-3 2 PR2-2 1 PR2-1 PR2-15 PR2-14 PR2-13 PR2-12 PR2-11 PR2-10 RESET: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
$60E
0 PR2-0
Supervisor/User
8.4.8 Compare Register (COM)
The COM can be used in any mode. When the 16-bit counter reaches the value in the COM, the TC and COM bits in the SR are set. In the input capture/output compare mode, a compare event can be programmed to set, clear, or toggle TOUT. The register can be read and written when the timer module is enabled (i.e., the STP bit in the MCR is cleared). COM
15 14 13 12 11 10 9 COM9 8 COM8 7 COM7 6 COM6 5 COM5 4 COM4 3 COM3 2 COM2 1 COM1 COM15 COM14 COM13 COM12 COM11 COM10 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$610
0 COM0
Supervisor/User The COM can be used to produce an interrupt when the SR TC bit has been enabled to produce an interrupt and the counter counts down to a preselected value. The COM can also be used to indicate that the timer is approaching time-out.
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Caution must be exercised when accessing the COM. If it were to be accessed simultaneously by the compare logic and by a write, the old compare value may get compared to the counter value.
8.5 TIMER MODULE INITIALIZATION SEQUENCE
The following paragraphs discuss a suggested method for initializing the timer module.
8.5.1 Timer Module Configuration
If the timer capability of the MC68341 is being used, the following steps should be followed to initialize a timer module properly. Control Register (CR) * Clear the SWR bit to disable the timer. Status Register (SR) * Clear the TO, TG, and TG bits to reset the interrupts. Module Configuration Register (MCR) * Initialize the STP for normal operation. * Select whether to respond to or ignore FREEZE (FRZx bits). * Select the access privilege for the supervisor/user registers (SUPV bit). * Select the interrupt arbitration level for the timer module (IARBx bits). Interrupt Register (IR) * Program the interrupt priority level for the timer interrupts (ILx bits). * Program the interrupt vector number for the timer interrupts (IVx bits). Preload Registers (PREL1 and PREL2) * If required, initialize the preload registers for mode of operation. Compare Register (COM) * If desired, initialize the compare register. The following steps begin operation: Control Register (CR) * Set the SWR bit to enable the timer. * Enable the desired interrupts (IEx bits). * Enable TGATE if required for mode of operation (TGE bit). * Select the prescaler clock (PCLK bit). * Enable the counter prescaler (CPE bit). * Select the selected clock (CLK bit).
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* If the PCLK bit is set, select the POTx bits. * Select the mode of operation (MODEx bits). * Select the operation of TOUT (OCx bits).
8.5.2 Timer Module Example Configuration Code
The following code is an example of a configuration sequence for the timer module. *************************************************************************** * MC68341 basic timer module register initialization example code. * This code is used to initialize the 68341's internal timer module * registers, providing basic functions for operation. * It sets up timer for square wave generation. *************************************************************************** *************************************************************************** * equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM40 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM40 MBAR address value *************************************************************************** * Timer module equates TIMER EQU $600 Offset from MBAR for timer module regs MCR EQU $0 MCR for timer * Timer register offsets from timer base address IR EQU $604 interrupt register timer CR EQU $606 control register timer SR EQU $608 status register timer CNTR EQU $60A counter register timer PRLD1 EQU $60C preload register 1 timer COM EQU $610 compare register timer
*************************************************************************** *************************************************************************** * Initialize Timer *************************************************************************** LEA MODBASE+TIMER,A0 Pointer to timer module * Disable timer CLR.W
CR(A0)
* Clear the TO, TG, and TC bits CLR.W SR(A0) * Module configuration register: * Timer module is set for normal operation, ignore FREEZE.
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* Supervisor/user timer registers unrestricted. * Interrupt arbitration at priority $03. MOVE.W #$0003,MCR(A0) * Initialize timer interrupt level to 2 and vector to $0F MOVE.W #$020F,IR(A0) * Initialize preload 1 to 3 MOVE.W #$0003,PRLD1(A0)
* Initialize the compare register to 0 CLR.W COM(A0) * Control register: * Enable timer, no interrupts are enabled, TGATE signal has no effect. * Use the selected clock for the counter clock, and enable it. * Selected clock is 1/2 system's freq. Square-wave generation, toggle TOUT. MOVE.W #$8205,CR(A0) *************************************************************************** END ***************************************************************************
*************************************************************************** * MC68341 basic timer module register initialization example code. * This code is used to initialize the 68341's internal timer module * registers, providing basic functions for operation. * It sets up timer for pulse-width measurement. In this mode, the number * of clock cycles during a particular event are counted. The event is * defined by the assertion and negation of TGATE. *************************************************************************** *************************************************************************** * equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM40 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM40 MBAR address value *************************************************************************** * Timer module equates TIMER EQU $600 Offset from MBAR for timer module regs MCR EQU $0 MCR for timer
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* Timer register offsets from timer base address IR EQU $604 interrupt register timer CR EQU $606 control register timer SR EQU $608 status register timer CNTR EQU $60A counter register timer COM EQU $610 compare register timer
*************************************************************************** *************************************************************************** * Initialize Timer *************************************************************************** LEA MODBASE+TIMER,A0 Pointer to timer module * Disable timer CLR.W
CR(A0)
* Allow TGATE to negate and assert so that an accurate count will result. * If SR TGL bit=1, continue looping. TGATE is negated. LOOP1 BTST.B #$3,SR(A0) BNE.B LOOP1 * If TGL bit=0, continue looping. TGATE is asserted. LOOP2 BTST.B #$3,SR(A0) BEQ.B LOOP2 * Ready to initialize timer, TGATE is negated. * Module configuration register: * Timer module is set for normal operation, ignore FREEZE. * Supervisor/user timer registers unrestricted. * Interrupt arbitration at priority $03. MOVE.W #$0003,MCR(A0) * Initialize timer interrupt level to 2 and vector to $0F MOVE.W #$020F,IR(A0) * Initialize the compare register to 0 CLR.W COM(A0) * Clear the SR TG bit (by writing a 1) to use as a flag MOVE.B #$20,SR(A0) * Control register: * Enable timer, no interrupts are enabled, TGATE signal used to control * the counter. Use the selected clock for the counter clock, and enable it. * Selected clock is 1/2 system's freq. Pulse-width measurement, * disable TOUT.
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MOVE.W
#$8A10,CR(A0)
* If SR TG bit=0, continue looping TGATE is asserted, * else TG=1 indicating TGATE was negated. When TG=1, counting is stopped. LOOP3 BTST.B #$5,SR(A0) BEQ.B LOOP3 * Counting is complete. To determine the number of cycles counted, the value * in CNTR must be read, inverted, and incremented by 1. MOVE.W CNTR(A0),D0 NOT.W D0 ADDQ.W #$1,DO * D0 contains the number of cycles counted. *************************************************************************** END ***************************************************************************
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SECTION 9 QUEUED SERIAL PERIPHERAL MODULE
The queued serial peripheral module (QSPM) provides a queued serial peripheral interface (QSPI). The QSPI is a full-duplex, synchronous serial interface for communicating with peripherals or microprocessors. It is enhanced by the addition of a queue for receive and transmit data. This section provides a block diagram, memory map, pin description, and register descriptions of the QSPM, with a breakdown of the QSPI submodule. Operation of the QSPI submodule includes master mode and slave mode. For a detailed description refer to 9.5.5.1 Master Mode and 9.5.5.2 Slave Mode. To aid in understanding the numerous bits and fields of the registers that appear throughout the text, a quick reference guide identifies all bit/field acronyms. (Refer to Table 9-3.). The MC68341 physically integrates the entire MC68332 queued serial module (QSM) onchip. However, due to the availability of two full-featured serial channels in the serial module, the QSM's serial communications interface (SCI) signals are not brought out. Register bits corresponding to the SCI logic are shown as undefined/reserved for the MC68341 and should not be changed from their default reset state.
9.1 BLOCK DIAGRAM
Figure 9-1 depicts the major components of the QSPM, which consist of the global registers, logic control, and the QSPI submodule. Refer to 9.5 QSPI Submodule for further definition of these components.
QSPI SUB-MODULE
MISO MOSI SCK PC0/SS PCS1
IMB
INTERFACE LOGIC
Figure 9-1. QSPM Block Diagram
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9.2 MEMORY MAP
The QSPM memory map is comprised of the global registers, the QSPI control and status registers, and the QSPI RAM as shown in Figure 9-2. For an accurate location of the QSPM in the MC68341 memory map, refer to Figure 4-1 SIM41 Module Register Block. The QSPM memory map may be divided into two segments: supervisor-only data space and assignable data space.
15 $800 $802 $804 $806 $808 $80A $80C $80E $810 $812 $814 $816 $818 $81A $81C $81E $820-FF $900-1F $920-3F $940-4F SPCR3 RESERVED REC.RAM TRAN.RAM COMD .RAM QUEUE RAM RESERVED QPAR SPCR0 SPCR1 SPCR2 SPSR QILR RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED QPDR QDDR ASSIGNABLE DATA SPACE (SUPERVISOR-ONLY OR UNRESTRICTED) 87 QMCR QTEST QIVR 0
SUPERVISOR-ONLY DATA SPACE
Figure 9-2. QSPM Memory Map The supervisor-only data space segment contains the QSPM global registers. These registers define parameters needed by the QSPM to integrate with the CPU. Access to these registers is permitted only when the CPU is operating in supervisor mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to both supervisor and user accesses. The supervisor (SUPV) bit in the QSPM module configuration register (QMCR) designates the assignable data space as either supervisor or unrestricted. If SUPV is set, then the space is designated as supervisor-only space. Access is then permitted only when the CPU is operating in supervisor mode. All attempts to read supervisor data spaces when not in supervisor mode (CPU status register, S bit = 0) return a value of zero, and all attempts to write have no effect. If SUPV is clear, both user and supervisor accesses are permitted. To clear SUPV in the QMCR, the CPU must be in supervisor mode (CPU status register, S-bit = 1).
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The QSPM assignable data space segment contains the QSPI, control/status registers, and the QSPI RAM. All registers and RAM may be accessed on byte, word, and long-word boundaries. The 80 bytes of static RAM are distinct from the QSPM register set. All bytes not used by the QSPI may be used as general-purpose RAM. When operating, the QSPI submodule uses three noncontiguous blocks of the 80-byte RAM for receive, transmit, and control data. More information on the QSPI RAM can be found in 9.5.4.6 QSPI RAM. The contents of most locations in the memory map may be rewritten with the identical value to that location, with one exception. (Refer to 9.5.4.3 QSPI Control Register 2 (SPCR2).) Writing a different value to certain control registers when a submodule using that register is enabled can cause unpredictable results. For predictable operation, if register bits are to be changed, the CPU should disable the submodule in an orderly fashion before altering the registers.
9.3 QSPM PINS
The QSPM has five external pins as shown in Figure 9-1. These pins, if not in use for their submodule function, can be used as general-purpose I/O port pins. Table 9-1 summarizes the QSPM pin functions, which are determined by the QSPI mode of operation (master or slave), the pin assignment register (QPAR), and by the appropriate QSPM data direction register (QDDR) bit.
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Table 9-1. QSPM Pin Summary
Pin Mode Master MISO Slave QDDR Bit 0 1 0 1 Master MOSI Slave 0 1 0 1 Master QSPI Pins SCK Slave 0 1 0 1 Master PCS0/SS Slave 0 1 0 1 Master PCS1 Slave X = QDDR bit ignored. 0 1 0 1 Pin Function Serial Data Input to QSPI Output Value from QPDR Input Value to QPDR Serial Data Output from QSPI Input Value to QPDR Serial Data Output from QSPI Serial Data Input to QSPI Output Value from QPDR Input Value to QPDR Clock Output from QSPI Clock Input to QSPI Output Value from QPDR Input (May Cause Mode Fault) Output Selects Peripherals Input Selects the QSPI Output Value from QPDR Input Value to QPDR Output Selects Peripherals Input Value to QPDR Output Value from QPDR
The QSPM pin control registers--QDDR, QSPM pin assignment register (QPAR), and QSPM port data register (QPDR)--affect pins being used as general-purpose I/O pins. The QSPI control register 0 (SPCR0) has one bit that affects pins employed as generalpurpose output pins. Within this register the wired-OR mode (WOMQ) control bit determines whether MISO, MOSI, SCK, PCS1, and PCS0 function as open-drain output pins or as normal output pins, regardless of their use as general-purpose I/O pins or as QSPI output pins.
9.4 REGISTERS
Registers of the QSPM are divided into three categories: QSPM global registers, QSPM pin control registers, and QSPI submodule registers. The QSPI registers are defined in 9.5 QSPI Submodule. Writes to unimplemented bits have no meaning or effect, and reads from unimplemented bits always return a logic zero value. In the registers discussed in the following pages, the numbers in the upper right-hand corner indicate the offset of the register from the base address specified in the module base address register (MBAR) in the SIM41. The numbers above the register description
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represent the bit position in the register. The register description contains the mnemonic for the bit. The values shown below the register description are the values of those register bits after a hardware reset. A value of U indicates that the bit value is unaffected by reset. Table 9-2 is a summary of the registers, bits, and reset states for the full QSPM module. As previously mentioned, Table 9-3 is a quick reference guide to all the bits/fields of the QSPM module. Along with the function, the register and register location of each bit/field are identified. Table 9-2. QSPM Register Summary
15 14 13 12 0 0 0 0 ILQSPI 0 0 0 0 11 0 0 0 0 10 0 0 0 0 9 0 0 0 0 RESERVED 0 0 0 0 0 0 8 0 0 0 0 7 SUPV 1 0 0 6 0 0 0 0 5 0 0 0 0 4 0 0 0 0 INTV 1 1 1 1 0 0 3 2 IARB 0 0 1 0 QMCR $800 STOP FRZ1 FRZ0 RESET: QTEST $802 RESET: QILR-QIVR $804 RESET: $806 - $812 QPDR $814 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSBD RSVD TQSM RSVD 0 0 0 0
Reserved 0 RSVD D4 D3 D2 D1 D0
(PCS1) (PCS0* ) (SCK) (MOSI) (MISO)
RESET: QPAR-QDDR $816 RESET:
0 0
0
0
0
0
0 0
0
0
0
0 RSVD
0
0
0
0
0
0
RSVD RSVD PCS1 PCS0*
MOSI MISO
PCS1 PCS0* SCK
MOSI MISO
0
0
0
0 BITS
0
0
0
0
0
0
0
0 SPBR
0
0
0
0
SPCRO $818 MSTR WOM Q RESET: SPCR1 $81A RESET: 0 SPE 0 0 0 0 0 0 0 0
CPOL CPHA 0 0 0 1 0 0 0 0
0 DTL
1
0
0
DSCKL 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
1
0
0
SPCR2 $81C SPIFI WREN WRTO E RESET: SPCR3-SPSR $81E RESET: $820- $8FF REC.RAM $900- $91F TRAN.RAM $920- $93F COMD.RAM CONT BITSE $940- $94F DT 0 0 0 0 0 0 0 0 0
ENDQP 0 0
LOOP Q
NEWQP 0 0 0 0
0
0 0
0 0
HMIE HALT 0 0
SPIF MODF HALT A 0 0 0
CPTQP 0 0 0 0
0
Reserved QSPI Receive Data (16 Words) QSPI Transmit Data (16 Words) DSCK RSVD RSVD PCS1 PCS0* CONT BITSE DT DSCK RSVD RSVD PCS1 PCS0*
* The PCS0 bit listed above represents the dual-function PCS0//SS.
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Table 9-3. Bit/Field Quick Reference Guide (Sheet 1 of 2)
Bit/Field Mnemonic SPBR BITS BITSE CONT CPHA CPOL CPTQP DSCK DSCKL DT DTL ENDQP FRZ1-FRZ0 HALT HALTA HMIE IARB ILQSPI INTV LOOPQ MISO MODF MOSI MSTR NEWQP PCS0/SS PCS1 SCK SPE SPIF SPIFIE STOP Serial Clock Baud Rate Bits Per Transfer Bits Per Transfer Enable Continue Clock Phase Clock Polarity Completed Queue Pointer Peripheral Select Chip (PSC) to Serial Clock (SCK) Delay Delay before Serial Clock (SCK) Delay after Transfer Length of Delay after Transfer Ending Queue Pointer Freeze1-0 Halt Halt Acknowledge Flag Halt Acknowledge Flag (HALTA) and Mode Fault Flag (MODF) Interrupt Enable Interrupt Arbitration Identification Number Interrupt Level for QSPI Interrupt Vector QSPI Loop Mode Master in Slave Out Mode Fault Flag Master Out Slave In Master/Slave Mode Select New Queue Pointer Value Peripheral Chip Select/Slave Select Peripheral Chip Select Serial Clock QSPI Enable QSPI Finished Flag SPI Finished Interrupt Enable Stop Function Register SPCR0 SPCR0 QSPI RAM QSPI RAM SPCR0 SPCR0 SPSR QSPI RAM SPCR1 QSPI RAM SPCR1 SPCR2 QMCR SPCR3 SPSR SPCR3 QMCR QILR QIVR SPCR3 QPAR/QDDR/QPDR SPSR QPAR/QDDR/QPDR SPCR0 SPCR2 QPAR/QDDR/QPDR QPAR/QDDR/QPDR QDDR/QPDR SPCR1 SPSR SPCR2 QMCR Register Location QSPI QSPI QSPI QSPI QSPI QSPI QSPI QSPI QSPI QSPI QSPI QSPI QSPM QSPI QSPI QSPI QSPM QSPM QSPM QSPI QSPM QSPI QSPM QSPI QSPI QSPM QSPM QSPM QSPI QSPI QSPI QSPM
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Table 9-3. Bit/Field Quick Reference Guide (Sheet 2 of 2)
Bit/Field Mnemonic SUPV TQSM TSBD WOMQ WREN WRTO Supervisor/Unrestricted Test QSPM Enable SPI Test Scan Path Select Wired-OR Mode for QSPI Pins Wrap Enable Wrap To Select Function Register QMCR QTEST QTEST SPCR0 SPCR2 SPCR2 Register Location QSPM QSPM QSPM QSPI QSPI QSPI
9.4.1 Overall QSPM Configuration Summary
After reset, the QSPM remains in an idle state, requiring initialization of several registers before any serial operations may begin execution. The following registers, fields, and bits are fully described later in this section. A general sequence guide for initialization follows: * QMCR (refer to 9.4.2.1 QSPM Configuration Register (QMCR)) *********em dash under a bullet???? This register must be initialized to properly configure: --Interrupt arbitration identification number used by the entire QSPM module --Supervisor/unrestricted bit (SUPV) --FREEZE and/or STOP configuration should remain cleared to zero for normal operation. * QIVR and QILR (refer to 9.4.2.3 QSPM Interrupt Level Register (QILR) and 9.4.2.4 QSPM Interrupt Vector Register (QIVR)) These registers are written to choose the base vector number for the QSPM module and interrupt level for the QSPI submodule. * QPDR and QDDR (refer 9.4.3.1 QSPM Port Data Register (QPDR) and 9.4.3.3 QSPM Data Direction Register (QDDR)) The pin control registers should be initialized in the order QPDR and then QDDR, thus establishing the default state and direction of the QSPM pins. For configuration of the QSPI submodule, initialize as follows: * RAM (refer to 9.5.4.6 QSPI RAM) * QPAR (refer 9.4.3.2 QSPM Pin Assignment Register (QPAR)) Assignment of appropriate pins to the QSPI must be made with this register. * SPCR0 (refer 9.5.4.1 QSPI Control Register 0 (SPCR0))
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The system designer must choose a transfer rate (baud) for operation in master mode, an appropriate clock phase, clock polarity, and the number of bits to be transferred in a serial operation. Master/slave mode select (MSTR) must be set to configure the QSPI for master mode or cleared to configure operation in slave mode. WOMQ should be set to enable or cleared to disable wired-OR mode operation. * SPCR1 (refer to 9.5.4.2 QSPI Control Register (SPCR1)) --SPE must be set to enable the QSPI; this register should be written last. --DTL allows the user to program a delay after any serial transfer, which is invoked by the DT bit for any serial transfer. --DSCKL allows the user to set a delay before SCK (after PCS valid), which is invoked by the DSCK bit for any transfer. * SPCR2 (refer to 9.5.4.3 QSPI Control Register 2 (SPCR2)) --NEWQP and ENDQP, respectively, determine the beginning of a queue and the number of serial transfers (up to 16) to be considered a complete queue. --WREN is set to enable queue wraparound, and WRTO helps determine the address used in wraparound mode. --SPIFIE is set to enable interrupts when SPIF is asserted. * SPCR3 (refer to 9.5.4.4 QSPI Control Register 3 (SPCR3)) HALT may be used for program debug, and HMIE is set to enable CPU interrupts when HALTA or MODF is asserted; LOOPQ is set only to enable a feedback loop that can be used for self-test mode.
9.4.2 QSPM Global Registers
The QSPM global registers contain system parameters used by the QSPM to interface with the CPU and other system modules. The four global registers are listed in Table 9-4. Table 9-4. QSPM Global Registers
Address $800 $802 $804 $805 Name QMCR QTEST QILR QIVR Usage QSPM Configuration Register QSPM Test Register QSPM Interrupt Level Register QSPM Interrupt Vector Register
9.4.2.1 QSPM CONFIGURATION REGISTER (QMCR). QMCR contains parameters for interfacing to the CPU and the intermodule bus (IMB). This register can be modified only when the CPU is in supervisor mode.
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QMCR
15 STOP 14 FRZ1 13 FRZ0 12 0 11 0 10 0 9 0 8 0 7 SUPV 6 0 5 0 4 0 3 2 IARB 1
$800
0
RESET: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
STOP--Stop Enable 1 = QSPM clock operation stopped 0 = Normal QSPM clock operation STOP places the QSPM into a low power state by disabling the system clock in most parts of the module. QMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is not readable; however, writes to RAM or any register are guaranteed valid while STOP is asserted. STOP may be negated by the CPU and by reset. The system software must stop each submodule before asserting STOP to avoid complications at restart and to avoid data corruption. The QSPI submodule should be stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set. FRZ1--Freeze1 1 = Halt the QSPM (on a transfer boundary) 0 = Ignore the FREEZE signal on the IMB FRZ1 determines what action is taken by the QSPM when the FREEZE signal of the IMB is asserted. FREEZE is asserted whenever the CPU enters the background mode. NOTE Ignoring the FREEZE signal can cause unpredictable results in the background mode operation of the QSPM, because the CPU is unable to service interrupt requests in this mode. If FRZ1 equals one when the FREEZE line is asserted, the QSPM comes to an orderly halt on a transfer boundary as if HALT had been asserted. The output pins continue to drive their last state. Once the FREEZE signal is negated, the QSPM module restarts automatically. FRZ0--Freeze0 Reserved for future enhancement. Bits 12-8--Not Implemented SUPV--Supervisor/Unrestricted 1 = Supervisor access All registers in the QSPM are placed in supervisor-only space. For any access from within user mode, address acknowledge (AACK) is not returned and the bus cycle is transferred externally.
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0 = User access Because the QSPM contains a mix of supervisor and user registers, AACK returns for accesses with either supervisor or user mode, and the bus cycle remains internal. If a supervisor-only register is accessed in user mode, the module responds as if an access had been made to an unimplemented register location. SUPV defines the assignable QSPM registers as either supervisor-only data space or unrestricted data space. Bits 6-4--Not Implemented IARB--Interrupt Arbitration Identification Number Each module that generates interrupts, including the QSPM, must have an IARB field. The value in this field is used to arbitrate for the IMB when two or more modules generate simultaneous interrupts of the same priority level. No two modules can share the same IARB value. The reset value of the IARB field is $0, which prevents the QSPM from arbitrating during an interrupt acknowledge cycle (IACK). The IARB field should be initialized by system software to a value between $F (top priority) and $1 (lowest priority). Otherwise, any interrupts generated are identified by the CPU as spurious. 9.4.2.2 QSPM TEST REGISTER (QTEST). QTEST is used in testing the QSPM. Accesses to QTEST must be made while the MC68341 is in test mode. QTEST
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 TSBD 2 1 RSVD TQS M
$802
0 RSVD
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSBD--SPI Test Scan Path Select 1 = Enable delay to SCK scan path 0 = Enable SPI baud clock scan path RSVD--Reserved TQSM--QSPM Test Enable 1 = Enable QSPM to send test scan paths 0 = Disable scan path 9.4.2.3 QSPM INTERRUPT LEVEL REGISTER (QILR). The QILR determines the priority level of interrupts requested by the QSPM and the vector used when acknowledging an interrupt. This register may be accessed only when the CPU is in supervisor mode.
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QILR
15 0 14 0 13 12 ILQSPI 11 10 9 RSVD 8 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
$804
0
RESET: 0 0 0 0 0 0 0 0
ILQSPI--Interrupt Level for QSPI ILQSPI determines the priority level of all QSPI interrupts. This field should be programmed to a value between $0 (interrupts disabled) to $7 (highest priority). 9.4.2.4 QSPM INTERRUPT VECTOR REGISTER (QIVR). At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the exception table. This vector is selected until QIVR is written. QIVR should be programmed to one of the userdefined vectors ($40-$FF) during initialization of the QSPM. After initialization, QIVR determines which vector in the exception vector table is to be used for QSPM interrupts. The value of INTV0 used during an IACK cycle is supplied by the bus interface unit (BIU). During an IACK, INTV7-INTV1 are driven on the DATA7- DATA1 IMB lines. The BIU drives DATA0 with a one for a QSPI interrupt. Writes to INTV0 have no meaning or effect. Reads of INTV0 return a value of one. QIVR
15 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX RESET: 0 0 0 0 1 1 1 1 7 6 5 4 INTV 3 2 1
$805
0
9.4.3 QSPM Pin Control Registers
Table 9-5 identifies the three pin control registers of the QSPM. The QSPM determines the use of five pins, which form a parallel port. Although these pins are used by the serial subsystems, any pin may alternately be assigned as general-purpose I/O on a pin-by-pin basis. For use of these pins as general-purpose I/O, they must not be assigned to the QSPI submodule in register QPAR. To avoid briefly driving incorrect data, the first byte to be output should be written before register QDDR is configured for any output pins. QDDR should then be written to determine the direction of data flow on the pins and to output the value contained in register QPDR for all pins defined as outputs. Subsequent data for output is then written to QPDR. Table 9-5. QSPM Pin Control Registers
Address $815 $816 $817 Name QPDR QPAR QDDR Usage QSPM Port Data Register QSPM Pin Assignment Register QSPM Data Direction Register
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9.4.3.1 QSPM PORT DATA REGISTER (QPDR). QPDR determines the actual input or output value of a QSPM port pin, if the pin is defined in QPAR as general-purpose I/O. All QSPM port pins may be used as general-purpose I/O. Writes to this register affect the pins defined as outputs; reads of this register return the actual value of the pins. QPDR
15 RESERVED 7 6 RSVD 5 4 3 2 1 D4 D3 (PCS1) (PCS0/ S S)
$815
0 D2 D1 D0 (SCK) (MOSI) (MISO)
RESET: 0 0 0 0 0 0 0 0
9.4.3.2 QSPM PIN ASSIGNMENT REGISTER (QPAR). QPAR determines which of the QSPI pins, with the exception of the SCK pin, are actually used by the QSPI submodule, and which pins are available for general-purpose I/O. Pins may be assigned to the QSPI or to function as general-purpose I/O on a pin-by-pin basis. QSPI pins designated by QPAR as general-purpose I/O are controlled only by QDDR and QPDR. The QSPI has no effect on these pins. QPAR
15 0 14 13 12 11 10 0 9 MOSI 8 MISO XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX RSVD RSVD PCS1 PCS0/S S
$816
0
RESET: 0 0 0 0 0 0 0 0
0 = General-purpose I/O 1 = QSPI module
Bit 15--Not Implemented Bits 14-13--Reserved PCS1--Peripheral Chip Select 1 PCS0/SS--Peripheral Chip Select 0/Slave Select These bits determine whether the associated QSPM port pins function as generalpurpose I/O pins or are assigned to the QSPI submodule. Bit 10--Not Implemented (When the QSPI is enabled, the SCK pin is required.) MOSI--Master Out Slave In MISO--Master In Slave Out
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These bits determine whether the associated QSPM port pin functions as a generalpurpose I/O pin or is assigned to the QSPI submodule. 9.4.3.3 QSPM DATA DIRECTION REGISTER (QDDR). QDDR determines each I/O pin as an input or an output regardless of whether the QSPI submodule is enabled or disabled. All QSPM pins are configured during reset as general-purpose inputs. (The QSPI is disabled.) QDDR
15 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX RESET: 0 0 0 0 0 0 0 0 7 6 RSVD 5 4 3 2 SCK 1 MOSI PCS1 PCS0/S S
$817
0 MISO
0 = Input 1 = Output
Bits 7--Reserved PCS1--Peripheral Chip Select 1 PSC0/SS--Peripheral Chip Select 0/Slave Select SCK--Serial Clock MOSI--Master Out Slave In MISO--Master In Slave Out All of these bits determine the QSPI port pin operation to be input or output. 1 = Output 0 = Input
9.5 QSPI SUBMODULE
The QSPI submodule communicates with external peripherals via synchronous serial bus. The QSPI is fully compatible with the serial peripheral interface (SPI) systems found on other Motorola devices such as the M68HC11 and M68HC05 Families. It has all of the capabilities of the SPI system as well as several new features. The following paragraphs describe the features, block diagram, pin descriptions, programmer's model (memory map) inclusive of registers, and the master and slave operation of the QSPI.
9.5.1 Features
Standard SPI features are listed below, followed by a list of the additional features offered on the QSPI: * Full Duplex, Three-Wire Synchronous Transfers
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* Half Duplex, Two-Wire Synchronous Transfers * Master or Slave Operation * Programmable Master Bit Rates * Programmable Clock Polarity and Phase * End-of-Transmission Interrupt Flag * Master-Master Mode Fault Flag * Easily Interfaces to Simple Expansion Parts (A/D converters, EEPROMS, display drivers, etc.) QSPI-Enhanced features are as follows: * Programmable Queue--Up to 16 Preprogrammed Transfers * Programmable Peripheral Chip Selects--Two Pins Select Up to Four SPI Chips * Wraparound Transfer Mode--For Autoscanning of Serial A/D (or Other) Peripherals, With No CPU Overhead * Programmable Transfer Length--From 8-16 Bits Inclusive * Programmable Transfer Delay--From 1 s to 0.5 ms (at 16.78 MHz) * Programmable Queue Pointer * Continuous Transfer Mode--Up to 256 Bits 9.5.1.1 PROGRAMMABLE QUEUE. A programmable queue allows the QSPI to perform up to 16 serial transfers without CPU intervention. Each transfer corresponds to a queue entry containing all the information needed by the QSPI to independently complete one serial transfer. This unique feature greatly reduces CPU/QSPI interaction, resulting in increased CPU and system throughput. 9.5.1.2 PROGRAMMABLE PERIPHERAL CHIP SELECTS. Two peripheral chip-select pins allow the QSPI to access up to four independent peripherals by decoding the two peripheral chip-select signals. Two independent peripherals can be selected by direct connection to a chip-select pin. The peripheral chip selects simplify interfacing to two peripherals by providing dedicated peripheral chip-select signals, alleviating the need for CPU intervention. 9.5.1.3 WRAPAROUND TRANSFER MODE. Wraparound transfer mode allows automatic, continuous re-execution of the preprogrammed queue entries. Newly transferred data replaces previously transferred data. Wraparound simplifies interfacing with A/D converters by automatically providing the CPU with the latest A/D conversions in the QSPI RAM. Consequently, serial peripherals appear as memory-mapped parallel devices to the CPU. 9.5.1.4 PROGRAMMABLE TRANSFER LENGTH. The number of bits in a serial transfer is programmable from 8 to 16 bits, inclusive. For example, 10 bits could be used for communicating with an external 10-bit A/D converter. Likewise, a vacuum fluorescent
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display driver might require a 12-bit serial transfer. The programmable length simplifies interfacing to serial peripherals that require different data lengths. 9.5.1.5 PROGRAMMABLE TRANSFER DELAY. An inter-transfer delay may be programmed from approximately 1 to 500 s (using a 16.78-MHz system clock). For example, an A/D converter may require time between transfers to complete a new conversion. The default delay is 1 s. The programmable length of delay simplifies interfacing to serial peripherals that require delay time between data transfers. 9.5.1.6 PROGRAMMABLE QUEUE POINTER. The QSPI has a pointer that identifies the queue location containing the data for the next serial transfer. The CPU can switch from one task to another in the QSPI by writing to the queue pointer, changing the location in the queue that is to be transferred next. Otherwise, the pointer increments after each serial transfer. By segmenting the queue, multiple-task support can be provided by the QSPI. 9.5.1.7 CONTINUOUS TRANSFER MODE. The continuous transfer mode allows the user to send and receive an uninterrupted bit stream with a peripheral. A minimum of 8 bits and a maximum of 256 bits may be transferred in a single burst without CPU intervention. Longer transfers are possible; however, minimal CPU intervention is required to prevent loss of data. A 1-s pause (using a 16.78-MHz system clock) is inserted between each queue entry transfer.
9.5.2 Block Diagram
Figure 9-3 provides a block diagram of the QSPI submodule components.
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QUEUE POINTER
4 A D D R E S S 4 R E G I S T E R RAM
COMPARATOR
DONE
END QUEUE POINTER
STATUS REGISTER
CONTROL REGISTERS
DELAY COUNTER
4 CHIP SELECT 4 COMMAND
M S CONTROL PLA DATA SERIALIZER M S
MOSI
MISO PCS0/SS PCS1
BAUD-RATE GENERATOR
SCK
Figure 9-3. QSPI Submodule Diagram
9.5.3 QSPI Pins
Five pins are associated with the QSPI; however, when not needed for a QSPI application, they may be configured as general-purpose I/O pins. Figure 9-3 identifies the QSPI pins. Table 9-6 lists the QSPI external input and output pins and their functions. QSPM register QDDR determines whether the pins are designated as input or output. The user must initialize QDDR for the QSPI to function correctly.
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Table 9-6. External Pin Inputs/Outputs to the QSPI
Pin Names Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Select Peripheral Chip Select 2 Slave Select3 Slave Select4 Mnemonics MISO MOSI SCK 1 PCS1 PCS0/SS SS Mode Master Slave Master Slave Master Slave Master Master Slave Master Function Serial Data Input to QSPI Serial Data Output from QSPI Serial Data Output from QSPI Serial Data Input to QSPI Clock Output from QSPI Clock Input to QSPI Outputs Select Peripheral Output Selects Peripheral Input Selects the QSPI May Cause Mode Fault
NOTES: 1. All QSPI pins (except SCK) can be used as general-purpose I/O if they are not used by the QSPI while the QSPI is operating. 2. An output (PCS0 ) when the QSPI is in master mode. 3. An input ( SS) when the QSPI is in slave mode. 4. An input ( SS) when the QSPI is in master mode; useful in multimaster systems.
9.5.4 Programmer's Model and Registers
The programmer's model (memory map) for the QSPI submodule consists of the QSPM global and pin control registers (refer to 9.4.2 QSPM Global Registers and 9.4.3 QSPM Pin Control Registers), four QSPI control registers, one status register, and the 80-byte QSPI RAM. Table 9-7 lists the registers and the QSPI RAM of the programmer's model. All of the registers and RAM can be read and written by the CPU. The four control registers must be initialized, in proper order, before the QSPI is enabled to ensure defined operation. Only the control registers must adhere to the order of sequence prescribed in 9.4.1 Overall QSPM Configuration Summary. Write register SPCR1 last when setting up the QSPI, as this register contains the QSPI enable bit (SPE). Asserting this bit starts the QSPI. QSPI control registers are reset to a defined state and may then be changed by the CPU. Reset values are shown below each register. Table 9-7. QSPI Registers
Address $818, 9 $81A, B $81C, D $81E $81F $900-1F $920-3F $940-4F Name SPCR0 SPCR1 SPCR2 SPCR3 SPSR RAM RAM RAM Usage QSPI Control Register 0 QSPI Control Register 1 QSPI Control Register 2 QSPI Control Register 3 QSPI Status Register QSPI Receive Data (16 Words) QSPI Transmit Data (16 Words QSPI Command Control (8 Words)
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In general, rewriting the same value into a control register does not affect the QSPI operation with the exception of NEWQP (bits 3-0) in SPCR2. Rewriting the same value to these bits causes the RAM queue pointer to restart execution at the designated location. If control bits are to be changed, the CPU should halt the QSPI first. With the exception of SPCR2, writing a different value into a control register while the QSPI is enabled may disrupt operation. SPCR2 is buffered, preventing any disruption of the current serial transfer. After completion of the current serial transfer, the new SPCR2 values become effective. 9.5.4.1 QSPI CONTROL REGISTER 0 (SPCR0). SPCR0 contains parameters for configuring the QSPI before it is enabled. Although the CPU can read and write this register, the QSPM has read-only access. SPCR0
15 14 13 12 BITS 11 10 9 CPOL 8 CPHA 7 6 5 4 SPBR 3 2 1 MSTR WOM Q RESET: 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
$818
0
MSTR--Master/Slave Mode Select 1 = QSPI is system master and can initiate transmission to external SPI devices. 0 = QSPI is a slave device, and only responds to externally generated serial transfers. MSTR configures the QSPI for either master or slave mode operation. This bit is cleared on reset and may only be written by the CPU, not the QSPM. WOMQ--Wired-OR Mode for QSPI Pins 1 = All QSPI port pins designated as output by QDDR function as open-drain outputs and can be wire-ORed to other external lines. 0 = Output pins have normal outputs instead of open-drain outputs. WOMQ allows the QSPI pins to be wire-ORed, regardless of whether they are used as general-purpose outputs or as QSPI outputs. WOMQ affects the QSPI pins whether the QSPI is enabled or disabled. BITS--Bits Per Transfer In master mode, BITS determines the number of data bits transferred for each serial transfer in the queue that has the command control bit, BITSE of the QSPI RAM, equal to one. If BITSE equals zero for a command, 8 bits are transferred for that command regardless of the value in BITS. Data transfers from 8 to 16 bits are supported. Illegal (reserved) values all default to 8 bits. BITSE is not used in slave mode. All transfers are of the length specified by BITS. Table 9-8 shows the number of bits per transfer. Table 9-8. Bits per Transfer if Command Control Bit BITSE = 1
Bit 13 Bit 12 Bit 11 Bit 10 Bits per Transfer
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0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 8 9 10 11 12 13 14 15
CPOL--Clock Polarity 1 = The inactive state value of SCK is high. 0 = The inactive state value of SCK is low. CPOL is used to determine the inactive state value of the serial clock (SCK). CPOL is used in conjunction with CPHA to produce the desired clock-data relationship between master and slave device(s). For an understanding of the QSPI clock/data timing relationship, refer to the timing diagrams in Figures 9-24-9-27. CPHA--Clock Phase 1 = Data is changed on the leading edge of SCK and captured on the following edge of SCK. 0 = Data is captured on the leading edge of SCK and changed on the following edge of SCK. CPHA determines which edge of SCK causes data to change and which edge of SCK causes data to be captured. CPHA is used in conjunction with CPOL to produce the desired clock-data relationship between master and slave device(s). Note that CPHA is set at reset. SPBR--Serial Clock Baud Rate The QSPI internally generates the baud rate for SCK, the frequency of which is programmable by the user. The clock signal is derived from the MC68341 system clock using a modulus counter. At reset, BAUD is initialized to a 2.1-MHz SCK frequency. The user programs a baud rate for SCK by writing a baud value from 2 to 255. The following equation determines the SCK baud rate: SCK Baud Rate = System Clock/(2 * SPBR) (9-1)
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or SPBR = System Clock/(2 * SCK Baud Rate Desired) where SPBR equals 2, 3, 4, . . . , 255. Programming SPBR with the values zero or one disables the QSPI baud rate generator. SCK is disabled and assumes its inactive state value. No serial transfers occur. SPBR has 254 active values. Table 9-9 lists several possible baud values and the corresponding SCK frequency based on a 16.78-MHz system clock. Table 9-9. Examples of SCK Frequencies
System Clock Frequency 16.78 MHz Required Division Ratio 4 8 16 34 168 510 Value of SPBR 2 4 8 17 84 255 Actual SCK Frequency 4.19 MHz 2.10 MHz 1.05 MHz 493 kHz 100 kHz 33 kHz
(9-2)
9.5.4.2 QSPI CONTROL REGISTER 1 (SPCR1). SPCR1 contains parameters for configuring the QSPI before it is enabled. Although the CPU can read and write this register, the QSPM has read access only, except for SPE. This bit is automatically cleared by the QSPI after completing all serial transfers or when a mode fault occurs. SPCR1
15 SPE RESE T: 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 14 13 12 11 DSCKL 10 9 8 7 6 5 4 DTL 3 2 1
$81A
0
SPE--QSPI Enable 1 = The QSPI is enabled and the pins allocated by QSPM register QPAR are controlled by the QSPI. 0 = The QSPI is disabled, and the seven QSPI pins can be used as general-purpose I/O pins, regardless of the values in QPAR. This bit enables or disables the QSPI Submodule. Setting SPE causes the QSPI to begin operation. If the QSPI is a master, setting SPE causes the QSPI to begin initiating serial transfers. If the QSPI is a slave, the QSPI begins monitoring the PCS0/SS pin to respond to the external initiation of a serial transfer. When the QSPI is disabled, the CPU may use the QSPI RAM. When the QSPI is enabled, both the QSPI and the CPU have access to the QSPI RAM. The CPU has both read and write access capability to all 80 bytes of the QSPI RAM. The QSPI can read
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only the transmit data segment and the command control segment, and can write only the receive data segment of the QSPI RAM. By clearing SPE, the QSPI turns itself off automatically when it is finished. An error condition called mode fault (MODF) also clears SPE. This error occurs when PCS0/SS is configured for input, the QSPI is a system master (MSTR = 1), and PCS0/SS is driven low externally. To stop the QSPI, assert HALT, then wait until HALTA is set. SPE may then be safely cleared to zero, providing an orderly method of quickly shutting down the QSPI after the current serial transfer is completed. The CPU can immediately disable the QSPI by just clearing SPE; however, loss of data from a current serial transfer may result and confuse an external SPI device. DSCKL--Delay before SCK This bit determines the length of time the QSPI delays from peripheral chip select (PCS) valid to SCK transition for serial transfers in which the command control bit, DSCK of the QSPI RAM, equals one. PCS may be either of the peripheral chip-select pins. The following equation determines the actual delay before SCK: PCS to SCK Delay = [DSCKL/System Clock Frequency] (9-3) where DSCKL equals {1,2,3, . . . 127}. NOTE A zero value for DSCKL causes a delay of 128/system clocks, which equals 7.6 s for a 16.78-MHz system clock. Because of design limits, a DSCKL value of one defaults to the same timing as a value of two. If a queue entry's DSCK equals zero, then DSCKL is not used. Instead, the PCS validto-SCK transition is one-half SCK period. DTL--Length of Delay after Transfer These bits determine the length of time that the QSPI delays after each serial transfer in which the command control bit, DT of the QSPI RAM, equals one. The following equation is used to calculate the delay: Delay after transfer = [(32 * DTL)/system clock frequency] (9-4) where DTL equals {1,2,3, . . . 255}. NOTE A zero value for DTL causes a delay-after-transfer value of (32 * 256)/system clock, which equals 488.5 s with a 16.78MHz system clock. If DT equals zero, a standard delay is inserted. Standard Delay-after-Transfer = [17/System Clock] = 1 s with a 16.78-MHz System Clock
(9-5)
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Delay after transfer can be used to ensure that the deselect time requirement (for peripherals having such a requirement) is met. Some peripherals must be deselected for a minimum period of time between consecutive serial transfers. A delay after transfer can be inserted between consecutive transfers to a given peripheral to ensure that its minimum deselect time requirement is met or to allow serial A/D converters to complete conversion before the next transfer is made. 9.5.4.3 QSPI CONTROL REGISTER 2 (SPCR2). SPCR2 contains parameters for configuring the QSPI. Although the CPU can read and write this register, the QSPM has read access only. Writes to this register are buffered. A write to SPCR2 that changes any of the bit values (while the QSPI is operating) is ineffective on the current serial transfer, but becomes effective on the next serial transfer. Reads of SPCR2 return the actual current value of the register, not the buffer. Refer to 9.5.5 Operating Modes and Flowcharts for a detailed description of this register. SPCR2
15 14 13 12 0 11 10 9 8 7 0 6 0 5 0 4 0 3 2 1 SPIFIE WREN WRTO RESE T: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENDQP NEWQP
$81C
0
SPIFIE--SPI Finished Interrupt Enable 1 = QSPI interrupts enabled 0 = QSPI interrupts disabled SPIFIE enables the QSPI to generate a CPU interrupt upon assertion of the status flag SFIP. Because of its special buffering, the value written to SPIFIE applies only upon completion of the queue (the transfer of the entry indicated by ENDQP). Thus, if a single sequence of queue entries is to be transferred (i.e., no WRAP), then SPIFIE should be set to the desired state before the first transfer. If a subqueue (see bit NEWQP) is to be used, the same CPU write that causes a branch to the subqueue may enable or disable the SPIF interrupt for the subqueue. The primary queue retains its own selected interrupt mode, either enabled or disabled. The SPIF interrupt must be cleared by clearing SPIF. Later interrupts may then be prevented by clearing SPIFIE to zero. The QSPI has three possible interrupt sources, but only one interrupt vector. These sources are SPIF, MODF, and HALTA. When the CPU responds to a QSPI interrupt, the user must ascertain the exact interrupt cause by reading register SPSR. Any interrupt that was set may then be cleared by writing to SPSR with a zero in the bit position corresponding to the exact interrupt source. Clearing SPIFIE does not immediately clear an interrupt already caused by SPIF. WREN--Wrap Enable 1 = Wraparound mode enabled 0 = Wraparound mode disabled WREN enables or disables wraparound mode. If enabled, the QSPI executes commands in the queue through the command contained in ENDQP. Execution
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continues at either address $0 or at the address found in NEWQP, depending on the state of WRTO. The QSPI continues looping until either WREN is negated, HALT is asserted, or SPE is negated. Once WREN is negated, the QSPI finishes executing commands through the command at the address contained in ENDQP, sets the SPIF flag, and stops. When WREN is set, SPIF is set each time the QSPI transfers the entry indicated by ENDQP. WRTO--Wrap To When wraparound mode is enabled and after the end of queue has been reached, WRTO determines which address the QSPI executes next. End of queue is determined by an address match with ENDQP. Execution wraps to address $0 if WRTO is not set, or to the address found in NEWQP if WRTO is set. Bit 12--Not Implemented ENDQP--Ending Queue Pointer This field determines the last absolute address in the queue to be completed by the QSPI. After completing each command, the QSPI compares the queue pointer value of the just-completed command with the value of ENDQP. If the two values match, the QSPI assumes it has reached the end of the programmed queue and sets the SPIF flag to so indicate. The QSPI RAM queue has 16 entries: $0-$F. The user may program the NEWQP to start executing commands, beginning at any of the 16 addresses. Similarly, the user may program the ENDQP to stop execution of commands at any of the 16 addresses. The queue is a circular data structure. If ENDQP is set to a lower address than NEWQP, the QSPI executes commands through address $F, and then continues execution at address $0 and so on until it stops after executing the command at address ENDQP. A maximum of 16 commands are executed before stopping, unless wraparound mode is enabled or unless the user modifies NEWQP and/or ENDQP. The user may write a NEWQP value at any time, changing the flow of execution. ENDQP may also be written at any time, changing the length of the queue. Wraparound mode may also be enabled, causing continuous execution until the mode is disabled or the QSPI is halted. Bits 7-4--Not Implemented NEWQP--New Queue Pointer Value NEWQP determines which queue entry the QSPI transfers first. NEWQP should be initialized before the QSPI is enabled with SPE. NEWQP may also be written while the QSPI is operating. When this happens, the QSPI completes transfer of the queue entry in progress and then immediately begins transferring queue entries starting with the entry indicated by the NEWQP. In this way, NEWQP provides additional functionality to the QSPI by providing a mechanism for supporting multiple queues or subqueues within the QSPI RAM. By changing the value in NEWQP, the user can cause the QSPI to execute a sequence of
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QSPI commands beginning at any location in the queue. Therefore, the user in advance is able to set up separate subqueues for different tasks within the QSPI RAM. By writing to NEWQP, selection between the different subqueues within the QSPI RAM is accomplished. If wraparound mode is enabled by setting WREN and WRTO in SPCR2, NEWQP assumes an additional function. When the end of the queue is reached, as determined by ENDQP, the address contained in NEWQP is used by the QSPI to wrap around to the first queue entry. The QSPI then re-executes the queued commands repeatedly until halted. 9.5.4.4 QSPI CONTROL REGISTER 3 (SPCR3). SPCR3 contains parameters for configuring the QSPI. The CPU can read and write this register; the QSPM has read-only access. SPCR3
15 0 14 0 13 0 12 0 11 0 10 LOOP Q 9 HMIE 8 HALT XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
$81E
0
RESET: 0 0 0 0 0 0 0 0
Bits 15-11--Not Implemented LOOPQ--QSPI Loop Mode 1 = Feedback path enabled 0 = Feedback path disabled LOOPQ enables or disables the feedback path on the data serializer for testing. If enabled, LOOPQ routes serial output data back into the data serializer, instead of received data. If disabled, LOOPQ allows regular received data into the data serializer. LOOPQ does not affect the QSPI output pins. HMIE--HALTA and MODF Interrupt Enable 1 = HALTA and MODF interrupts enabled 0 = HALTA and MODF interrupts disabled HMIE enables or disables QSPI interrupts to the CPU caused when either the HALTA status flag or the MODF status flag in SPSR is asserted. When HMIE is set, the assertion of either flag causes the QSPI to send a hardware interrupt to the CPU. When HMIE is clear, the asserted flag does not cause an interrupt. HALT--Halt 1 = Halt enabled 0 = Halt not enabled This bit is used by the CPU to stop the QSPI on a queue boundary. The QSPI halts in a known state from which it can later be restarted. When HALT is asserted by the CPU, the QSPI finishes executing the current serial transfer (up to 16 bits) and then halts. While halted, if the command control bit (CONT of the QSPI RAM) for the last command was asserted, the QSPI continues driving the peripheral chip-select pins with the value
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designated by the last command before the halt. If CONT was clear, the QSPI drives the peripheral chip-select pins to the value in QSPM register QPDR. If HALT is asserted during the last command in the queue, the QSPI completes the last command, asserts both HALTA and SPIF, and clears SPE. If the last queue command has not been executed, asserting HALT does not set SPIF nor clear SPE. QSPI execution continues when the CPU clears HALT. 9.5.4.5 QSPI STATUS REGISTER (SPSR). SPSR contains QSPI status information. Only the QSPI can assert the bits in this register. The CPU reads this register to obtain status information and writes this register to clear status flags. CPU writes to CPTQP have no effect. SPSR
15 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX RESET: 0 0 0 0 0 0 0 0 7 SPIF 6 5 4 0 3 2 1 MODF HALTA CPTQP
$81F
0
SPIF--QSPI Finished Flag 1 = QSPI finished 0 = QSPI not finished SPIF is set when the QSPI finishes executing the last command determined by the address contained in ENDQP in SPCR2. When the address of the command being executed matches the ENDQP, the SPIF flag is set after finishing the serial transfer. If wraparound mode is enabled (WREN = 1), the SPIF is set, after completion of the command defined by ENDQP, each time the QSPI cycles through the queue. If SPIFIE in SPCR2 is set, an interrupt is generated when SPIF is asserted. Once SPIF is set, the CPU may clear it by reading SPSR followed by writing SPSR with a zero in SPIF. MODF--Mode Fault Flag 1 = Another SPI node requested to become the network SPI master while the QSPI was enabled in master mode (MSTR = 1), or the PCS0/SS pin was incorrectly pulled low by external hardware. 0 = Normal operation MODF is asserted by the QSPI when the QSPI is the serial master (MSTR = 1) and the slave select (PCS0/SS ) input pin is pulled low by an external driver. This is possible only if the PCS0/SS pin is configured as input by QDDR. This low input to SS is not a normal operating condition. It indicates that a multimaster system conflict may exist, that an external device is requesting to become the SPI network master, or simply that the hardware is incorrectly affecting PCS0/SS. SPE in SPCR1 is cleared, disabling the QSPI. The QSPI pins revert to control by QPDR. If MODF is set and HMIE in SPCR3 is asserted, the QSPI generates an interrupt to the CPU. The CPU may clear MODF by reading SPSR with MODF asserted, followed by writing SPSR with a zero in MODF. After correcting the mode fault problem, the QSPI can be re-enabled by asserting SPE.
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The PCS0/SS pin may be configured as a general-purpose output instead of input to the QSPI. This inhibits the mode fault checking function. In this case, MODF is not used by the QSPI. HALTA--Halt Acknowledge Flag 1 = QSPI halted 0 = QSPI not halted HALTA is asserted by the QSPI when it has come to an orderly halt at the request of the CPU, via the assertion of HALT. To prevent undefined operation, the user should not modify any QSPI control registers or RAM while the QSPI is halted. If HMIE in SPCR3 is set, the QSPI sends interrupt requests to the CPU when HALTA is asserted. The CPU can only clear HALTA by reading SPSR with HALTA set and then writing SPSR with a zero in HALTA. Bit 4--Not Implemented CPTQP--Completed Queue Pointer CPTQP contains the queue pointer value of the last command in the queue that was completed. The value of CPTQP is not updated until the command has been completed entirely. While the first command in a queue is executing, CPTQP contains either the reset value ($0) or the pointer to the last command completed in the previous queue. If the QSPI is halted, CPTQP may be used to determine which commands have not been executed. The CPTQP may also be used to determine which locations in the receive data segment of the QSPI RAM contain valid received data. 9.5.4.6 QSPI RAM. The QSPI uses an 80-byte block of dual-access static RAM, which can be accessed by both the QSPI and the CPU. Because of sharing, the length of time taken by the CPU to access the QSPI RAM, when the QSPI is enabled, may be longer than when the QSPI is disabled. From one to four CPU wait states may be inserted by the QSPI in the process of reading or writing. The size and type of access of the QSPI RAM by the CPU affects the QSPI access time. The QSPI is byte, word, and long-word addressable. Only word accesses of the RAM by the CPU are coherent accesses because these accesses are an indivisible operation. If the CPU makes a coherent access of the QSPI RAM, the QSPI cannot access the QSPI RAM until the CPU is finished. However, a long-word or misaligned word access is not coherent because the CPU must break its access of the QSPI RAM into two parts, which allows the QSPI to access the QSPI RAM in between the two accesses by the CPU. The RAM is divided into three segments: receive data (REC.RAM), transmit data (TRAN.RAM), and command control (COMD.RAM). Receive data is information received from a serial device external to the MC68341. Transmit data is information stored by the CPU for transmission to an external peripheral chip. Command control contains all the information needed by the QSPI to perform the transfer. Figure 9-4 illustrates the organization of the RAM.
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D00
D20
D40
ENTRY 0
REC.RAM
TRAN.RAM
D1E
D3E
D4F
COMD.RAM
F
WORD
WORD
BYTE
Figure 9-4. Organization of the QSPI RAM Once the CPU has set up the queue of QSPI commands and enabled the QSPI, the QSPI operates independently of the CPU. The QSPI executes all of the commands in its queue, sets a flag indicating that it is finished, and then either interrupts the CPU or waits for CPU intervention. 9.5.4.6.1 Receive Data RAM (REC.RAM). This segment of the RAM stores the data that is received by the QSPI from peripherals, SPI bus masters, or other SPI devices. The CPU reads this segment of RAM to retrieve the data from the QSPI. Data stored in receive RAM is right-justified, i.e., the least significant bit is always in the right-most bit position within the word (bit 0) regardless of the serial transfer length. Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry. The CPU can access the data using byte, word, or long-word addressing. The CPTQP value in SPSR shows which queue entries have been executed. The CPU uses this information to determine which locations in receive RAM contain valid data before reading them. 9.5.4.6.2 Transmit Data RAM (TRAN.RAM). This segment of the RAM stores the data that is to be transmitted by the QSPI to peripherals. The CPU normally writes one word of data into this segment for each queue command to be executed. If the corresponding peripheral, such as a serial input port, is used solely to input data, then this segment does not need to be initialized. Information to be transmitted by the QSPI should be written by the CPU to the transmit data segment in a right-justified manner. The information in the transmit data segment of the RAM cannot be modified by the QSPI. The QSPI merely copies the information to its data serializer for transmission to a peripheral. Information in transmit RAM remains there until it is re-written by the CPU. 9.5.4.6.3 Command RAM (COMD.RAM). The command segment of the QSPI RAM is used only by the QSPI when it is in master mode. The CPU writes one byte of control information to this segment for each QSPI command to be executed. The information in the command RAM cannot be modified by the QSPI. It merely uses the information to perform the serial transfer.
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COMD.RAM consists of 16 bytes. Each byte is divided into two fields. The first, the peripheral chip-select field, activates the correct serial peripheral during the transfer. The second, the command control field, provides transfer options specifically for that command/serial transfer. This feature gives the user more control over each transfer, providing the flexibility to interface to external SPI chips with different requirements (refer to Figure 9-5). A maximum of 16 commands can be in the queue command control bytes. These bytes are assigned an address from $0-$F. Queue execution by the QSPI proceeds from the address contained in NEWQP through the address contained in ENDQP. Both of these fields are contained in SPCR2. COMD.RAM--Command RAM
7 CONT 6 BITSE 5 DT 4 DSCK 3 RSVD 2 RSVD 1 PCS1
$940
0 PCS0 *
--
--
--
--
--
--
--
--
CONT
BITSE
DT
DSCK
RSVD
RSVD
PCS1
PCS0 *
$94F
COMMAND CONTROL PERIPHERAL CHIP SELECT
*The PCS0 bit represents the dual-function PCS0/SS .
Figure 9-5. Command RAM
CONT--Continue 1 = Keep peripheral chip selects asserted after transfer is complete. 0 = Return control of peripheral chip selects to QPDR after transfer is complete. Some peripheral chips must be deselected between every QSPI transfer. Other chips must remain selected between several sequential serial transfers. CONT is designed to provide the flexibility needed to handle both cases. If CONT = 1 and the peripheral-chip-select pattern for the next command is the same as that of the present command, the QSPI drives the PCS pins to the same value continuously during the two serial transfers. An unlimited number of serial transfers may be sent to the same peripheral(s) without deselecting it (them) by setting CONT = 1. If CONT = 1 and the peripheral-chip-select pattern for the next command is different from that of the present command, the QSPI drives the PCS pins to the new value for the second serial transfer. Although this case is similar to CONT = 0, a difference remains. When CONT = 1, the QSPI continues to drive the PSC pins using the pattern from the first transfer until it switches to using the pattern for the second transfer. When CONT = 0, the QSPI drives the PCS pins to the values found in register QPDR between serial transfers. BITSE--Bits Per Transfer Enable 1 = Number of bits set in BITS field of SPCR0
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0 = 8 bits DT -- Delay After Transfer A/D converters require a known amount of time to perform a conversion. The conversion time for serial CMOS A/D converters may range from 1-100 s. To facilitate interfacing to peripherals with a latency requirement, the QSPI provides a programmable delay at the end of the serial transfer, with the DT field. The user may avoid using this delay option by executing transfers with other peripheral devices in between transfers with the peripheral that requires a delay. This interleaved operation improves the effective serial transfer rate. The amount of the delay between transfers is programmable by the user via the DTL field in SPCR1. The range may be set from 1-489 s at 16.78 MHz. DSCK -- PCS to SCK Delay 1 = DSCKL field in SPCR1 specifies value of delay from PCS valid to SCK. 0 = PCS valid to SCK transition is 1/2 SCK. PCS1-PCS0/SS--Peripheral Chip Select The two peripheral chip-select bits can be used directly to select one of two external chips for the serial transfer, or decoded by external hardware to select one of four chipselect patterns for the serial transfer. More than one peripheral chip select may be activated at a time, which is useful for broadcast messages in a multinode SPI system. More than one peripheral chip may be connected to each PCS pin. Care must be taken by the system designer not to exceed the maximum drive capability of the pins as defined in Section 12 Electrical Characteristics for QSPM pins. QSPM register QPDR determines the state of the PCS pins when the QSPI is disabled, and also determines the state of PCS pins that are not assigned to the QSPI when the QSPI is enabled. QPDR determines the state of pins assigned to the QSPI between transfers as well. To use a peripheral chip-select pin, the CPU assigns the pin to the QSPI in QPAR by writing a one to the appropriate bit. The default value of the PCS pin should be written to QPDR. Next, the pin must be defined as an output in QDDR by setting the appropriate bit, which causes the pin to start driving the default value. The QSPI RAM may then be initialized for a serial transmission, with the peripheralchip-select bits of the command control byte appropriately configured to activate the desired PCS pin(s) during the serial transfer. When the command is executed, the PCS pin(s) are driven to the values contained in the appropriate control byte. After completing the serial transfer, the QSPI returns control of the peripheral-chip-select signal(s) (if CONT = 0 in the command control byte) to register QPDR.
9.5.5 Operating Modes and Flowcharts
The QSPI utilizes an 80-byte block of dual-access static RAM accessible by both the QSPI and the CPU. The RAM is divided into three segments: 16 command control bytes, 16 transmit data words of information to be transmitted, and 16 receive data words for data to be received. Once the CPU has a) set up a queue of QSPI commands, b) written
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the transmit data segment with information to be sent, and c) enabled the QSPI, the QSPI operates independently of the CPU. The QSPI executes all of the commands in its queue, sets a flag indicating completion, and then either interrupts the CPU or waits for CPU intervention. The QSPI operates on a queue data structure contained in the QSPI RAM. Control of the queue is handled by three pointers: the new queue pointer (NEWQP), the completed queue pointer (CPTQP), and the end queue pointer (ENDQP). NEWQP, contained in SPCR2, points to the first command in the queue to be executed by the QSPI. CPTQP, contained in SPSR, points to the command last executed by the QSPI. ENDQP, also contained in SPCR2, points to the last command in the queue to be executed by the QSPI, unless wraparound mode is enabled (WREN = 1). At reset, NEWQP is initialized to $0, causing QSPI execution to begin at queue address $0 when the QSPI is enabled (SPE = 1). CPTQP is set by the QSPI to the queue address ($0-$F) last executed, but is initialized to $0 at reset. ENDQP is also initialized to $0 at reset, but should be changed by the user to reflect the last queue entry to be transferred before enabling the QSPI. Leaving NEWQP and ENDQP set to $0 causes a single transfer to occur when the QSPI is enabled. The organization of the QSPI RAM defines that one byte of command control data, one word of transmit data, and one word of receive data all correspond to one queue entry, $0$F. After executing the current command, ENDQP is checked against CPTQP for an end-ofqueue condition. If a match occurs, the SPIF flag is set and the QSPI stops unless wraparound mode is enabled. The QSPI operates in one of two modes: master or slave. Master mode is used when the MC68341 originates all data transfers. Slave mode is used when another device or a peripheral to the MC68341 initiates all serial transfers to the MC68341 via the QSPI. Switching between the two operating modes is achieved under software control by writing to the master (MSTR) bit in SPCR0. In master mode, the QSPI executes the queue of commands as defined by the control bits in each entry. Chip-select pins are activated; data is transmitted, received, and placed in the QSPI RAM. In slave mode, a similar operation occurs in response to the slave select (SS) pin activated by an external SPI bus master. The primary differences are a) no peripheral chip selects are generated, and b) the number of bits transferred is controlled in a different manner. When the QSPI is selected, it executes the next queue transfer to correctly exchange data with the external device. The following flowcharts, Figures 9-6-9-8, outline the operation of the QSPI for both master and slave modes. Note that the CPU must initialize the QSPM global and pin registers and the QSPI control registers before enabling the QSPI for either master or slave operation. If using master mode, the necessary command control RAM should also
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be written before enabling the QSPI. Any data to be transmitted should also be written before the QSPI is enabled. When wrap mode is used, data for subsequent transmissions may be written at any time.
BEGIN
CPU INITIALIZES QSM GLOBAL REGISTERS
CPU INITIALIZES QSM PIN REGISTERS
INITIALIZATION OF QSPI BY THE CPU CPU INITIALIZES QSPI CONTROL REGISTERS
CPU INITIALIZES QSPI RAM
CPU ENABLES QSPI
A (PROCEED TO FIGURE 9-7 FOR MASTER MODE OR TO FIGURE 9-8 FOR SLAVE MODE)
Figure 9-6. Flowchart of QSPI Initialization Operation
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QSPI CYCLE BEGINS A
IS QSPI DISABLED
Y
N
HAS NEWQP BEEN WRITTEN
Y
QUEUE POINTER CHANGED TO NEWQP
N READ COMMAND CONTROL AND TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS
ASSERT PERIPHERAL CHIP SELECT(S)
IS PCS TO SCK DELAY PROGRAMMED
Y EXECUTE PROGRAMMED DELAY
N EXECUTE STANDARD DELAY
EXECUTE SERIAL TRANSFER
STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS
B
Figure 9-7. Flowchart of QSPI Master Operation (1 of 3)
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B
WRITE QUEUE POINTER TO CPTQP STATUS BITS
IS CONTINUE BIT ASSERTED
Y
N NEGATE PERIPHERAL CHIP SELECT(S)
IS DELAY AFTER TRANSFER ASSERTED N
Y
EXECUTE PROGRAMMED DELAY
EXECUTE STANDARD DELAY
C (CONTINUED ON NEXT PAGE)
Figure 9-7. Flowchart of QSPI Master Operation (2 of 3)
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C
IS THIS THE LAST COMMAND IN THE QUEUE N
Y
ASSERT SPIF STATUS FLAG
IS INTERRUPT ENABLE BIT SPIFIE ASSERTED
Y
INTERRUPT CPU
N
INCREMENT QUEUE POINTER
IS WRAP ENABLE BIT ASSERTED N DISABLE QSPI
Y
RESET QUEUE POINTER TO NEWQP OR $0000
A (PROCEED TO FIGURE 9-7)
IS HALT OR FREEZE ASSERTED
Y
HALT QSPI AND ASSERT HALTA
N IS INTERRUPT ENABLE BIT HMIE ASSERTED Y INTERRUPT CPU
N
IS HALT OR FREEZE ASSERTED
Y
N
A (PROCEED TO FIGURE 9-7)
Figure 9-7. Flowchart of QSPI Master Operation (3 of 3)
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QSPI CYCLE BEGINS A
IS QSPI DISABLED N
Y
HAS NEWQP BEEN WRITTEN
Y
QUEUE POINTER CHANGED TO NEWQP
N
READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS
IS SLAVE SELECT PIN ASSERTED N
Y
EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED
STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS
WRITE QUEUE POINTER TO CPTQP STATUS BITS
B
Figure 9-8. Flowchart of QSPI Slave Operation (1 of 2)
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B
IS THIS THE LAST COMMAND IN THE QUEUE N
Y
ASSERT SPIF STATUS FLAG
IS INTERRUPT ENABLE BIT SPIFIE ASSERTED
Y
INTERRUPT CPU
N
INCREMENT QUEUE POINTER
IS WRAP ENABLE BIT ASSERTED N DISABLE QSPI
Y
RESET QUEUE POINTER TO NEWQP OR $0000
A (PROCEED TO FIGURE 9-8, PART 1)
IS HALT OR FREEZE ASSERTED N
Y
HALT QSPI AND ASSERT HALTA
IS INTERRUPT ENABLE BIT HMIE ASSERTED
Y
INTERRUPT CPU
N
IS HALT OR FREEZE ASSERTED N
Y
A
Figure 9-8. Flowchart of QSPI Slave Operation (2 of 2) Although the QSPI inherently supports multimaster operation, no special arbitration mechanism is provided. The user is given a mode fault flag (MODF) to indicate a request
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for SPI master arbitration; however, the system software must implement the arbitration. Note that unlike previous SPI systems, e.g., on the M68HC11 Family, MSTR is not cleared by a mode fault being set nor are the QSPI pin output drivers disabled; however, the QSPI is disabled when software clears SPE in QSPI register SPCR1. Normally, the SPI bus performs simultaneous bidirectional synchronous transfers. The serial clock on the SPI bus master supplies the clock signal (SCK) to time the transfer of the bits. Four possible combinations of clock phase and polarity may be employed. Data is transferred with the most significant bit first. The number of bits transferred per command defaults to eight, but may be programmed to a value from 8-16 bits, using the BITSE field. Typically, outputs used for the SPI bus are not open drain unless multiple SPI masters are in the system. If needed, WOMQ in S PCR0 may be set to provide open-drain outputs. An external pullup resistor should be used on each output bus line. WOMQ affects all QSPI pins regardless of whether they are assigned to the QSPI or used as general-purpose I/O. 9.5.5.1 MASTER MODE. When operated in master mode, the QSPI may initiate serial transfers. The QSPI is unable to respond to any externally initiated serial transfers. QSPM register QDDR should be written to direct the data flow on the QSPI pins used. The SCK pin should be configured as an output. Pins MOSI, PCS1/SS, and PCS0 should be configured as outputs as necessary. MISO should be configured as an input if necessary. QSPM register QPAR should be written to assign the necessary bits to the QSPI. The pins necessary for master mode operation are MISO and/or MOSI, SCK, and one or more of the PCS pins, depending on the number of external peripheral chips to be selected. MISO is used as the data input pin in master mode, and MOSI is used as the data output pin in master mode. Either or both may be necessary, depending on the particular application. SCK is the serial clock output in master mode. PCS1/SS and PCS0 are the select pins used to select external SPI peripheral chips for a serial transfer initiated by the QSPI. These pins operate as either active-high or active-low chip selects. Other considerations for initialization are prescribed in 9.4.1 Overall QSPM Configuration Summary. 9.5.5.1.1 Master Mode Operation. After reset, the QSPM registers and the QSPI control registers must be initialized as described above. In addition to the command control segment, the transmit data segment may, depending upon the application, need to be initialized. If meaningful data is to be sent out from the QSPI, the user should write the data to the transmit data segment before enabling the QSPI. Shortly after SPE is set, the QSPI commences operation at the address indicated by NEWQP. The QSPI transmits the data found in the transmit data segment at the address indicated by NEWQP, and the QSPI stores received data in the receive data segment at the address indicated by NEWQP. Data is transferred synchronously with the internally generated SCK.
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Transmit data is loaded into the data serializer (refer to 9.5.4.4 QSPI Control Register 3 (SPCR3)). The QSPI employs control bits, CPHA and CPOL, to determine which SCK edge the MISO pin uses to latch incoming data and which edge the MOSI pin uses to start driving the outgoing data. SPBR of SPCR0 determines the baud rate of SCK. DSCK and DSCKL determine any peripheral chip selects valid to SCK start delay. The number of bits transferred is determined by BITSE and BITS fields. Two options are available: the user may use the default value of 8 bits, or the user may program the length from 8-16 bits, inclusive. Once the proper number of bits are transferred, the QSPI stores the received data in the receive data segment, stores the internal working queue pointer value in CPTQP, increments the internal working queue pointer, and loads the next data required for transfer from the queue. The internal working queue pointer address is the next command executed unless the CPU writes a new value first. If CONT is set and the peripheral-chip-select pattern does not change between the current and the pending transfer, the PCS pins are continuously driven in their designated state during and between both serial transfers. If the peripheral-chip-select pattern changes, then the first pattern is driven out during execution of the first transfer, followed by the QSPI switching to the next pattern of the second transfer when execution of the second transfer begins. If CONT is clear, the deselected peripheral-chip-select values (found in register QPDR) are driven out between transfers. DT causes a delay to occur after the specified serial transfer is completed. The length of the delay is determined by DTL. When DT is clear, the standard delay (1 s at a 16.78MHz system clock) occurs after the specified serial transfer is completed. 9.5.5.1.2 Master Wraparound Mode. When the QSPI reaches the end of the queue, it always sets the SPIF flag whether wraparound mode is enabled or disabled. An optional interrupt to the CPU is generated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wraparound mode is enabled. A description of SPIFIE may be found in 9.5.4.3 QSPI Control Register 2 (SPCR2). In wraparound mode, the QSPI cycles through the queue continuously. Each time the end of the queue is reached, the SPIF flag is set. If the CPU fails to clear SPIF it remains set, and the QSPI continues to send interrupt requests to the CPU (assuming SPIFIE is set). The user may avoid causing CPU interrupts by clearing SPIFIE. As SPIFIE is buffered, clearing it after the SPIF flag is asserted does not immediately stop the CPU interrupts, but only prevents future interrupts from this source. To clear the current interrupt, the CPU must read QSPI register SPSR with SPIF asserted, followed by a write to SPSR with a zero in SPIF (clear SPIF). Execution continues in wraparound mode, even while the QSPI is requesting interrupt service from the CPU. The internal working queue pointer increments to the next address, and the commands are executed again. SPE is not cleared by the QSPI. New receive data overwrites previously received data in the receive data segment.
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Wraparound mode is properly exited in two ways: a) The CPU may disable wraparound mode by clearing WREN. The next time the end of the queue is reached, the QSPI sets SPIF, clears SPE, and stops; b) The CPU sets HALT. This second method halts the QSPI after the current transfer is completed, allowing the CPU to negate SPE. The CPU can immediately stop the QSPI by clearing SPE; however, this method is not recommended as it causes the QSPI to abort a serial transfer in process. 9.5.5.2 SLAVE MODE. When operating in slave mode, the QSPI may respond to externally initiated serial transfers. The QSPI is unable to initiate any serial transfers. Slave mode is typically used when multiple devices are in an SPI bus network, because only one device can be the SPI master (in master mode) at any given time. QSPM register QDDR should be written to direct data flow on the QSPI pins used. The MISO and MOSI pins, if needed, should be configured as output and input, respectively. Pins SCK and PCS0/SS should be configured as inputs. QSPM register QPAR should be written to assign the necessary bits to the QSPI. The pins necessary for slave mode operation are MISO and/or MOSI, SCK, and PCS0/SS. MISO is the data output pin in slave mode, and MOSI is the data input pin in slave mode. Either or both may be necessary depending on the particular application. The serial clock (SCK) is the slave clock input in slave mode. PCS0/SS is the slave select pin used to select the QSPI for a serial transfer by the external SPI bus master when the QSPI is in slave mode. The external bus master selects the QSPI by driving PCS0/SS low. The command control segment is not implemented in slave mode; therefore, the CPU does not need to initialize it. This segment of the QSPI RAM and any other unused segments may be employed by the CPU as general-purpose RAM. Other considerations for initialization are prescribed in 9.4.1 Overall QSPM Configuration Summary. 9.5.5.2.1 Description of Slave Operation. After reset, the QSPM registers and the QSPI control registers must be initialized as described above. Although the command control segment is not used, the transmit and receive data segments may, depending upon the application, need to be initialized. If meaningful data is to be sent out from the QSPI, the user should write the data to the transmit data segment before enabling the QSPI. If SPE is set and MSTR is not set, a low state on the slave select (PCS0/SS) pin commences slave mode operation at the address indicated by NEWQP. The QSPI transmits the data found in the transmit data segment at the address indicated by NEWQP, and the QSPI stores received data in the receive data segment at the address indicated by NEWQP. Data is transferred in response to an external slave clock input at the SCK pin. Because the command control segment is not used, the command control bits and peripheral-chip-select codes have no effect in slave mode operation. The QSPI does not drive either of the two peripheral chip selects as outputs. PCS0/SS is used as an input. Although CONT cannot be used in slave mode, a provision is made to enable receipt of more than 16 data bits. While keeping the QSPI selected (PCS0/ SS is held low), the QSPI stores the number of bits, designated by BITS, in the current receive data segment
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address, increments NEWQP, and continues storing the remaining bits (up to the BITS value) in the next receive data segment address. As long as PCS0/SS remains low, the QSPI continues to store the incoming bit stream in sequential receive data segment addresses, until either the value in BITS is reached or the end-of-queue address is used with wraparound mode disabled. When the end of the queue is reached, the SPIF flag is asserted, optionally causing an interrupt. If wraparound mode is disabled, any additional incoming bits are ignored. If wraparound mode is enabled, storing continues at either address $0 or the address of NEWQP, depending on the WRTO value. When using this capability to receive a long incoming data stream, the proper delay between transfers must be used. The QSPI requires time, approximately 1 s at 16.78MHz system clock, to prefetch the next transmit RAM entry for the next transfer. Therefore, the user may select a baud rate that provides at least a 1 s delay between successive transfers to ensure no loss of incoming data. If the system clock is operating at a slower rate, the delay between transfers must be increased proportionately. Because the BITSE option in the command control segment is no longer available, BITS sets the number of bits to be transferred for all transfers in the queue until the CPU changes the BITS value. As mentioned above, until PCS0/SS is negated (brought high), the QSPI continues to shift one bit for each pulse of SCK. If PCS0/SS is negated before the proper number of bits (according to BITS) is received, the QSPI, the next time it is selected, resumes storing bits in the same receive data segment address where it left off. If more than 16 bits are transferred before negating the PCS0/SS, the QSPI stores the number of bits indicated by BITS in the current receive data segment address, then increments the address and continues storing as described above. Note that PCS0/ SS does not necessarily have to be negated between transfers. Once the proper number of bits (designated by BITS) are transferred, the QSPI stores the received data in the receive data segment, stores the internal working queue pointer value in CPTQP, increments the internal working queue pointer, and loads the new transmit data from the transmit data segment into the data serializer. The internal working queue pointer address is used the next time PCS0/SS is asserted, unless the CPU writes to the NEWQP first. The DT and DSCK command control bits are not used in slave mode. As a slave, the QSPI does not drive the clock line nor the chip-select lines and, therefore, does not generate a delay. In slave mode, the QSPI shifts out the data in the transmit data segment. The transmit data is loaded into the data serializer (refer to Figure 9-9) for transmission. This serializer shifts the 16 bits of data out in sequence, most significant bit first, as clocked by the incoming SCK signal. The QSPI uses CPHA and CPOL to determine which incoming SCK edge the MOSI pin uses to latch incoming data, and which edge the MISO pin uses to drive the data out.
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The QSPI transmits and receives data until reaching the end of the queue (defined as a match with the address in ENDQP), regardless of whether PCS0/SS remains selected or is toggled between serial transfers. Receiving the proper number of bits causes the received data to be stored. The QSPI always transmits as many bits as it receives at each queue address, until the BITS value is reached or PCS0/SS is negated. 9.5.5.2.2 Slave Wraparound Mode. When the QSPI reaches the end of the queue, it always sets the SPIF flag, whether wraparound mode is enabled or disabled. An optional interrupt to the CPU is generated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wraparound mode is enabled. A description of SPIFIE bit can be found in 9.5.4.3 QSPI Control Register 2 (SPCR2). In wraparound mode, the QSPI cycles through the queue continuously. Each time the end of the queue is reached, the SPIF flag is set. If the CPU fails to clear SPIF, it remains set, and the QSPI continues to send interrupt requests to the CPU (assuming SPIFIE is set). The user may avoid causing CPU interrupts by clearing SPIFIE. As SPIFIE is buffered, clearing it after the SPIF flag is asserted does not immediately stop the CPU interrupts, but only prevents future interrupts from this source. To clear the current interrupt, the CPU must read QSPI register SPSR with SPIF asserted, followed by a write to SPSR with zero in SPIF (clear SPIF). Execution continues in wraparound mode even while the QSPI is requesting interrupt service from the CPU. The internal working queue pointer is incremented to the next address and the commands are executed again. SPE is not cleared by the QSPI. New receive data overwrites previously received data located in the receive-data segment. Wraparound mode is properly exited in two ways: a) The CPU may disable wraparound mode by clearing WREN. The next time end of the queue is reached, the QSPI sets SPIF, clears SPE, and stops; and, b) The CPU sets HALT. This second method halts the QSPI after the current transfer is completed, allowing the CPU to negate SPE. The CPU can immediately stop the QSPI by clearing SPE; however, this method is not recommended, as it causes the QSPI to abort a serial transfer in process.
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SECTION 10 IEEE 1149.1 TEST ACCESS PORT
The MC68341 includes dedicated user-accessible test logic that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The MC68341 implementation supports circuit-board test strategies based on this standard. The test logic includes a test access port (TAP) consisting of four dedicated signal pins, a 16-state controller, an instruction register, and two test data registers. A boundary scan register links all device signal pins into a single shift register. The test logic, implemented using static logic design, is independent of the device system logic. The MC68341 implementation provides the following capabilities: a. Perform boundary scan operations to test circuit-board electrical continuity b. Sample the MC68341 system pins during operation and transparently shift out the result in the boundary scan register c. Bypass the MC68341 for a given circuit-board test by effectively reducing the boundary scan register to a single bit d. Disable the output drive to pins during circuit-board testing NOTE Certain precautions must be observed to ensure that the IEEE 1149.1 test logic does not interfere with nontest operation. See 10.6 Non-IEEE 1149.1 Operation for details.
10.1 OVERVIEW
NOTE This description is not intended to be used without the supporting IEEE 1149.1 document. The discussion includes those items required by the standard and provides additional information specific to the MC68341 implementation. For internal details and applications of the standard, refer to the IEEE 1149.1 document.
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An overview of the MC68341 implementation of IEEE 1149.1 is shown in Figure 10-1. The MC68341 implementation includes a 16-state controller, a 3-bit instruction register, and two test registers (a 1-bit bypass register and a 155-bit boundary scan register). This implementation includes a dedicated TAP consisting of the following signals: TCK -- TMS -- a test clock input to synchronize the test logic a test mode select input (with an internal pullup resistor) that is sampled on the rising edge of TCK to sequence the TAP controller's state machine TDI -- a test data input (with an internal pullup resistor) that is sampled on the rising edge of TCK. TDO -- a three-state test data output that is actively driven in the shift-IR and shiftDR controller states. TDO changes on the falling edge of TCK.
TEST DATA REGISTERS 154 BOUNDARY SCAN REGISTER (155 BITS) TDI M U X BYPASS 0
DECODER M U X
2 3-BIT INSTRUCTION REGISTER
0
TDO
TMS TCK TAP CTLR
Figure 10-1. Test Access Port Block Diagram
10.2 TAP CONTROLLER
The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is a synchronous state machine that controls the operation of the JTAG logic. The state machine is shown in Figure 10-2; the value shown adjacent to each arc represents the value of the TMS signal sampled on the rising edge of the TCK signal. For a description of the TAP controller states, please refer to the IEEE 1149.1 document.
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1
TEST LOGIC RESET 0 1
0
RUN-TEST/IDLE
SELECT-DR_SCAN 0
1
1
1 SELECT-IR_SCAN 0
1
CAPTURE-DR 0 SHIFT-DR 1 1 0
CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0
0
EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1
0
PAUSE-IR 1
0
0
EXIT2-IR 1
UPDATE-DR 1 0
1
UPDATE -IR
0
Figure 10-2. TAP Controller State Machine
10.3 BOUNDARY SCAN REGISTER
The MC68341 IEEE 1149.1 implementation has a 155-bit boundary scan register. This register contains bits for all device signal and clock pins and associated control signals. The XTAL, X2, XFC, BSW, EXTAL, and VBATT pins are associated with analog signals and are not included in the boundary scan register. All MC68341 bidirectional pins, except the open-drain I/O pins (DONE1, DONE2, HALT, and RESET) and QSM pins (QSCLK, MISO, MOSI, PCS1, PCS0 ) have a single register bit for pin data and an associated control bit in the boundary scan register. All open drain I/O and QSM pins have two register bits, input and output, for pin data and no associated control bit. To ensure proper operation, the open-drain pins require external pullups. Twenty-seven control bits in the boundary scan register define the output enable signal for
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associated groups of bidirectional and three-state pins. The control bits and their bit positions are listed in Table 10-1. Table 10-1. Boundary Scan Control Bits
Name ifetch.ctl modck.ctl irq1.ctl irq2.ctl irq3.ctl irq4.ctl irq5.ctl irq6.ctl irq7.ctl Bit Number 152 149 131 129 127 125 123 121 119 Name ab31.ctl ab30.ctl ab29.ctl ab28.ctl ab27.ctl ab26.ctl ab25.ctl ab24.ctl db.ctl Bit Number 114 112 110 108 106 104 102 100 98 Name berr.ctl ab.ctl cs0.ctl tout.ctl pcs0.ctl pcs1.ctl miso.ctl mosi.ctl sck.ctl Bit Number 97 96 74 44 14 11 8 5 2
Boundary scan bit definitions are shown in Table 10-2. The first column in Table 10-2 defines the bit's ordinal position in the boundary scan register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 0; the last bit to be shifted out is 154. The second column references one of the five MC68341 cell types depicted in Figures 10-3-10-7, which describe the cell structure for each type. The third column lists the pin name for all pin-related bits or defines the name of bidirectional control register bits. The active level of the control bits (i.e., output driver on) is defined by the last digit of the cell type listed for each control bit. For example, the active level for irq2.ctl (bit 129) is logic zero since the cell type is IO.Ctl0. The active level for ab.ctl (bit 96) is logic one, since the cell type is IO.Ctl1. IO.Ctl0 (see Figure 10-6) differs from IO.Ctl1 (see Figure 10-5) by an inverter in the output enable path. The fourth column lists the pin type: TS-Output indicates a three-state output pin, I/O indicates a bidirectional pin, and OD-I/O denotes an open-drain bidirectional pin. An opendrain output pin has two states: off (high impedance) and logic zero. The last column indicates the associated boundary scan register control bit for bidirectional, three-state, and open-drain output pins. Bidirectional pins include a single scan bit for data (IO.Cell) as depicted in Figure 10-7. These bits are controlled by one of the two bits shown in Figures 10-5 and 10-6. The value of the control bit determines whether the bidirectional pin is an input or an output. One or more bidirectional data bits can be serially connected to a control bit as shown in Figure 10-8. Note that, when sampling the bidirectional data bits, the bit data can be interpreted only after examining the IO control bit to determine pin direction.
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Table 10-2. Boundary Scan Bit Definitions
Bit Num 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 Cell Type O.Latch I.Pin IO.Ctl0 IO.Cell O.Latch IO.Ctl0 IO.Cell I.pin O.Latch I.Pin O.Latch I.Pin O.Latch IO.Cell I.pin O.Latch I.Pin IO.Cell IO.Cell IO.Cell IO.Cell IO.Cell O.Latch IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell Pin/Cell Name FREEZE BKPT ifetch.ctl IFETCH IPIPE modck.ctl MODCK SEXTCLK CLKOUT RESET RESET HALT HALT BERR BR BG BGACK AS DS SIZ0 SIZ1 R/ W RMC irq1.ctl IRQ1 irq2.ctl IRQ2 irq3.ctl IRQ3 irq4.ctl IRQ4 irq5.ctl IRQ5 irq6.ctl IRQ6 Pin Type Output Input -- I/O* Output -- I/O Input Output OD-I/O OD-I/O OD-I/O OD-I/O I/O** Input Output Input I/O* I/O* I/O* I/O* I/O* TS-Output -- I/O -- I/O -- I/O -- I/O -- I/O -- I/O Output CTL Cell -- -- -- ifetch.ctl -- -- modck.ctl -- -- -- -- -- -- berr.ctl -- -- -- ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl -- irq1.ctl -- irq2.ctl -- irq3.ctl -- irq4.ctl -- irq5.ctl -- irq6.ctl Bit Num 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 Cell Type IO.Ctl0 IO.Cell IO.Cell IO.Cell IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl0 IO.Cell IO.Ctl1 IO.Ctl0 IO.Ctl1 IO.Cell IO.Cell IO.Cell IO.Cell IO.Cell IO.Cell IO.Cell IO.Cell IO.Cell IO.Cell IO.Cell Pin/Cell Name irq7.ctl IRQ7 DSACK1 DSACK0 A0 ab31.ctl A31 ab30.ctl A30 ab29.ctl A29 ab28.ctl A28 ab27.ctl A27 ab26.ctl A26 ab25.ctl A25 ab24.ctl A24 db.ctl berr.ctl ab.ctl D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Pin Type -- I/O I/O** I/O** I/O* -- I/O -- I/O -- I/O -- I/O -- I/O -- I/O -- I/O -- I/O -- -- -- I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output CTL Cell -- irq7.ctl berr.ctl berr.ctl ab.ctl -- ab31.ctl -- ab30.ctl -- ab29.ctl -- ab28.ctl -- ab27.ctl -- ab26.ctl -- ab25.ctl -- ab24.ctl -- -- -- db.ctl db.ctl db.ctl db.ctl db.ctl db.ctl db.ctl db.ctl db.ctl db.ctl db.ctl
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Table 10-2. Boundary Scan Bit Definitions (Continued)
Bit Num 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 Cell Type IO.Cell IO.Cell IO.Cell IO.Cell IO.Cell O.Latch O.Latch O.Latch O.Latch O.Latch IO.Ctl0 IO.Cell O.Latch O.Latch O.Latch O.Latch O.Latch O.Latch O.Latch I.Pin O.Latch O.Latch I.Pin I.Pin O.Latch O.Latch I.Pin I.Pin I.Pin I.Pin O.Latch O.Latch I.Pin O.Latch O.Latch Pin/Cell Name D4 D3 D2 D1 D0 68KAS LWE UWE LDS UDS cs0.ctl CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 DONE2 DONE2 DACK2 DREQ2 DONE1 DONE1 DACK1 DREQ1 X1 SCLK CTSB RTSB TxDB RxDB TRDYA RRDYA Pin Type I/O I/O I/O I/O I/O TS-Output TS-Output TS-Output TS-Output TS-Output -- I/O* TS-Output TS-Output TS-Output TS-Output TS-Output TS-Output TS-Output OD-I/O OD-I/O Output Input OD-I/O OD-I/O Output Input Input Input Input Output Output Input Output Output Output CTL Cell db.ctl db.ctl db.ctl db.ctl db.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl -- cs0.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit Num 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Cell Type I.Pin O.Latch O.Latch I.Pin I.Pin IO.ctl0 O.Latch I.Pin IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell IO.cell Pin/Cell Name CTSA RTSA TxDA RxDA TIN tout.ctl TOUT TGATE A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 FC0 FC1 FC2 FC3 Pin Type Input Output Output Input Input -- TS-Output Input I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* Output CTL Cell -- -- -- -- -- -- tout.ctl -- ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl ab.ctl
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Table 10-2. Boundary Scan Bit Definitions (Continued)
Bit Num 14 13 12 11 10 9 8 7 Cell Type IO.ctl0 I.Pin O.Latch IO.ctl0 I.Pin O.Latch IO.ctl0 I.Pin Pin/Cell Name pcs0.ctl PCS0 PCS0 pcs1.ctl PCS1 PCS1 miso.ctl MISO Pin Type -- I/O I/O -- I/O I/O -- I/O Output CTL Cell -- -- pcs0.ctl -- -- pcs1.ctl -- -- Bit Num 6 5 4 3 2 1 0 Cell Type O.Latch IO.ctl0 I.Pin O.Latch IO.ctl0 I.Pin O.Latch Pin/Cell Name MISO mosi.ctl MOSI MOSI sck.ctl SCK SCK Pin Type I/O -- I/O I/O -- I/O I/O Output CTL Cell miso.ctl -- -- mosi.ctl -- -- sck.ctl
NOTES: The noted pins are implemented differently than defined in the signal definition description: * Input during Motorola factory test ** Output during Motorola factory test
1 - EXTEST 0 - OTHERWISE
SHIFT DR
TO NEXT CELL
G1 DATA FROM SYSTEM LOGIC 1 MUX 1 TO OUTPUT BUFFER
G1 1 MUX 1
1D C1 1D C1
FROM LAST CELL
CLOCK DR
UPDATE DR
Figure 10-3. Output Latch Cell (O.Latch)
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1 - EXTEST 0 - OTHERWISE
TO NEXT CELL
G1 1 MUX 1 G1 1 1D C1 1D C1 MUX 1 INPUT PIN
UPDATE DR
CLOCK DR
FROM LAST CELL
SHIFT DR
Figure 10-4. Input Pin Cell (I.Pin)
1 - EXTEST 0 - OTHERWISE G1 OUTPUT CONTROL FROM SYSTEM LOGIC 1 MUX 1
TO NEXT CELL
TO OUTPUT ENABLE (1 = DRIVE)
G1 1 MUX 1
1D C1 1D C1 R
SHIFT DR
FROM LAST CELL
CLOCK DR
RESET UPDATE DR
Figure 10-5. Active-High Output Control Cell (IO.Ctl1)
FIG. 9-4
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1 - EXTEST 0 - OTHERWISE OUTPUT CONTROL FROM SYSTEM LOGIC G1 1 MUX 1
TO NEXT CELL
TO OUTPUT ENABLE (1 = DRIVE)
G1 1 MUX 1
1D C1 1D C1 R
SHIFT DR
FROM LAST CELL
CLOCK DR
RESET UPDATE DR
Figure 10-6. Active-Low Output Control Cell (IO.Ctl0)
1 - EXTEST 0 - OTHERWISE OUTPUT FROM SYSTEM LOGIC G1 1 MUX 1
SHIFT DR
TO NEXT CELL
TO OUTPUT DRIVER
G1 1 MUX 1
G1 1 MUX 1
1D C1 1D C1
FROM OUTPUT ENABLE
FROM PIN
FROM LAST CELL
CLOCK DR
UPDATE DR
Figure 10-7. Bidirectional Data Cell (IO.Cell)
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TO NEXT CELL
OUTPUT ENABLE
IO.CTL0 OR IO.CTL1
*
OUTPUT DATA IO.CELL INPUT DATA
EN I/O PIN
FROM LAST CELL TO NEXT BIDIRECTIONAL PIN NOTE: More than one lO.Cell could be serially connected and controlled by a single IO.Ctlx cell.
Figure 10-8. General Arrangement for Bidirectional Pins
10.4 INSTRUCTION REGISTER
The MC68341 IEEE 1149.1 implementation includes the three mandatory public instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS), but does not support any of the optional public instructions defined by IEEE 1149.1. One additional public instruction (HI-Z) provides the capability for disabling all device output drivers. The MC68341 includes a 3-bit instruction register without parity, consisting of a shift register with three parallel outputs. Data is transferred from the shift register to the parallel outputs during the update-IR controller state. The three bits are used to decode the four unique instructions listed in Table 10-3. The parallel output of the instruction register is reset to all ones in the test-logic-reset controller state. Note that this preset state is equivalent to the BYPASS instruction. Table 10-3. Instructions
Code B2 0 0 X 1 1 B1 0 0 1 0 0 B0 0 1 X 0 1 Instruction EXTEST SAMPLE/PRELOAD BYPASS HI-Z BYPASS
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During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with the standard 2-bit binary value (01) into the two least significant bits and the loss-of-crystal (LOC) status signal into bit 2. The parallel outputs, however, remain unchanged by this action since an update-IR signal is required to modify them. The LOC status bit of the instruction register indicates whether an internal clock is detected when operating with a crystal clock source. The LOC bit is clear when a clock is detected and set when it is not. The LOC bit is always clear when an external clock is used. The LOC bit can be used to detect faulty connectivity when a crystal is used to clock the device.
10.4.1 EXTEST (000)
The external test (EXTEST) instruction selects the 155-bit boundary scan register. EXTEST asserts internal reset for the MC68341 system logic to force a predictable benign internal state while performing external boundary scan operations. By using the TAP, the register is capable of a) scanning user-defined values into the output buffers, b) capturing values presented to input pins, c) controlling the direction of bidirectional pins, and d) controlling the output drive of three-state output pins. For more details on the function and uses of EXTEST, please refer to the IEEE 1149.1 document.
10.4.2 SAMPLE/PRELOAD (001)
The SAMPLE/PRELOAD instruction selects the 155-bit boundary scan register and provides two separate functions. First, it provides a means to obtain a snapshot of system data and control signals. The snapshot occurs on the rising edge of TCK in the captureDR controller state. The data can be observed by shifting it transparently through the boundary scan register. NOTE Since there is no internal synchronization between the IEEE 1149.1 clock (TCK) and the system clock (CLKOUT), the user must provide some form of external synchronization to achieve meaningful results. The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output bits prior to selection of EXTEST. This initialization ensures that known data will appear on the outputs when entering the EXTEST instruction.
10.4.3 BYPASS (X1X, 101)
The BYPASS instruction selects the single-bit bypass register as shown in Figure 10-9. This creates a shift-register path from TDI to the bypass register and, finally, to TDO, circumventing the 155-bit boundary scan register. This instruction is used to enhance test efficiency when a component other than the MC68341 becomes the device under test.
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SHIFT DR 0 FROM TDI
G1 1 MUX 1
1D C1 TO TDO
CLOCK DR
Figure 10-9. Bypass Register When the bypass register is selected by the current instruction, the shift-register stage is set to a logic zero on the rising edge of TCK in the capture-DR controller state. Therefore, the first bit to be shifted out after selecting the bypass register will always be a logic zero.
10.4.4 HI-Z (100)
The HI-Z instruction is not included in the IEEE 1149.1 standard. It is provided as a manufacturer's optional public instruction to prevent having to backdrive the output pins during circuit-board testing. When HI-Z is invoked, all output drivers, including the twostate drivers, are turned off (i.e., high impedance). The instruction selects the bypass register.
10.5 MC68341 RESTRICTIONS
The control afforded by the output enable signals using the boundary scan register and the EXTEST instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. The user must avoid situations in which the MC68341 output drivers are enabled into actively driven networks. Overdriving the TDO driver when it is active is not recommended. The MC68341 includes on-chip circuitry to detect the initial application of power to the device. Power-on reset (POR), the output of this circuitry, is used to reset both the system and IEEE 1149.1 logic. The purpose for applying POR to the IEEE 1149.1 circuitry is to avoid the possibility of bus contention during power-on. The time required to complete device power-on is power-supply dependent. However, the IEEE 1149.1 TAP controller remains in the test-logic-reset state while POR is asserted. The TAP controller does not respond to user commands until POR is negated. The MC68341 features a low-power stop mode that uses a CPU instruction called LPSTOP. The interaction of the IEEE 1149.1 interface with LPSTOP mode is as follows: 1. Leaving the TAP controller test-logic-reset state negates the ability to achieve minimal power consumption, but does not otherwise affect device functionality. 2. The TCK input is not blocked in LPSTOP mode. To consume minimal power, the TCK input should be externally connected to V CC or ground. 3. The TMS and TDI pins include on-chip pullup resistors. In LPSTOP mode, these two pins should remain either unconnected or connected to VCC to achieve minimal power consumption.
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10.6 NON-IEEE 1149.1 OPERATION
In non-IEEE 1149.1 operation, there are two constraints. First, the TCK input does not include an internal pullup resistor and should be pulled up externally to preclude mid-level inputs. The second constraint is to ensure that the IEEE 1149.1 test logic is kept transparent to the system logic by forcing the TAP controller into the test-logic-reset state, using either of two methods. During power-on, POR forces the TAP controller into this state. Alternatively, sampling TMS as a logic one for five consecutive TCK rising edges also forces the TAP controller into this state. If TMS either remains unconnected or is connected to VCC , then the TAP controller cannot leave the test-logic-reset state, regardless of the state of TCK.
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SECTION 11 APPLICATIONS
This section provides guidelines for using the MC68341. Minimum system-configuration requirements and memory interface information are discussed.
11.1 MINIMUM SYSTEM CONFIGURATION
One of the powerful features of the MC68341 is the small number of external components needed to create an entire system. The information contained in the following paragraphs details a simple high-performance MC68341 system (see Figure 11-1). This system configuration features the following hardware: * Processor Clock Circuitry * Reset Circuitry * SRAM Interface * ROM Interface * Serial Interface
CLOCK CIRCUITRY
SRAM
MC68341
SERIAL INTERFACE ROM
Figure 11-1. Minimum System Configuration Block Diagram
11.1.1 Processor Clock Circuitry
The MC68341 has an on-chip clock synthesizer that can operate from an on-chip phaselocked loop (PLL) and a voltage-controlled oscillator (VCO). The clock synthesizer uses an external crystal connected between the EXTAL and XTAL pins as a reference frequency source. Figure 11-2 shows a typical circuit using an inexpensive 32.768-kHz watch crystal. The 22-M resistor connected between the EXTAL and XTAL pins provides biasing for a faster oscillator startup time. The crystal manufacturer's documentation should be consulted for specific recommendations on external component values.
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470 k XTAL MC68341 EXTAL 22 M
4.7 pF
32.768 kHz
20 pF
Figure 11-2. Sample Crystal Circuit The circuit shown in Figure 11-3 is the typical circuit recommended by Statek Corporation, for 32768 kHz crystal, part number CX-IV. It is recommended to start with these values, but parameter values may need to be adjusted to compensate for variables in layout.
470 k XTAL MC68341 EXTAL 22 M
10 pF
32.768 kHz
20 pF
Figure 11-3. Statek Corporation Crystal Circuit A separate power pin (VCCSYN ) is used to provide increased noise immunity for the clock circuits. The source for VCCSYN should be a quiet power supply, and external bypass capacitors (see Figure 11-4) should be placed as close as possible to the VCCSYN pin to ensure a stable operating frequency. Additionally, the PLL requires that an external low-leakage filter capacitor, typically in the range of 0.01 to 0.1 F, be connected between the XFC and VCCSYN pins. The XFC capacitor should provide 50-M insulation but should not be electrolytic. For external clock mode without PLL, the XFC pin can be left open. Smaller values of the external filter capacitor provide a faster response time for the PLL, and larger values provide greater frequency stability. Figure 11-4 depicts examples of both an external filter capacitor and bypass capacitors for VCCSYN .
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VCCSYN VCCSYN MC68341 XFC 0.1 F 1 0.1 F 0.01 F
NOTE 1: Must be a low leakage capacitor.
Figure 11-4. XFC and V CCSYN Capacitor Connections
11.1.2 Reset Circuitry
A power-on reset (POR) is generated by the SIM41 module when it detects a positive going V CC transition--the VCC threshold is typically in the range 2.0-2.7V, and varies depending on processing and environmental variables. Hysteresis is included in the reset circuit to prevent reassertion for a monotonically increasing VCC voltage; however, excessively long VCC rise times (>100 ms) may allow the reset logic to release RESET before V CC has stabilized. The reset thresholds provided in the SIM41 should not be relied upon to monitor VCC, since internal logic may fail at voltages between spec VCCmin and the reset trigger threshold. An external low voltage monitor circuit, such as the MC34064, should be used instead. When the MC68341 is used in crystal clock mode, the simplest external reset logic consists of simply a 1K pullup resistor from RESET to V CC . This solution relies on a monotonically increasing VCC that has a rise time on the order of 100ms or less - the actual allowable rise time is dependent on the startup time of the 32.768kHz oscillator circuit. As noted above, this does not provide rigorous VCC monitoring, and may be susceptible to sags or glitches in the VCC supply voltage. In external clock mode, either with or without the PLL, the POR time delay of 328 * T clkin does not provide adequate time for V CC to stabilize before allowing reset to negate. Applications using these two clocking modes should include an external reset circuit which generates an appropriate delay for the power source being used, as well as a voltage monitor if needed.
11.1.3 SRAM Interface
SRAM interfacing is very simple when a programmable chip select is used, as shown in Figure 11-5. The chip select provides address decode and controls bus cycle termination, while UWE and LWE are used as byte write strobes. The SRAMs are enabled only during SRAM accesses to minimize system power consumption. This SRAM interface supports a two-clock access at 16.78-MHz with up to 24ns memory data access time. If buffers are required to reduce signal loading or if slower and less expensive memories are desired, a three-clock bus cycle can be used. Additional
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memories can be used provided the MC68341 specification for load capacitance on the chip-select (CS) signal is not exceeded. (Address buffers may be needed, however.)
A31-A0
LWE MC68341 UWE R/W CS1 D15-D0
.. ..
A15-A1 .. .. MCM62L06C
.. .. W G
A15-A1 .. ..
MCM62L06C
W G E DQ7-D0 ... D15-D8 .
E
DQ7-D0
. .. D7-D0
.
Figure 11-5. SRAM Interface
11.1.4 ROM Interface
Using the programmable chip selects creates a very straightforward ROM interface. As shown in Figure 11-6, no external circuitry is needed. Care must be used, however, not to overload the address bus. Address buffers may be required to ensure that the total system input capacitance on the address signals does not exceed the CL specification.
MC68341 A16-A1 D15-D0 CS0 CE OE 16-BIT ROM
Figure 11-6. ROM Interface
11.1.5 Serial Interface
The necessary circuitry to create an RS-232 interface with the MC68341 includes an external crystal and an RS-232 receiver/driver (see Figure 11-7). The resistor and capacitor values shown are typical; the crystal manufacturer's documentation should be consulted for specific recommendations on external component values. The circuit shown does not include modem support (ready-to-send (RTS) and clear-to-send (CTS) are not shown); however, these signals can be connected to the receiver/driver and to the connector in a similar manner as the connections for TxDx and RxDx.
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10 pF X1 10 M X2 MC68341 470 4.7 pF Rx1 Tx1 RS 232 CONNECTOR 10 F 10 F DSACK0 3.6864 MHz
RxD TxD T
R
MC145407 VCC 10 F 10 F C1+ C1VSS GND V CC V DD C2+ C2-
Figure 11-7. Serial Interface
11.2 MEMORY INTERFACE INFORMATION
The following paragraphs contain information on using an 8-bit boot ROM, performing access time calculations, calculating frequency-adjusted outputs, and interfacing an 8-bit device to 16-bit memory using the DMA channel single-address mode.
11.2.1 Using an 8-Bit Boot ROM
Upon power-up, the MC68341 uses CS0 to begin operation. CS0 is a six-wait-state, 16-bit chip select, until otherwise programmed. If an 8-bit ROM is desired, external circuitry can be added to return an 8-bit DSACK in five (or less) wait states (see Figure 11-8).
'393 CLKOUT CP Q0 Q1 Q2 Q3
CS0
MR
Figure 11-8. External Circuitry for 8-Bit Boot ROM The 393 is a falling edge-triggered counter; thus, CS0 is stable during the time in which it is being clocked. CS0 acts as the asynchronous reset--i.e., when it is asserted, the 393 is allowed to count. The falling edge of S2 provides the first counting edge. Q1 does not transition on this falling edge, but transitions to a logic one on the subsequent edge. DSACK0 is Q1 inverted; thus, on the next falling edge, DSACK0 is seen as asserted, indicating an 8-bit port. When CS0 is negated, Q1 is again held in reset and DSACK0 is negated. The timing diagram in Figure 11-9 illustrates this operation.
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S0 CLKOUT
S1
S2
SW
SW
SW
SW
S3
S4
S5
S0
S1
S2
CS0
Q1
DSACK0
Figure 11-9. 8-bit Boot ROM Timing
11.2.2 Access Time Calculations
The two time paths that are critical in an MC68341 application using the CS signals are shown in Figure 11-10. The first path is the time from address valid to when data must be available to the processor; the second path is the time from CS asserted to when data must be available to the processor. Note that the CS timing shown in these examples is for M68300 bus cycles; timing for 68000 bus cycles can be derived in a similar manner.
S0 CLKOUT t6 A31-A0 t9 CS t CSDV D15-D0 tADV t 27 S1 S4 S5 S0
Figure 11-10. Access Time Computation Diagram As shown in the diagram, an equation for the address access time, t ADV , can be developed as follows: tADV = t cyc(N c - 0.5) - t s9 - t s27 where: tcyc = system CLKOUT period Nc = number of clocks per bus cycle ts6 = CLKOUT high to address valid = 30 ns maximum at 16.78 MHz ts27 = data-in valid to CLKOUT low setup = 5 ns minimum at 16.78 MHz
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An equation for the chip select access time, t CSDV, can be developed as follows: tCSDV = t cyc(N c - 1) - t s9 - ts27 where: tcyc = system clock period Nc = number of clocks per access ts9 = CLKOUT low to CS asserted = 30 ns maximum at 16.78 MHz ts27 = data-in valid to CLKOUT low setup = 5 ns minimum at 16.78 MHz Using these equations, the memory access times at 16.78 MHz are shown in Table 11-1. See Section 12 Electrical Characteristics for more timing information. Table 11-1. Memory Access Times at 16.78 MHz
Access Time t ADV t CSDV N=2 54 ns 24 ns N=3 114 ns 84 ns N=4 173 ns 143 ns N=5 233 ns 203 ns N=6 292 ns 263 ns
The values can be used to determine how many clock cycles an access will take, given the access time of the memory devices and any delays through buffers or external logic that may be needed.
11.2.3 Calculating Frequency-Adjusted Output
The general relationship between the CLKOUT and most input and output signals is shown in Figure 11-11. Most outputs transition off of a falling edge of CLKOUT, but the same principle applies to those outputs that transition off of a rising edge.
CLKOUT td OUTPUTS t su ASYNCHRONOUS INPUTS th
Figure 11-11. Signal Relationships to CLKOUT For outputs that are referenced to a clock edge, the propagation delay (td ) does not change as the frequency changes. For instance, specification 6 in the electrical characteristics, shown in Section 12 Electrical Characteristics, shows that address, function code, and size information is valid 3 to 30 ns after the rising edge of S0. This specification does not change even if the device frequency is less than 16.78 MHz. Additionally, the relationship between the asynchronous inputs and the clock edge, as shown in Figure 11-11, does not change as frequency changes.
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A second type of specification indicates the minimum amount of time a signal will be asserted. This type of specification is illustrated in Figure 11-12.
T/2 CLKOUT td OUTPUT tw N
Figure 11-12. Signal Width Specifications The method for calculating a frequency-adjusted tw is as follows: tw' = tw + N (T f'/2 - T f/2) + (T f'/2 - t d) where: tw' = the frequency-adjusted signal Frequency-Adjusted Signal:width tw = the signal width at 16.78 MHz N = the number of full one-half clock periods in tw Tf'/2 = one-half the new clock period Tf/2 = one-half the clock period at full speed td = the propagation time from the clock edge The following calculation uses a 16.78-MHz part, specification 14, AS width asserted, at 12.5 MHz as an example: tw = 100 ns N=3 Tf'/2 = 80/2 = 40 ns Tf/2 = 60/2 = 30 ns td = 30 ns maximum therefore: tw' = 100 + 3(40 - 30) + (40 - 30) = 140 ns
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The third type of specification used is a skew between two outputs (see Figure 11-13).
T/2 CLKOUT td1 OUTPUT1 t d2 OUTPUT2 ts
Figure 11-13. Skew between Two Outputs The method for calculating a frequency-adjusted ts is as follows: ts' = ts + N (T f'/2 - T f/2) + (T f'/2 - td1) where: ts' = the frequency-adjusted skew ts = the skew at full speed N = the number of full one-half clock periods in ts, if any Tf'/2 = one-half the new clock period Tf/2 = one-half the clock period at full speed td1 = the propagation time for the first output from the clock edge The following calculation uses a 16.78-MHz port, specification 21, R/W high to A S asserted, at 8 MHz as an example: ts = 15 ns minimum N=0 Tf'/2 = 125/2 = 62.5 ns Tf/2 = 60/2 = 30 ns td1 = 30 ns maximum therefore: ts' = 15 + 0(62.5 - 30) + (62.5 - 30) = 47.5 ns minimum In this manner, new specifications for lower frequencies can be derived for an MC68341.
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11.2.4 Interfacing an 8-Bit Device to 16-Bit Memory Using Single-Address DMA Mode
One of the requirements of single-address mode is that the source and destination must be the same port size. However, the MC68341 can perform direct memory accesses in single-address mode between an 8-bit device and 16-bit memory. The port size must be specified as 8 bits, and some external logic is required as shown in Figure 11-14.
DEVICE
D15-D8
MC68341
R/W A0 SIZ1 SIZ0
T/R OE
B 74F245 A
MEMORY
D7-D0
Figure 11-14. Circuitry for Interfacing 8-Bit Device to 16-Bit Memory in Single-Address DMA Mode During even-byte accesses, the data is transferred directly on D15-D8. However, during odd-byte accesses, the data must be routed on D15-D8 for the 8-bit device and on D7- D0 for the 16-bit memory.
11.3 POWER CONSUMPTION CONSIDERATIONS
The MC68341 can be designed into low-power applications that involve high-performance processing capability (32-bits), high functional density, small size, portable capability, and battery operation. The MC68341 fits into the following types of applications: * "Palmtop" Computers * Telephony -- Stylus Input -- Cordless Phones -- Voice Input -- Cellular Phones -- Image Input * CD-I, CD-ROM * Transaction Tracking * Defense Industry -- Car Rental -- Guidance Systems -- Cargo -- Tracking Systems -- Courier * Data Entry -- Handheld * Instruments * Bar Code Scanners * Handheld Games
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11.4 MC68341V (3.3 V)
The MC68341V can operate with a 3.3-V power supply for significant power savings. The formula for power dissipation is Pd V2 x f + dc Table 11-2 shows typical electrical characteristics for both the MC68341 and MC68341V. Table 11-2. Typical Electrical Characteristics
Parameter Clock Frequency Typical Current (16 MHz) Typical Current (8 MHz) Standby Current MC68341 (5.0 V) 0-16.78 MHz 0-25 MHz TBD TBD TBD MC68341V (3.3 V) 0-8.39 MHz 0-16.78 MHz TBD TBD TBD
Running at 3.3 V saves 66% of the power consumption. The 3.3 V operation provides the following user advantages:
Advantage Lower Supply Voltage Fewer Batteries Lower Current Drain Less Heat Generated Less EMF Radiation Benefit Fewer Batteries Less Weight Smaller Size Extended Battery Life No Fan No Fan Noise Easier FCC Certification Less Crosstalk Closer PCB Traces All-In-One 3.3 V Part: Processor Peripherals Glue Logic
High Functional Integration
These advantages result in a much more portable system.
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SECTION 12 ELECTRICAL CHARACTERISTICS - PRELIMINARY
This section contains preliminary information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MC68341. Refer to Section 13 Ordering Information and Mechanical Data for specific part numbers corresponding to voltage, frequency, and temperature ratings.
12.1 MAXIMUM RATINGS
Rating Supply Voltage 1, 2 Input Voltage1, 2 Operating Temperature Range Commercial Symbol VCC Vin TA 0 to 70 Value -0.3 to +6.5 -0.3 to +6.5 Unit V V C
Storage Temperature Range Tstg -55 to +150 C NOTES: 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or V CC ).
The above ratings define a range of conditions in which the device will operate without being damaged. However, sections of the device may not operate normally while being exposed to the electrical extremes.
12.2 THERMAL CHARACTERISTICS
Characteristic Thermal Resistance--Junction to Case Plastic 160-Pin PQFP Thermal Resistance--Junction to Ambient Plastic 160-Pin PQFP * Estimated Symbol Value TBD C/W 43* Unit C/W
JC JA
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12.3 POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in C can be obtained from: TJ = T A + (PD * JA) (1)
where: TA = Ambient Temperature, C JA = Package Thermal Resistance, Junction-to-Ambient, C/W PD = PINT + PI/O PINT = ICC x VCC, Watts--Chip Internal Power PI/O = Power Dissipation on Input and Output Pins--User Determined For most applications, P I/O < PINT and can be neglected. An approximate relationship between P D and T J (if P I/O is neglected) is: PD = K / (TJ + 273C) Solving Equations (1) and (2) for K gives: K = P D * (TA + 273C) + JA * P D2 where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P D (at thermal equilibrium) for a known TA. Using this value of K, the values of PD and T J can be obtained by solving Equations (1) and (2) iteratively for any value of T A.
12.4 AC ELECTRICAL SPECIFICATION DEFINITIONS
The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals. The measurement of the AC specifications is defined by the waveforms shown in Figure 12-1. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in the figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown. Inputs are specified with minimum setup and hold times and are measured as shown. Finally, the measurement for signal-to-signal specifications are shown. Note that the testing levels used to verify conformance to the AC specifications do not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics.
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The MC68341V low voltage part can operate up to 16.78 MHz with a 3.3 V 0.3 V supply. Separate part numbers are used to distinguish the operation of the parts according to the supply voltage- refer to Section 13 Ordering Information and Mechanical Data for the part numbering schemes. MC68341 is used throughout this section to refer to the 16.78or 25.16-MHz parts at 5.0 V 5%. MC68341V is used throughout this section to refer to the 16.78-MHz part at 3.3 V 0.3 V.
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2.0 V CLKOUT 0.8 V A B OUTPUTS(1) VALID OUTPUT n 2.0 V 0.8 V 2.0 V 0.8 V VALID OUTPUT
2.0 V 0.8 V
n+1 B VALID OUTPUT n 2.0 V 0.8 V
A
2.0 V 0.8 V
OUTPUTS(2)
VALID OUTPUT n+1
C 2.0 V INPUTS(3) 0.8 V
D 2.0 V 0.8 V
VALID INPUT
C 2.0 V INPUTS(4) 0.8 V
D 2.0 V 0.8 V DRIVE TO 2.4 V DRIVE TO 0.5 V
VALID INPUT
2.0 V ALL SIGNALS(5) 0.8 V E F 2.0 V 0.8 V NOTES: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. This output timing is applicable to all parameters specified relative to the falling edge of the clock. 3. This input timing is applicable to all parameters specified relative to the rising edge of the clock. 4. This input timing is applicable to all parameters specified relative to the falling edge of the clock. 5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal. LEGEND: A. Maximum output delay specification. B. Minimum output hold time. C. Minimum input setup time specification. D. Minimum input hold time specification. E. Signal valid to signal valid specification (maximum or minimum). F. Signal valid to signal invalid specification (maximum or minimum).
Figure 12-1. Drive Levels and Test Points for AC Specifications
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12.5 DC ELECTRICAL SPECIFICATIONS - PRELIMINARY
(GND = 0 Vdc, TA = 0 to 70C; see numbered notes) Characteristic Input High Voltage (except clocks) Input Low Voltage Clock Input High Voltage (EXTAL, EXTCLK, SCLK) Undershoot Input Leakage Current (All Input Only Pins) Vin = VCC or GND Hi-Z (Off-State) Leakage Current (All Noncrystal Outputs and I/O Pins) Vin = 0.5/2.4 V1 Signal Low Input Current VIL = 0.8 V Signal High Input Current VIH = 2.0 V Output High Voltage1, 2 I OH = -0.8 mA I OH = -20 A 3 Output Low Voltage1 I OL = 2.0 mA I OL = 3.2 mA I OL = 5.3 mA I OL = 15.3 mA All Noncrystal Outputs except DONE2, DONE1 , RTCOUT, HALT , RESET. RTCOUT CLKOUT, FREEZE, IPIPE , IFETCH A23-A0, D15-D0, FC3-FC0, SIZ1, SIZ0 All Other Output Only and Group 2 I/O Pins HALT , RESET VOL -- 0.5 0.5 0.5 0.5 -- I CC SICC PD I CC SICC PD VBATT I BATT Cin TBD TBD -- -- TBD TBD -- 2.0 -- -- 10 20 -- 100 pF TBD VCC TBD mA A mW V A pF TBD mA A mW V TMS, TDI TMS, TDI IL IH VOH -0.015 -0.015 2.4 0.2 0.2 -- mA mA V Symbol VIH VIL VIHC -- I in I OZ Min 2.0 GND 0.7 * (V CC ) -- -2.5 -20 Max VCC 0.8 VCC +0.3 -0.8 2.5 20 Unit V V V V A A
Total Supply Current at 5 V +5% @ 16.78 MHz RUN LPSTOP (VCO Off) Power Dissipation at 5 V +5% @ 16.78 MHz4 Total Supply Current at 3.3 V + 0.3 V @ 16.78 MHz RUN LPSTOP (VCO Off) Power Dissipation at 3.3 V +0.3 V @ 16.78 MHz 4 RTC Battery Voltage RTC Battery Supply Current Input Capacitance 5 All Input-Only Pins All I/O Pins Load Capacitance
CL
NOTES: 1. Input-Only Pins: BERR, BG, BKPT, BR, CTSB, CTSA, DREQ2, DREQ1, DSACK1, DSACK0, EXTAL, RxDB, RxDA, SCLK, TCK, TDI, TGATE, TIN, TMS,EXTCLK, BSW. Output-Only Pins: A23-A0, AS, AS68K , BG , CLKOUT, CS7-CS1, DACK2 , DACK1, DS , FC3-FC0, FREEZE, IFETCH , IPIPE , LDS, LWE, RMC, RTSB , RTSA, R/ W, RRDYA, SIZ1, SIZ0, TDO, TOUT, TxDB, TxDA, TRDYA , UDS , UWE. Input/Output Pins: Group 1: D15-D0. Group 2: A31-A24, CS0, DONE2, DONE1, IRQ7-IRQ1 , MODCK Group 3: HALT, RESET. Group 4: MISO, MOSI, PCS1, PCS0, QSCLK 2. VOH specification for HALT, RESET, DONE2, and DONE1 is not applicable because they are open-drain pins. 3. RMC/RTCOUT can source 20A when configured as RTCOUT, 0.8mA when configured as RMC. 4. Power dissipation measured with all modules active. 5. Capacitance is periodically sampled rather than 100% tested.
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12.6 CLOCK AC ELECTRICAL SPECIFICATIONS - PRELIMINARY
(GND = 0 Vdc, TA = 0 to 70C; see numbered notes)
CLOCK SPECIFICATIONS - Crystal Mode
3.3 V or 5.0 V 16.78 MHz Num. Characteristic System Frequency - Crystal Mode1 Crystal Frequency2 External Clock Input Frequency 3 External Clock Duty Cycle VCO Frequency Range PLL Start-up Time4 Limp Mode CLKOUT Frequency 5 SYNCR X-bit = 0 and Z-bit = 0 SYNCR X-bit = 1 and Z-bit = 0 CLKOUT stability 6 1 CLKOUT Period CLKOUT Duty Cycle 2,3 4,5 CLKOUT Pulse Width CLKOUT Rise and Fall Times t CW t Crf f VCO t rc f limp Symbol f sys f XTAL f EXT Min 0.13 25 25 20 0.1 -- -- -- -- 59.6 47 28 -- Max 16.78 50 50 80 51.2 20 8.39 16.78 1 -- 53 -- 5 5.0 V 25.16 MHz Min 0.13 25 25 20 0.1 -- -- -- -- 39.7 47 19 -- Max 25.16 50 50 80 51.2 20 8.39 16.78 1 -- 53 -- 4 % ns % ns ns Unit MHz kHz kHz % MHz ms MHz
CLK t cyc
NOTES: 1. All crystal mode clock specifications are based on using a 32.768-kHz crystal for the input. 2. The RTC requires a 32.768 kHz crystal or external clock for proper operation. 3. EXTAL can be direct driven by an external oscillator source - refer to the DC Electrical Characteristics for VIL/VIH requirements. 4. Assumes that a stable VCCSYN is applied, that an external filter capacitor with a value of 0.1 F is attached to the XFC pin, and that the crystal oscillator is stable. This specification also applies to the period required for PLL lock after changing the W or Y frequency control bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock to lock after exiting LPSTOP. 5. The X-bit in the SYNCR controls a divide-by-two scaler on the system clock output. 6. CLKOUT stability is the average deviation from programmed frequency measured at maximum f sys . Measurement is made with a stable external clock input applied using the PLL.
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CLOCK SPECIFICATIONS - External Clock With PLL Mode
3.3 V or 5.0 V 16.78 MHz Num. Characteristic System Frequency External Clock with PLL Mode 1C External Clock Input Period External Clock Duty Cycle External Clock Input Period with /2 External Clock Duty Cycle with /2 VCO Frequency Range PLL Start-up Time1 Limp Mode CLKOUT Frequency CLKOUT stability 2 CLKOUT Duty Cycle 2C, 3C 4,5 CLKOUT Pulse Width CLKOUT Rise and Fall Times Clock Input to CLKOUT Skew (Rising Edges) t EXTCW t Crf f VCO t rc f limp CLK t EXTcyc Symbol f sys t EXTcyc Min 0.1 59.6 20 TBD TBD 0.1 -- -- -- 47 28 -- -- 1 53 -- 5 5 Max 16.78 10S 80 -- -- 33.6 20 5.0 V 25.16 MHz Min 0.1 39.7 20 TBD TBD 0.1 -- -- -- 47 19 -- -- 1 53 -- 4 5 Max 25.16 10S 80 -- -- 51.2 20 Unit MHz ns % ns % MHz ms kHz % % ns ns ns
NOTES: 1. Assumes that a stable VCCSYN is applied, that an external filter capacitor with a value of 0.1 F is attached to the XFC pin, and that the crystal oscillator is stable. This specification also applies to the period required for PLL lock after changing the W or Y frequency control bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock to lock after exiting LPSTOP. 2. CLKOUT stability is the average deviation from programmed frequency measured at maximum f sys . Measurement is made with a stable external clock input applied using the PLL.
CLOCK SPECIFICATIONS - External Clock Mode (Without PLL)
3.3 V or 5.0 V 16.78 MHz Num. Characteristic System Frequency1 External Clock Without PLL Mode External Clock Input Period External Clock Pulse Width External Clock Input Period with /2 External Clock Pulse Width with /2 2B, 3B9 CLKOUT Pulse Width 4,5 CLKOUT Rise and Fall Times Clock Input to CLKOUT Skew (Rising Edges) All internal registers retain data at 0 Hz. t EXTCW t Crf t EXTcyc Symbol f sys t EXTcyc Min dc 59.6 TBD TBD TBD TBD -- TBD Max 16.78 -- -- -- -- -- 5 TBD 5.0 V 25.16 MHz Min dc 39.7 TBD TBD TBD TBD -- TBD Max 25.16 -- -- -- -- -- 4 TBD Unit MHz ns ns ns ns ns ns ns
1B
1.
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12.7 AC TIMING SPECIFICATIONS - PRELIMINARY
(GND = 0 Vdc, TA = 0 to 70C; see numbered notes; see Figures 12-2-12-13) 3.3 V or 5.0 V 16.78 MHz Num. 6 6A 7 8 99 9A2 9B 9C 11 11A 12 13 Characteristic CLKOUT High to Address, FC, SIZ Valid CLKOUT High to FC3, RMC Valid CLKOUT High to Address, Data, FC, SIZ, RMC High Impedance CLKOUT High to Address, FC, SIZ, RMC Invalid CLKOUT Low to AS , DS, CS, IFETCH , IPIPE, IACK Asserted AS to DS or CS Asserted (Read) CLKOUT High to AS68K , CS, UDS, LDS Asserted AS68K to UDS , LDS, or CS Asserted (Read) Address, FC, SIZ, RMC Valid to AS , CS (and DS Read) Asserted Address, FC, SIZ, RMC Valid to AS68K , CS (and UDS /LDS Read) Asserted CLKOUT Low to AS , DS, CS, IFETCH , IPIPE , AS68K , LDS, UDS, LWE, UWE Negated AS , DS, CS, AS68K , UDS, LDS , UWE, LWE , IACK Negated to Address, FC, SIZ Invalid (Address Hold) AS , CS (and DS Read) Width Asserted DS Width Asserted (Write) AS , CS, IACK (and DS Read) Width Asserted (Fast Termination Cycle) AS68K , CS (and UDS/ LDS Read) Width Asserted UDS, LDS Width Asserted (3-Clock Write) AS , DS, CS Width Negated CLKOUT High to AS , DS, R/ W, AS68K, UDS, LDS, UWE, LWE High Impedance AS , DS, CS, AS68K, UDS, LDS, UWE, LWE, Negated to R/ W High CLKOUT High to R/W High CLKOUT High to R/W Low R/ W High to AS , CS Asserted R/ W High to AS68K, CS Asserted R/ W Low to DS Asserted (Write) R/ W Low to LDS, UDS Asserted (Write) CLKOUT High to Data-Out Valid t AVSA t AVSKA t CLSN t SNAI Symbol t CHAV t CHAVB t CHAZx t CHAZn t CLSA t STSA Min 0 0 0 0 3 -15 3 -15 15 45 3 15 Max 30 35 60 -- 30 15 30 15 -- -- 30 -- 5.0 V 25.16 MHz Min 0 0 0 0 3 -6 3 -6 10 30 3 10 Max 20 25 40 -- 20 6 20 6 -- -- 20 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
14 14A 14B 14C 14D 153 16 17 18 20 219 21A 22 22A 23
t SWA t SWAW t SWDW t SWA t SWBW t SN t CHSZ t SNRN t CHRH t CHRL t RAAA t RABA t RASA t RADA t CHDO
100 45 40 70 15 40 -- 15 0 0 15 45 70 100 --
-- -- -- -- -- -- 60 -- 30 30 -- -- -- -- 30
70 30 30 50 10 30 -- 10 0 0 10 30 47 67 --
-- -- -- -- -- -- 40 -- 20 20 -- -- -- -- 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
12-8
MC68341 USER'S MANUAL
MOTOROLA
12.7 AC TIMING SPECIFICATIONS - PRELIMINARY (Continued)
3.3 V or 5.0 V 16.78 MHz Num. 24 25 26 26A 27 27A 28 294 29A4 304 30A4 315 31A 32 33 34 356 37 39 39A 46 46A 47A8 47B 485,7 53 54 55 56 56A 57 Characteristic Data-Out Valid to Negating Edge of AS, CS , (Fast Termination Write) DS, CS , UDS, LDS Negated to Data-Out Invalid (Data-Out Hold) Data-Out Valid to DS Asserted (Write) Data-Out Valid to UDS, LDS Asserted (Write) Data-In Valid to CLKOUT Low (Data Setup) Late BERR , HALT, BKPT Asserted to CLKOUT Low (Setup Time, no 68K Bus) AS , DS AS68K, UDS, LDS Negated to DSACK , BERR , HALT Negated DS, UDS, LDS, CS0 Negated to Data-In Invalid (Data-In Hold) DS, CS, UDS, LDS Negated to Data-In High Impedance CLKOUT Low to Data-In Invalid (Fast Termination Hold) CLKOUT Low to Data-In High Impendance DSACK Asserted to Data-In Valid DSACK Asserted to DSACK Valid (Skew) HALT and RESET Input Transition Time CLKOUT Low to BG Asserted CLKOUT Low to BG Negated BR Asserted to BG Asserted (RMC Not Asserted) BGACK Asserted to BG Negated BG Width Negated BG Width Asserted R/ W Width Asserted (Write or Read) R/ W Width Asserted (Fast Termination Write or Read) Asynchronous Input Setup Time Asynchronous Input Hold Time DSACK Asserted to BERR , HALT Asserted Data-Out Hold from CLKOUT High CLKOUT High to Data-Out High Impedance R/ W Asserted to Data Bus Impedance Change RESET Pulse Width (Reset Instruction) RESET Pulse Width (Input from External Device) BERR Negated to HALT Negated (Rerun) Symbol t DVASN t SNDOI t DVSA t DVBSA t DICL t BELCL t SNDN t SNDI t SHDI t CLDI t CLDH t DADI t DADV t HRrf t CLBA t CLBN t BRAGA t GAGN t GH t GA t RWA t RWAS t AIST t AIHT t DABA t DOCH t CHDH t RADC t HRPW t RPWI t BNHN Min 15 15 15 45 5 20 0 0 -- 15 -- -- -- -- -- -- 1 1 2 1 150 90 8, 5 15 -- 0 -- 40 512 590 0 Max -- -- -- -- -- -- 80 -- 60 -- 90 50 30 200 30 30 -- 2.5 -- -- -- -- -- -- 30 -- 30 -- -- -- -- 5.0 V 25.16 MHz Min 10 10 10 30 5 10 0 0 -- 10 -- -- -- -- -- -- 1 1 2 1 100 60 5 10 -- 0 -- 25 512 590 0 Max -- -- -- -- -- -- 50 -- 40 -- 60 32 20 140 20 20 -- 2.5 -- -- -- -- -- -- 20 -- 20 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLKOUT CLKOUT CLKOUT CLKOUT ns ns ns ns ns ns ns ns CLKOUT CLKOUT ns
MOTOROLA
MC68341 USER'S MANUAL
12-9
12.7 AC TIMING SPECIFICATIONS - PRELIMINARY (Continued)
3.3 V or 5.0 V 16.78 MHz Num. 70 71 72 80 81 82 83 84 85 86 87 88 89 Characteristic CLKOUT Low to Data Bus Driven (Show Cycle) Data Setup Time to CLKOUT Low (Show Cycle) Data Hold from CLKOUT Low (Show Cycle) DSI Input Setup Time DSI Input Hold Time DSCLK Setup Time DSCLK Hold Time DSO Delay Time DSCLK Cycle CLKOUT High to FREEZE Asserted CLKOUT High to FREEZE Negated CLKOUT High to IFETCH High Impedance CLKOUT High to IFETCH Valid Symbol t SCLDD t SCLDS t SCLDH t DSISU t DSIH t DSCSU t DSCH t DSOD t DSCCYC t FRZA t FRZN t IFZ t IF Min 0 15 10 15 10 15 10 -- 2 0 0 0 0 Max 30 -- -- -- -- -- -- t cyc + 25 -- 50 50 50 50 5.0 V 25.16 MHz Min 0 10 6 10 6 10 6 -- 2 0 0 0 0 Max 20 -- -- -- -- -- -- t cyc + 16 -- 35 35 35 35 Unit ns ns ns ns ns ns ns ns CLKOUT ns ns ns ns
NOTES: 1. All AC timing is shown with respect to 0.8 V and 2.0 V levels unless otherwise noted. 2. This number can be reduced to 5 ns if strobes have equal loads. 3. If multiple chip selects are used, the CS width negated (#15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. 4. These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast termination reads. The user is free to use either hold time for fast termination reads. 5. If the asynchronous setup time (#47) requirements are satisfied, the DSACK low to data setup time (#31) and DSACK low to BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to CLKOUT low setup time (#27) for the following clock cycle: BERR must only satisfy the late BERR low to CLKOUT low setup time (#27A) for the following clock cycle. 6. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after cycles of the current operand transfer are complete and RMC is negated. 7. In the absence of DSACK, BERR is an asynchronous input using the asynchronous setup time (#47). 8. Specification #47A for 16.78 MHz @ 3.3 V 0.3V will be 8 ns. 9. During interrupt acknowledge cycles up to two wait states may be inserted by the processor between states S0 and S1.
12-10
MC68341 USER'S MANUAL
MOTOROLA
S0
S1
S2
S3
S4
S5
CLKOUT 6 SIZ1-SIZ0, FC3-FC0, A31-A0 AS68K UDS, LDS UWE, LWE 6A 8
RMC 11 AS 9 DS 9A CS 18 R/W 46 47A
DSACK0
14 12
13
21
20
28
DSACK1
31 D15-D0
29
29A 27 BERR 48 HALT 9 IFETCH, IPIPE 47A ASYNCHRONOUS INPUTS 27A BKPT NOTE: All timing is shown with respect to 0.8V and 2.0V levels. 47B 12 12 27A
Figure 12-2. M68300 Read Cycle Timing Diagram
MOTOROLA MC68341 USER'S MANUAL 12-11
S0 CLKOUT 6 A31-A0, FC3-FC0, SIZ1-SIZ0 AS68K UDS, LDS UWE, LWE
S1
S2
S3
S4
S5
6A
8
11 14 AS 9 DS 9 12 13
15
CS 20 R/W 46 DSACK0 47A DSACK1 55 D15-D0 23 26 BERR 48 HALT 27A 54 25 53 28 22 14A 17
BKPT
NOTE: All timing is shown with respect to 0.8-V and 2.0-V levels.
Figure 12-3. M68300 Write Cycle Timing Diagram
12-12
MC68341 USER'S MANUAL
MOTOROLA
S0 CLKOUT 6 A31-A0
S1
S4
S5
S0
8
FC3-FC0
SIZ1-SIZ0 9 14B AS 12 DS
CS 18 R/W 46A 27 30 D15-D0 27A BKPT 30A
Figure 12-4. M68300 Fast Termination Read Cycle Timing Diagram
MOTOROLA
MC68341 USER'S MANUAL
12-13
S0 CLKOUT 6 A31-A0
S1
S4
S5
S0
8
FC3-FC0 SIZ1-SIZ0 12 AS 9 14B DS CS 20 46A R/W 23 D15-D0 27A BKPT 25 24 18
Figure 12-5. M68300 Fast Termination Write Cycle Timing Diagram
12-14
MC68341 USER'S MANUAL
MOTOROLA
S0
S1
S2
S3
S4
S5
CLKOUT 6 SIZ1-SIZ0, FC2-FC0, A31-A0 11A AS68K UDS, LDS UWE, LWE 9B 9C RMC 12 13 14C 8
AS
DS
CS 18 R/W 46 47A
DSACKx
21A
20
28
31 D15-D0
29
29A 27 BERR 48 HALT 9 IFETCH, IPIPE 27A BKPT NOTE: All timing is shown with respect to 0.8V and 2.0V levels. 12 12 27A
Figure 12-6. 68000 Three-Clock Read Cycle Timing Diagram
MOTOROLA
MC68341 USER'S MANUAL
12-15
S0 CLKOUT 6 A31-A0, FC2-FC0, SIZ1-SIZ0
S1
S2
S3
S4
S5
8
12 11A AS68K 9B UDS, LDS 9B 13 14C
UWE, LWE AS, DS 20 22A 14D 17
CS
R/W 46 DSACKx 55 D15-D0 23 26A BERR 48 HALT 27A 54 47A 28 25 53
NOTE: All timing is shown with respect to 0.8V and 2.0V levels.
Figure 12-7. 68000 Three-Clock Write Cycle Timing Diagram
12-16
MC68341 USER'S MANUAL
MOTOROLA
S0 CLKOUT
S1
S2
S3
S4
S5
A31-A0
7
D15-D0
AS
16
DS R/W
DSACK0
DSACK1
47A
BR
35
BG
39A
33
BGACK
34
37
Figure 12-8. Bus Arbitation Timing--Active Bus Case
MOTOROLA
MC68341 USER'S MANUAL
12-17
CLKOUT
A31-A0
D15-D0
AS 47A BR 35 BG 33 BGACK 34 47A 37 47A
Figure 12-9. Bus Arbitration Timing--Idle Bus Case
S0 CLKOUT 6 A31-A0 18 R/W 20 AS
S41
S42
S43
S0
S1
S2
8
12 9 15
DS 70 D15-D0 27A BKPT SHOW CYCLE START OF EXTERNAL CYCLE 71 72
Figure 12-10. Show Cycle Timing Diagram
12-18
MC68341 USER'S MANUAL
MOTOROLA
S0 CLKOUT 6 SIZ1-SIZ0
0-2 CLOCKS *
S1
S2
S3
S4
S5
8
FC3-FC0
A31-A0, 11 AS 9 DS 9A IACKx 18 R/W 46 31A DSACK0 47A DSACK1 31 29 D15-D0 29A 27 28 21 20 13 12 14
* Up to two wait states may be inserted by the processor between states S0 and S1.
Figure 12-11. IACK Cycle Timing Diagram
MOTOROLA
MC68341 USER'S MANUAL
12-19
CLKOUT
FREEZE 82 BKPT/DSCLK
83
85 81 80 IFETCH/DSI 84 IPIPE/DSO
Figure 12-12. Background Debug Mode Serial Port Timing
CLKOUT 86 FREEZE 87 IFETCH/DSI 88 89
Figure 12-13. Background Debug Mode FREEZE Timing
12-20
MC68341 USER'S MANUAL
MOTOROLA
12.8 DMA MODULE AC ELECTRICAL SPECIFICATIONS - PRELIMINARY
(GND = 0 Vdc, TA = 0 to 70C; see Figure 12-14 and 12-15) 3.3 V or 5.0 V 16.78 MHz Num. 1 2 3 41 5 6 7 8 8A 9 10 Characteristic CLKOUT Low to AS , DACK, DONE Asserted CLKOUT Low to AS , DACK Negated DREQ Asserted to AS Asserted (for DMA Bus Cycle) Asynchronous Input Setup Time to CLKOUT Low Asynchronous Input Hold Time from CLKOUT Low AS to DACK Assertion Skew DACK to DONE Assertion Skew AS , DACK, DONE Width Asserted AS , DACK, DONE Width Asserted (Fast Termination Cycle) CLKOUT High to DTC Asserted CLKOUT High to DTC Negated Min -- -- Max 30 30 5.0 V 25.16 MHz Min -- -- Max 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns
3t cyc + tAIST + tCLSA 8, 5 15 -15 -15 100 40 -- -- -- -- 15 15 -- -- 30 30 5 10 -10 -8 70 28 -- -- -- -- 10 8 -- -- 20 20
NOTES: 1. Specification #4 for 16.78 MHz @ 3.3 V 0.3 V will be 8 ns.
CPU_CYCLE (DMA REQUEST) S0 CLKOUT 4 DONE (INPUT) DREQ 3 AS 1 DACK 7 DONE (OUTPUT) 1 2 5 1 6 8 S1 S2 S3 S4 S5 S0 S1 DMA_CYCLE S2 S3 S4 S5
Figure 12-14. DMA Signal Timing Diagram
MOTOROLA
MC68341 USER'S MANUAL
12-21
S0 CLOCK
S1
S2
S3
Sw
Sw
Sw
Sw
S4
S5
S0
S1
ADDR/SIZ FC, R/W
AS, DS, CSx
DSACKx
1 1
DACKx (NORMAL) DACKx (DELAYED)
RDYx 5 10 4 DTC 9
Figure 12-15. DMA Enhancements Timing Diagram
12-22
MC68341 USER'S MANUAL
MOTOROLA
12.9 TIMER MODULE ELECTRICAL SPECIFICATIONS - PRELIMINARY
(GND = 0 Vdc, TA = 0 to 70C; see Figures 12-16 and 12-17) 3.3 V or 5.0 V 16.78 MHz Num. 1 2 3 41 5 6 7 8 Characteristic CLKOUT Period in Crystal Mode Clock Rise and Fall Time TIN/ TGATE High or Low Time, Minimum Pulse Width Asynchronous Input Setup Time to CLKOUT Low Asynchronous Input Hold Time from CLKOUT Low Asynchronous Input Setup Time to CLKOUT High Asynchronous Input Hold Time from CLKOUT High CLKOUT High to TOUT Valid Symbol t cyc t rf -- -- -- -- -- t TO Min 59.6 -- t cyc +20 8, 5 15 5 15 3 Max -- 10 -- -- -- -- -- 30 5.0 V 25MHz Min 40 -- t cyc +12 5 8 3 8 3 Max -- 5 -- -- -- -- -- 20 Unit ns ns ns ns ns ns ns ns
NOTES: 1. Specification #4 for 16.78 MHz @ 3.3 V 0.3 V will be 8 ns.
1 CLKOUT 2 TIN TGATE 3 3 2
Figure 12-16. Timer Module Clock Signal Timing Diagram
MOTOROLA
MC68341 USER'S MANUAL
12-23
CLKOUT 4 TIN 6 TGATE 8 TOUT 7 5
Figure 12-17. Timer Module Signal Timing Diagram
12-24
MC68341 USER'S MANUAL
MOTOROLA
12.10 SERIAL MODULE ELECTRICAL SPECIFICATIONS - PRELIMINARY
(GND = 0 Vdc, TA = 0 to 70C; see numbered notes; see Figures 12-18-12-21) 3.3 V or 5.0 V 16.78 MHz Num. 1 2 32 4 5 6 7 8 91 10 Characteristic CLKOUT Cycle Time Clock Rise or Fall Time Clock Input (X1 or SCLK ) Synchronizer Setup Time Clock Input (X1 or SCLK ) Synchronizer Hold Time TxD Data Valid from CLKOUT High X1 Cycle Time X1 High or Low Time SCLK High or Low Time, Asynchronous (16x) Mode SCLK High Time, Synchronous (1x) Mode SCLK Low Time, Synchronous (1x) Mode Symbol t cyc t rf t CS t CH t VLD t X1 t X1HL t AHL t SH t SL Min 59.6 -- 8, 5 15 Max -- 10 -- -- 0.5 t cyc 2.25 t cyc 0.55 t cyc + 0.75(tCS + t CH ) t cyc + t CS + t CH t cyc (Gx) + tCS (Gx) + tCH (Gx) greater of ({1.5tcyc (Tx) + t CS (Tx) + t VLD (Tx)} + 0.5tcyc (Rx) + t CS (Rx) + t CH (Rx)}) or t SH 1.5tcyc (Tx) + t CS (Tx) + t VLD (Tx) 0.5tcyc (Rx) + t CS (Rx) + t CH (Rx) 0.5tcyc (Rx) + t CS (Rx) + t CH (Rx) Min 40 -- 5 8 5.0 V 25.16 MHz Max -- 5 -- -- Unit ns ns ns ns Max Min Min Min Min Min
11 12 13
TxD Data Valid from SCLK Low, Synchronous (1x) Mode RxD Setup Time to SCLK High, Synchronous (1x) Mode RxD Hold Time from SCLK High, Synchronous (1x) Mode
tT x D tR x S tR x H
Max Min Min
NOTES: 1. Asynchronous operation numbers take into account a receiver and transmitter operating at different clock frequencies. (Rx) refers to receiver value. (Tx) refers to transmitter value. (Gx) refers to the value that is greater, either receiver or transmitter. 2. Specification #3 for 16.78 MHz @ 3.3 V 0.3 V will be 8 ns.
1
CLKOUT 5
TxD
Figure 12-18. Serial Module General Timing Diagram
MOTOROLA
MC68341 USER'S MANUAL
12-25
6 2 2
X1
7
7
Figure 12-19. Serial Module Asynchronous Mode Timing (X1)
2 SCLK (16x)
2
8
8
Figure 12-20. Serial Module Asynchronous Mode Timing (SCLK-16X)
10 2 SCLK (1x) 2
9
11
TxD 13 12 RxD
Figure 12-21. Serial Module Synchronous Mode Timing Diagram
12-26
MC68341 USER'S MANUAL
MOTOROLA
12.11 QSPM ELECTRICAL SPECIFICATIONS - PRELIMINARY
(GND = 0 Vdc, TA = 0 to 70C; see Figures 12-22-12-25) Num Function Operating Frequency Master Slave 1 Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock (SCK) High or Low Time Master Slave Sequential Transfer Delay Master Slave (Does Not Require Deselect) Data Setup Time (Inputs) Master Nominal 50 Slave Nominal 50 Data Hold Time (Inputs) Master Nominal 50 Slave Nominal 50 Access Time Slave MISO Disable Time Slave Data Valid (after SCK Edge)* Master Slave Data Hold Time (Outputs) Master Slave Rise Time* Outputs (SCK, MOSI, MISO, PCS1-PCS0) Inputs (SCK, MOSI, MISO, SS) Nominal 50 -- -- 0 0 -- -- -- -- TBD TBD TBD TBD TBD TBD TBD TBD ns ns ns ns ns s ns s Min DC DC 4 TBD 2 TBD 1/2 TBD 2 2 17 13 TBD TBD TBD TBD -- -- 1/2 Max 1/4 1/4 510 -- 128 -- 1/2 -- 255 -- 8192 -- -- -- -- -- 1/4 SCK SCK Unit System Clock Frequency System Clock Frequency System Clocks System Clocks System Clocks System Clocks SCK SCK System Clocks System Clocks System Clocks System Clocks ns ns ns ns
2
3
4
5
6
7
8 9 10
11
12
13
Fall Time* Outputs (SCK, MOSI, PCS1-PCS0, MISO) Inputs (SCK, MOSI, MISO, SS) *Assumes 200 pF load on all QSPI pins
MOTOROLA
MC68341 USER'S MANUAL
12-27
3 PCS1-PCS0 OUTPUT 5 13 12 SCK CPOL 0 OUTPUT 4 SCK CPOL 1 OUTPUT 6 MISO INPUT MSB IN 11 MOSI OUTPUT PD MSB OUT 13 BIT 6-1 1
2
4 7 12 BIT 6-1 LSB IN 10
13 MSB IN
LSB OUT
PORT DATA 12
MSB OUT
Figure 12-22. QSPI Timing Master, CPHA 0
3 PCS1-PCS0 OUTPUT 1 13 12 SCK CPOL 0 OUTPUT 4 SCK CPOL 1 OUTPUT 4 12 MISO INPUT MSB IN BIT 6-1 11 MOSI OUTPUT PORT DATA MSB OUT 13 BIT 6-1 LSB IN 10 LSB OUT PORT DATA 12 1 7 5
2
13 6 MSB
MSB
Figure 12-23. QSPI Timing Master, CPHA 1
12-28
MC68341 USER'S MANUAL
MOTOROLA
3 SS INPUT 13 SCK CPOL 0 INPUT 4 SCK CPOL 1 INPUT 4 8 MISO OUTPUT MSB OUT 7 6 MOSI INPUT MSB IN BIT 6-1 LSB IN MSB IN 11 BIT 6-1 12 11 10 LSB OUT 12 PD 13 9 13 1 12 5
2
MSB OUT
Figure 12-24. QSPI Timing Slave, CPHA 0
SS INPUT 1 SCK CPOL 0 INPUT 2 SCK CPOL 1 INPUT 8 10 MISO OUTPUT PD 7 6 MOSI INPUT MSB IN BIT 6-1 LSB IN SLAVE MSB OUT 10 BIT 6-1 11 SLAVE LSB OUT 9 4 4 12 13
5
4
3
4
13
12
PD
Figure 12-25. QSPI Timing Slave, CPHA 1
MOTOROLA
MC68341 USER'S MANUAL
12-29
12.12 IEEE 1149.1 ELECTRICAL SPECIFICATIONS
(GND = 0 Vdc, TA = 0 to 70C; see Figures 12-26--12-28) 3.3 V or 5.0 V 16.78 MHz Num. 1 2 3 6 7 8 9 10 11 12 13 Characteristic TCK Frequency of Operation TCK Cycle Time in Crystal Mode TCK Clock Pulse Width Measured at 1.5 V TCK Rise and Fall Times Boundary Scan Input Data Setup Time Boundary Scan Input Data Hold Time TCK Low to Output Data Valid TCK Low to Output High Impedance TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK Low to TDO Data Valid TCK Low to TDO High Impedance Min 0 59.6 28 0 16 26 0 0 15 15 0 0 Max 16.78 -- -- 5 -- -- 40 60 -- -- 25 25 5.0 V 25.16 MHz Min 0 40 18 0 10 18 0 0 10 10 0 0 Max 25 -- -- 3 -- -- 26 40 -- -- 16 16 Unit MHz ns ns ns ns ns ns ns ns ns ns ns
1 2 TCK VIH VIL 3 3 2
Figure 12-26. Test Clock Input Timing Diagram
12-30
MC68341 USER'S MANUAL
MOTOROLA
TCK
VIH VIL 6 7
DATA INPUTS 8 DATA OUTPUTS 9 DATA OUTPUTS 8 DATA OUTPUTS
INPUT DATA VALID
OUTPUT DATA VALID
OUTPUT DATA VALID
Figure 12-27. Boundary Scan Timing Diagram
TCLK VIL 10 TDI TMS 12
VIH
11
INPUT DATA VALID
TDO 13
OUTPUT DATA VALID
TDO 12 TDO OUTPUT DATA VALID
Figure 12-28. Test Access Port Timing Diagram
MOTOROLA
MC68341 USER'S MANUAL
12-31
SECTION 13 ORDERING INFORMATION AND MECHANICAL DATA
This section contains ordering information, pin assignments and package dimensions of the MC68341.
13.1 STANDARD MC68341 ORDERING INFORMATION
Supply Voltage 5.0 V 5.0 V 3.3 V Package Type Plastic Quad Flat Pack FT Suffix Plastic Quad Flat Pack FT Suffix Plastic Quad Flat Pack FT Suffix Frequency (MHz) 0 - 25 0 - 16.78 0 - 16.78 Temperature 0C to +70C 0C to +70C 0C to +70C Order Number MC68341FT25 MC68341FT16 MC68341FT16V
MOTOROLA
MC68341 USER'S MANUAL
13-1
13.2 PIN ASSIGNMENT -- PLASTIC SURFACE MOUNT 13.2.1 160-Lead Plastic Quad Flat Pack (FT Suffix)
VCC AS68K VCC LWE UWE LDS UDS CS0/AVEC CS1 CS2 CS3 CS4 CS5 CS6 CS7 DONE2 DACK2 DREQ2 DONE1 DACK1 DREQ1 X1 GND VCC X2 SCLK CTSB RTSB TxDB RxDB TxRDYA RxRDYA CTSA RTSA TxDA RxDA TIN/RDYB TOUT TGATE/RDYA VCC GND D0 D1 D2 D3 VCC GND D4 D5 D6 D7 D8 D9 D10 D11 VCC GND D12 GND D13 D14 D15 A24/PORTA A25/IACK1 A26/IACK2 A27/IACK3 VCC GND A28/IACK4 A29/IACK5 A30/IACK6 A31/IACK7 A0 DSACK0 DSACK1 IRQ7 IRQ6 IRQ5 IRQ4 GND 121 81
MC68341FT (TOP VIEW)
160 1
41
GND A1 A2 A3 GND VCC A4 A5 A6 A7 A8 A9 A10 GND VCC A11 A12 A13 GND A14 A15 A16 GND VCC A17 A18 A19 A20 A21 A22 A23 GND VCC FC0 FC1 FC2 FC3 PCS0 PCS1 GND
13-2
VCC IRQ3 IRQ2 IRQ1 RMC/RTCOUT R/W SIZ1 SIZ0 DS AS BGACK BG BR BSW VBAT BERR HALT RESET GND CLKOUT VCC XFC VCC EXTAL VCCSYN XTAL EXTCLK MODCK IPIPE IFETCH BKPT FREEZE TCK TMS TDI TDO QSCLK MOSI MISO VCC
MC68341 USER'S MANUAL
MOTOROLA
13.3 PACKAGE DIMENSIONS 13.3.1 FT Suffix
MOTOROLA
MC68341 USER'S MANUAL
13-3
section 1 CD-I, 1-1 section 2 Address Space, 2-8 Spaces, 2-6, 2-8 Strobe Signal, 2-3, 2-6 Autovector Signal, 2-3 Breakpoint Signal, 2-12 Bus Error Signal, 2-3, 2-10 Bus Signals, 2-3, 2-5, 2-6 Chip Select, 2-3, 2-8 Data Bus Signals, 2-3, 2-6, 2-7, 2-9 Strobe Signal, 2-3, 2-7 DMA Acknowledge Signals, 2-4, 2-13 Done Signals, 2-4, 2-13 Request Signals, 2-4, 2-12 Transfer Type, 2-13 EXTAL Pin, 2-11 FREEZE Signal, 2-4, 2-12 Function Code Encoding, 2-8 Signals, 2-8 Halt Signal, 2-3, 2-10 Instruction Fetch Signal, 2-4, 2-11 Pipe Signal, 2-4, 2-12 Interrupt Request Signals, 2-9 MODCK Signal, 2-5, 2-11 Port B Functions, 2-9 Read-Modify-Write Signal, 2-10 Read/Write Signal, 2-3, 2-7 Receive Data Signal, 2-4, 2-14 Receiver Ready Signal, 2-4, 2-14 Reset
MOTOROLA MC68840 USER'S MANUAL 9-1
Signal, 2-3, 2-10 Serial Clock Signals, 2-4, 2-12, 2-15 Size Signal Encoding, 2-8 Signals, 2-3, 2-8, 2-9 TCK Signal, 2-5, 2-16 TDI Signals, 2-5 TDO Signals, 2-5, 2-16 Timer Gate Signals, 2-4, 2-5, 2-15 Input Signal, 2-3, 2-5, 2-15, 2-16 Output Signal, 2-3, 2-5, 2-16 TMS Signal, 2-5, 2-16 Transmit Ready Signal, 2-4, 2-14 VCCSYN, 2-11 X1 Signal, 2-4, 2-13 X2 Signal, 2-4, 2-13 XFC Pin, 2-5, 2-11 XTAL Pin, 2-5, 2-11
section 3
section 4 Address Mask Register, 4-1--4-2, 4-15--4-16, 4-32--4-33, 4-48 Space Bits, 4-22 Spaces, 4-16, 4-22, 4-32, 4-35 Autovector Register, 4-5, 4-20, 4-25, 4-47 Signal, 4-6 Base Address Bits, 4-22, 4-32 BME Bit, 4-6, 4-48 Chip Select, 4-1--4-2, 4-15--4-17, 4-20, 4-31--4-36, 4-47--4-50 Overlapped, 4-16, 4-36 Programming Example, 4-36 Registers, 4-31, 4-35 Signals, 4-1, 4-31 CLKOUT Signals, 4-1, 4-9, 4-11--4-15, 4-18, 4-27, 4-31, 4-46--4-47 Clock Operating Modes, 4-9 Synthesizer, 4-1--4-2, 4-9, 4-25
9-2 MC68840 USER'S MANUAL MOTOROLA
Synthesizer Control Register, 4-20, 4-29, 4-47, 4-50 Crystal Oscillator, 4-10 DBF Bit, 4-6, 4-25 DBFE Bit, 4-6, 4-27, 4-48 DD Bit, 4-16, 4-33 Double Bus Fault, 4-4 Monitor, 4-1, 4-4, 4-6, 4-18--4-19, 4-25, 4-27, 4-48--4-49 DSACK Signals, 4-2, 4-4, 4-6, 4-16--4-17, 4-33--4-34 EBI, 4-2, 4-17, 4-20, 4-24, 4-36 Error Signal, 4-4 EXTAL Pin, 4-7--4-9, 4-15, 4-27 External Bus Interface, 4-17, 4-36 Reset, 4-25 FC Bit, 4-16 FCM Bit, 4-16 FREEZE, 4-3, 4-19, 4-23 Frequency Divider, 4-12 Global Chip Select, 4-15--4-16, 4-33 Halt Signal, 4-4, 4-6, 4-19 IACK Signals, 4-17, 4-36--4-37 IEEE 1149.1, 4-1--4-2 Internal Autovector, 4-47 Bus Monitor, 4-1, 4-4, 4-6, 4-19, 4-27 DSACK Signal, 4-16, 4-33--4-35 Interrupt Arbitration, 4-3--4-6, 4-24, 4-39, 4-47, 4-50 Loss of Input Signal, 4-9, 4-11, 4-31 Periodic Interrupt Control Register, 4-7, 4-28, 4-48 Timer, 4-1, 4-4, 4-7, 4-9, 4-18--4-19, 4-23, 4-47--4-48, 4-50 Timer Register, 4-28--4-29, 4-48 Periodic Timer Period Calculation, 4-8 Phase Comparator, 4-12 Phase-Locked Loop, 4-9 PIRQL Bit, 4-7 PIV Bit, 4-7 Port A Data Direction Register, 4-36--4-37 Data Register, 4-36--4-37 Pin Function, 4-17 Pin Assignment Register, 4-1--4-2, 4-17, 4-36
MOTOROLA MC68840 USER'S MANUAL 9-3
Port B Data Direction Register, 4-37--4-38 Data Register, 4-37--4-38 Pin Assignment Register, 4-5, 4-17--4-18, 4-37 Port C Pin Assignment, 4-20 Pin Assignment Register, 4-38, 4-43 Port Size, 4-2, 4-16, 4-34, 4-36 PS Bit, 4-16 Real-Time Clock, 4-1, 4-9 Reset Status Register, 4-4, 4-6, 4-20, 4-25 RSTEN Bit, 4-12, 4-25, 4-47 Show Cycle, 4-3, 4-5, 4-24, 4-50 SIM40, 4-28 Simultaneous Interrupt, 4-28 SLIMP Bit, 4-11 SLOCK, 4-12, 4-30--4-31 Software Interrupt Vector Register, 4-7, 4-26, 4-48 Service Register, 4-7, 4-27, 4-29 Service Routine, 4-7 Timeout, 4-4, 4-7, 4-26--4-27 Watchdog, 4-1, 4-4, 4-6--4-7, 4-9, 4-18--4-19, 4-23, 4-25--4-29, 4-47--4-50 Watchdog Clock Rate, 4-7 Spurious Interrupt Monitor 4-1, 4-4, 4-6, 4-18-- 4-19 STEXT Bit, 4-18, 4-47 STOP Instruction, 4-18 STP Bit, 4-18 STSIM Bit, 4-15, 4-31 SUPV Bit, 4-24, 4-47 SWE Bit, 4-29, 4-48 SWP Bit, 4-7, 4-26, 4-48 SWRI Bit, 4-7, 4-48 SWT Bit, 4-7, 4-27 System Configuration and Protection, 4-1--4-5, 4-23 Configuration and Protection Operation, 4-3 Protection and Control Register, 4-4 VCCSYN, 4-9--4-12, 4-46 Wait States, 4-1, 4-16--4-17, 4-33--4-34, 4-36, 4-50 WP Bit, 4-16 XFC Pin, 4-12 XTAL Pin, 4-9
9-4
MC68840 USER'S MANUAL
MOTOROLA
section 5 A-Line Instructions, 5-45, 5-58, 5-61, 5-107 A/D Bit, 5-71 Field, 5-71 Register, 5-74--5-75 A/D Register, 5-74 Address Error Exception, 5-36, 5-43, 5-47 Register, 5-2, 5-5--5-7, 5-11, 5-36, 5-56, 5-65, 5-71, 5-76, 5-95--5-97 Alternate Function Code Registers, 5-6 Arithmetic/Logic Instruction Timing Table, 5-101 B0, 5-51, 5-56 B1, 5-51 Background, 5-35 Background Debug Mode, 5-61--5-63, 5-65 Command Execution, 5-65--5-66 Command Summary, 5-74 Serial Interface, 5-65--5-67, 5-74, 5-82 BDM Sources, 5-64 BERR Signal, 5-43 BGND Instruction, 5-64--5-65 Binary-Coded Decimal Extended Instructions Timing Table, 5-103 Instructions, 5-24 Bit Manipulation Instructions, 5-23 Timing Table, 5-105 BKPT Signal, 5-2, 5-63--5-64, 5-66 BKPT_TAG, 5-70 Breakpoint Exception, 5-45, 5-51, 5-64 Breakpoint Instruction, 5-2, 5-44 Bus Error Exception, 5-36, 5-43, 5-50--5-51, 5-53--5-54, 5-57 Bus Controller, 5-88 Calculate Effective Address Instruction Timing Table, 5-98 CALL Command, 5-83 Change of Flow, 5-2, 5-47, 5-87, 5-89 Changing Privilege Level, 5-36 CLKOUT Signal, 5-67, 5-85 Code Compatibility, 5-1, 5-5 Command Format, 5-74--5-82, 5-84--5-85 Sequence Diagram, 5-72--5-73 Compare Register, 5-9 Compressed Table, 5-29--5-30
MOTOROLA MC68840 USER'S MANUAL 9-5
Condition Branch Instruction Timing Table, 5-105 Condition Code Register, 5-9, 5-12, 5-18, 5-26 Condition Codes, 5-2, 5-7, 5-12, 5-15, 5-17--5-18, 5-22, 5-25, 5-27, 5-87--5-88 Condition Test Instructions, 5-18, 5-27 Control Instruction Timing Table, 5-106 CPU32 Block Diagram, 5-3 Privilege Levels, 5-6, 5-35 Processing States, 5-34--5-35 Programming Model, 5-1, 5-6 Serial Logic, 5-66--5-67, 5-69 Stack Frames, 5-34, 5-38--5-39 Current Instruction Program Counter, 5-65 Data Movement Instructions, 5-8, 5-13, 5-19 Registers, 5-1, 5-6--5-7, 5-11, 5-23, 5-27, 5-71, 5-74--5-75, 5-93 DBcc Instruction, 5-3 Deterministic Opcode Tracking, 5-61--5-62, 5-85 Double Bus Fault, 5-41, 5-54, 5-64--5-65 DSCLK Signal, 5-66--5-68, 5-70--5-71 DSI Signal, 5-66--5-67 DSO Signal, 5-68 Dump Memory Block, 5-74 Dump Memory Block Command, 5-79 Effects of Wait States on Instruction Timing, 5-90 Error Exception, 5-43 Error Stack Frame, 5-50, 5-58--5-59 Error Stack Frames, 5-59 Exception Handler, 5-10, 5-35, 5-39--5-40, 5-48--5-51, 5-53--5-57 Priorities, 5-39 Processing, 5-4, 5-7, 5-35--5-36, 5-38--5-41, 5-43--5-48, 5-50, 5-52, 5-54, 5-57, 563, 5-87 Fault, 5-43--5-54 Faults, 5-50, 5-52 Sequence, 5-36, 5-38, 5-43--5-47 Stack Frame, 5-54, 5-57 Exception Handler, 5-51 Exception Processing, 5-44, 5-48, 5-59 Exception Vectors, 5-44 Exception-Related Instructions and Operands Timing Table, 5-107 External Exceptions, 5-38 F-Line Instructions, 5-45, 5-58, 5-61, 5-107 Fault Address Register, 5-65 Correction, 5-3, 5-55--5-57, 5-64
9-6 MC68840 USER'S MANUAL MOTOROLA
Recovery, 5-50, 5-55, 5-57, 5-65 Types, 5-52 Fetch Effective Address Instruction Timing Table, 5-97 Fill Memory Block Command, 5-74, 5-80 Format Error Exception, 5-45, 5-50 Four-Word Stack Frame, 5-58--5-59 GO Command, 5-66 Hardware Breakpoints, 5-45, 5-58, 5-61, 5-63 IFETCH Signal, 5-62, 5-66, 5-85, 5-87 Immediate Arithmetic/logic Instruction Table, 5-102 IN, 5-50, 5-51 IN Bit, 5-51 Instruction Cycles, 5-95 Execution Overlap, 5-89, 5-93 Execution Time Calculation, 5-91, 5-100, 5-102, 5-106--5-107 Head, 5-89, 5-91, 5-93, 5-95--5-108 Pipeline Operation, 5-85--5-86 Stream Timing Examples, 5-92 Tail, 5-89, 5-91--5-96 Integer Arithmetic Operations, 5-20--5-21 Internal Exceptions, 5-38 Interrupt Exception, 5-4, 5-38 IPIPE Signal, 5-62, 5-66, 5-85--5-87 LG Bit, 5-55 Microbus Controller, 5-88--5-89 Microsequencer Operation, 5-87--5-89 MOVE Instruction Timing Table, 5-99 MOVEM Faults, 5-50, 5-54 Multiprocessor System, 5-50, 5-59 Negative Tails, 5-92, 5-94 No Operation Command, 5-9, 5-34, 5-74, 5-84 Opcode Tracking in Loop Mode, 5-87 Operand Size Field, 5-71, 5-79--5-80 Operand Faults, 5-54 Operation Field, 5-71 Prefetch Controller, 5-87--5-89 Prefetch Faults, 5-51, 5-54 Privilege Violations, 5-38, 5-46 Program Control Instructions, 5-24, 5-27 Program Counter, 5-1, 5-5, 5-12, 5-37, 5-58, 5-60--5-61, 5-65, 5-76 Programming Mode CPU32, 5-6 Programming Model
MOTOROLA MC68840 USER'S MANUAL 9-7
CPU32, 5-1 R/W Field, 5-71 Read A/D Register Command, 5-74 Memory Location Command, 5-72, 5-74, 5-77 Modify Write Cycle, 5-51 System Register Command, 5-65, 5-74--5-75 Read-Modify-Write Cycle, 5-51 Register Field, 5-11, 5-71, 5-76--5-77 Indirect Addressing Mode, 5-5 Released Write, 5-43--5-44, 5-51--5-53, 5-55, 5-58, 5-65 Reset Exception, 5-35, 5-38, 5-40--5-41 Instruction, 5-36, 5-41, 5-74, 5-84 Peripherals Command, 5-74, 5-84 RESET Signal, 5-41 Reset Vector, 5-4, 5-37--5-38 Return from Exception, 5-9, 5-49, 5-108 Return Program Counter, 5-60, 5-65 Returning from Background Mode, 5-66 RM Bit, 5-51, 5-53 RR Bit, 5-51--5-52, 5-54--5-55 RTE, 5-51 RTE Instruction, 5-36, 5-39, 5-45, 5-49, 5-50, 5-55--5-57 RW Bit, 5-52--5-53 Save and Restore Operations Table, 5-108 Serial Interface Timing, 5-69 State Machine, 5-67--5-68 Serial Interface, 5-65 Shift and Rotate Instruction Timing Table, 5-104 Instructions, 5-22, 5-104 Single Operand Instruction Table, 5-103 Six-Word Stack Frame, 5-54, 5-56, 5-58 SIZ, 5-52 Software Breakpoints, 5-44, 5-61 Stack Frames, 5-34, 5-39, 5-49, 5-57--5-58 Stack Pointer, 5-59 Status Register, 5-4, 5-8--5-9, 5-12, 5-58, 5-60--5-61, 5-76 Surface Interpolation with Tables, 5-34 System Control Instructions, 5-25 Table Lookup and Interpolate (TBL) Instruction, 5-2, 5-9--5-10
9-8 MC68840 USER'S MANUAL MOTOROLA
TP Bit, 5-50 TR Bit, 5-51 Trace Exception, 5-40, 5-44, 5-47--5-48, 5-51, 5-53, 5-55, 5-58 Mode, 5-7, 5-47, 5-61 Tracing, 5-38, 5-40--5-41, 5-44, 5-47--5-49, 5-61 Transition to Background Mode, 5-35 Trap Instruction, 5-37, 5-40, 5-44 Unimplemented Instructions, 5-9--5-10, 5-45--5-46, 5-61 User Privilege Level, 5-7, 5-36 Using Table Lookup and Interpolate Instructions, 5-10 Vector Base Register, 5-4, 5-44, 5-76 Vector Numbers, 5-4, 5-38, 5-49 Virtual Memory, 5-2, 5-56 Word Operands, 5-19, 5-97--5-100, 5-102--5-103, 5-106 Write A/D Register Command, 5-74--5-75 Memory Location Command, 5-53 System Register Command, 5-74, 5-76 Write Pending Buffer, 5-88 section 6 Burst Request Mode, 6-6 Bus Arbitration, 6-19 Byte Transfer Count Register (BTC), 6-16 Byte Transfer Counter Register (BTC), 6-25 Channel Control Register (CCR), 6-25 Channel Example Configuration Code, 6-40 Channel Status Register (CSR), 6-29 Channel Termination, 6-21 Control Register (CCR), 6-5 Cycle Steal Request Mode, 6-6 Data Holding Register (DHR), 6-13 Destination Address Register (DAR), 6-30 DHR, 6-36 Direct Memory Access (DMA) Controller Module, 6-1 DMA Block Diagram, 6-1 Burst Request Mode, 6-6 Bus Arbitration, 6-19 Channel Example Configuration code, 6-40 Channel Initialization, 6-36 Channel Termination, 6-21 Channels, 6-2 Connections to Serial Module, 6-7
MOTOROLA MC68840 USER'S MANUAL 9-9
Cycle Steal Request Mode, 6-6 Dual-Address Mode, 6-2 External Request, 6-6 Features, 6-1 Initialization, 6-19 Internal Request, 6-5 Interrupt Service Mask (ISM) Level, 6-2 Interrupts, 6-21 Programmer's Model, 6-23 Purpose, 6-2 Registers, 6-23 Requests, 6-2 Signals, 6-4 Single-Address Mode, 6-2 DMA Acknowledge (DACK1, DACK2), 6-4 DMA Done (DONE1,DONE2), 6-4 DMA Request (DREQ1, DREQ2), 6-4 Dual Address Read Cycle, 6-13 Transfer Mode, 6-8, 6-13 Write cycle, 6-16 Dual-Address Mode, 6-2, 6-39 Encoding Address Space, 6-31 BBx, 6-28 DSIZEx, 6-27 FRZ0, 6-33 FRZ1, 6-33 REQx, 6-28 SSIZEx, 6-27 Fast Termination, 6-21, 6-22 Function Code Register (FCR), 6-31 Handshake Signals, 6-8 Interrupt Register (INTR), 6-32 Interrupt Service Mask (ISM) Level, 6-2 Interrupts, 6-21 Mode Burst Request Mode, 6-6 Cycle Steal Request Mode, 6-6 Dual-Address Transfer Mode, 6-8, 6-13 Single-Address Transfer Mode, 6-8 Module Base Address Register (MBAR), 6-24 Module Configuration Register (MCR), 6-23, 6-33 Read Dual-Address Read Cycle, 6-13 Single-Address Source (Read) Cycle, 6-8 Register(s)
9-10 MC68840 USER'S MANUAL MOTOROLA
Byte Transfer Count Register (BTC), 6-16 Byte Transfer Counter Register, 6-25 Channel Control Register (CCR), 6-25 Channel Status Register, 6-29 Control Register (CCR), 6-5 Data Holding Register (DHR), 6-13 Destination Address Register (DAR), 6-30 DMA Module, 6-23 Function Code Register (FCR), 6-31 Interrupt Register (INTR), 6-32 Module Base Address Register (MBAR), 6-24 Module Configuration Register (MCR), 6-23, 6-33 Source Address Register (SAR), 6-35 RESET Instruction, 6-24 Signal(s) DMA Acknowledge (DACK1, DACK2), 6-4 DMA Done (DONE1, DONE2), 6-4 DMA Request (DREQ1, DREQ2), 6-4 SIM41, 6-22 Single Address Destination (Write) Cycle, 6-11 Source (Read) Cycle, 6-8 Transfer Mode, 6-8 Single-Address Mode, 6-2, 38 Source Address Register (SAR), 6-35 Timing Dual-Address Read (Cycle Steal-Source Requesting), 6-15 Dual-Address Write (Cycle Steal-Destination Requesting), 6-18 Dual-Address Write (External Burst-Destination Requesting), 6-17 Fast Termination Option (Cycle Steal), 6-22 Fast Termination Option (External Burst-Source Requesting), 6-23 Single-Address Read (Cycle Steal), 6-10 Single-Address Read (External Burst), 6-9 Single-Address Write (Cycle Steal), 6-12 Single-Address Write (External Burst), 6-11 Transfer, 6-20 Dual-Address Transfer Mode, 6-8, 6-13 Single-Address Transfer Mode, 6-8 Write Dual-Address Write Cycle, 6-16 Single-Address Destination (Write) Cycle, 6-11 section 7 Asynchronous, 7-3, 7-8 Automatic Echo Mode, 7-14 Auxiliary Control Register (ACR), 7-20
MOTOROLA MC68840 USER'S MANUAL 9-11
Baud Rate Generator, 7-3, 7-5, 7-8 Block Mode, 7-13 Bus IMB, 7-17 Channel A Clear-To-Send (CTSA ), 7-7 Channel A Receiver Serial Data Input (RxDA), 7-6 Channel A Status Register (SRA), 7-7 Channel A Transmitter Serial Data Output (TxDA), 7-6 Channel B Clear-To-Send (CTSB), 7-7 Channel B Receiver Serial Data Input (RxDB), 7-6 Channel B Transmitter Serial Data Output (TxDB), 7-6 Channel's Mode Register (MR1), 7-13 Status Register (SR), 7-10 Character Mode, 7-13 Clock-Select Register (CSR), 7-6, 7-20 Command Registers (CR), 7-10, 7-22 Crystal, 7-5 CSR, 7-8 CTS, 7-7, 7-11 Encoding B/Cx, 7-34 CMx, 7-35 FRZx, 7-31 MISCx, 7-23 PMx, 7-34 PT, 7-34 RCSx, 7-21 RCx, 7-25 SBx, 7-36 TCSx, 7-22 TCx, 7-24 External Clock Input (SCLK), 7-3 Clock Signal, 7-5 Input (SCLK), 7-6 FFULLA, 7-8 FIFO stack, 7-13 First-In-First-Out (FIFO) Full Indicator, 7-7 Flowchart Serial Module Programming, 7-43 Framing Error, 7-11 IER, 7-7 IMB, 7-17 Input Port Change Register (IPCR), 7-25 Port Register (IP), 7-26
9-12 MC68840 USER'S MANUAL MOTOROLA
Intermodule Bus (IMB), 7-1 Interrupt Acknowledge Cycle (Serial Module), 7-17 Enable Register (IER), 7-4, 7-27 Level Register (ILR), 7-28 Request (IRQ7-IRQ1), 7-3 Status Register (ISR), 7-3, 7-28 Vector Register (IVR), 7-17, 7-30 ISR, 7-7, 7-8 Local Loopback Mode, 7-14 LPSTOP Instruction, 7-31 MC68681, 7-4 Mode Register 1 (MR1), 7-33 Mode Register 2 (MR2), 7-35 Module Base Address Register (MBAR), 7-18 Module Configuration Register (MCR), 7-31 Multidrop Mode, 7-15 Looping Modes, 7-14 OP0, 7-6 OP1, 7-7 OP4, 7-8 OP6, 7-7 Ouput Port Data Register (OP), 7-6, 7-37 Output Port Control Register (OPCR), 7-38 Parity Error, 7-11 Read Serial Module, 7-17 Receiver Block Diagram, 7-8 Break Condition, 7-12 Buffer (RB), 7-39 Timing, 7-11 Register(s) Auxiliary Control Register (ACR), 7-20 Channel A Status Register (SRA), 7-7 Channel's Mode Register (MR1), 7-13 Channel's Status Register (SR), 7-10 Clock-Select Register (CSR), 7-6, 7-20 Command Register (CR), 7-10, 7-22 CSR, 7-8 IER, 7-7 Input Port Change Register (IPCR), 7-25 Input Port Register (IP), 7-26 Interrupt Enable Register (IER), 7-4, 7-27 Interrupt Level Register (ILR), 7-28 Interrupt Status Register (ISR), 7-3, 7-28 Interrupt Vector Register (IVR), 7-17, 7-30
MOTOROLA MC68840 USER'S MANUAL 9-13
ISR, 7-7, 7-8 Mode Register 1 (MR1), 7-33 Mode Register 2 (MR2), 7-35 Module Base Address Register (MBAR), 7-18 Module Configuration Register (MCR), 7-31 Output Port Control Register (OPCR), 7-38 Output Port Data Register (OP), 7-6, 7-37 Receiver Buffer (RB), 7-39 Status Register (SR), 7-10, 7-39 Transmitter Buffer (TB), 7-11, 7-41 Remote Loopback Mode, 7-14 Request-To-Send (RTS), 7-11 RESET Instruction, 7-18 RTSA, 7-6 RTSB, 7-7 RRDYA, 7-7 Serial Module Automatic Echo Mode, 7-14 Baud Rate Generator, 7-3, 7-5, 7-8 Block Diagram, 7-1 Block Code, 7-13 Channel A, 7-6 Channel B, 7-6 Character Mode, 7-13 Communication Channel, 7-3 Example Configuration Code, 7-50 Features, 7-2 Functional Areas, 7-1 I/O Driver Routines, 7-42 Initialization, 7-42 Initializing, 7-48 Interrupt Acknowledge Cycles, 7-17 Interrupt Handling Routine, 7-42 Local Loopback Mode, 7-14 Looping Modes, 7-14 Multidrop Mode, 7-15 Programming Flowchart, 7-43 Programming Model, 7-4, 7-19 Read Cycles, 7-17 Registers, 7-18 Remote Loopback Mode, 7-14 Signals, 7-4 Write Cycles, 7-17 Signal(s) Channel A Clear-To-Send (CTSA), 7-7 Channel A Receiver Serial Data Input (RxDA), 7-6 Channel A Transmitter Serial Data Output (TxDA), 7-6
9-14 MC68840 USER'S MANUAL MOTOROLA
Channel B Clear-To-Send (CTSB), 7-7 Channel B Receiver Serial Data Input (RxDB), 7-6 Channel B Transmitter Serial Data Output (TxDB), 7-6 Crystal, 7-5 CTSx, 7-7, 7-11 External Clock Signal, 7-5 External Input (SCLK), 7-6 FFULLA, 7-8 Interrupt Request (IRQ7-IRQ1), 7-3 OP0, 7-6 OP1, 7-7 OP4, 7-8 OP6, 7-7 Request-To-Send (RTSx), 7-11 RTSA, 7-6 RTSB, 7-7 RxRDYA, 7-7 TxRDYA, 7-7 X1, 7-5 X2, 7-5 Status Register (SR), 7-39 Synchronous, 7-3, 7-8 Transmitter Block Diagram, 7-8 Buffer (TB), 7-11, 7-41 Timing, 7-10 TRDYA , 7-7 Write Serial Module, 7-17 X1, 7-5 X2, 7-5 section 8 Changing Timer Modes, 8-1 CLK Bit, 8-26 COM Bit, 8-6, 8-8--8-10, 8-12--8-14, 8-16, 8-19, 8-24--8-25 Compare Register, 8-2, 8-17, 8-25--8-29 Configuration Code (Modules) Timer Module, 8-27--8-29 Control Register, 8-4, 8-17, 8-19, 8-26--8-29 Counter Clock, 8-2 Event, 8-2, 8-4 Register, 8-5, 8-17 CPE Bit, 8-9--8-11, 8-14
MOTOROLA MC68840 USER'S MANUAL 9-15
IE Bit, 8-4, 8-7--8-8, 8-19 IMB, 8-1, 8-3, 8-5, 8-16, 8-18 Interrupt Register, 8-16, 8-26 IRQ Bit, 8-4, 8-22 Mode Bits, 8-5, 8-8, 8-10, 8-15 Module Configuration Register, 8-16, 8-26 OC Bits, 8-9, 8-4, 8-21 ON Bit, 8-7 PCLK, 8-15, 8-19--8-21, 8-26--8-27 Period Interrupt Generation, 8-5, 8-7--8-8 Period Measurement, 8-2, 8-12--8-13, 8-21 PO Bits, 8-12--8-14, 8-16, 8-22, 8-24 POT Bits, 8-15, 8-21, 8-27 Preload Register, 8-26--8-27 Programming Model Timer, 8-17 Pulse-Width Measurement, 8-1, 8-11--8-12, 8-21, 8-29 Pulse-Width Modulation, 8-5 Selected Clock, 8-3, 8-10, 8-20--8-21, 8-26, 8-28--8-29 Shadowing, 8-5--8-6 Square-Wave Generation, 8-1, 8-5, 8-28 Status Register, 8-2, 8-22, 8-26--8-27, 8-29 STP Bit, 8-18, 8-22, 8-24--8-25 SUPV Bit, 8-16, 8-26 SWR Bit, 8-19, 8-24, 8-26 System Clock, 8-3, 8-5, 8-13, 8-20, 8-22, 8-24 TC Bit, 8-7--8-8, 8-10, 8-12--8-14, 8-19, 8-22, 8-24--8-25, 8-27 TG Bit, 8-6, 8-8--8-9, 8-11--8-15, 8-26, 8-29--8-30 TGE Bit, 8-6, 8-7, 8-9, 8-12, 8-14, 8-20, 8-23, 8-26 TGL Bit, 8-9, 8-11, 8-13--8-15, 8-29 Time-Out, 8-2, 8-6--8-10, 8-12--8-14, 8-22--8-25 Timer Bypass, 8-15, 8-21 Clock Selection Logic, 8-2--8-3 Gate Signal, 8-5--8-7 Input Signals, 8-5 Prescaler, 8-1, 8-2 Programming Model, 8-17 TO Bit, 8-8--8-10, 8-13 Toggle Mode, 8-6--8-7, 8-9--8-10, 8-21--8-22 Using TGATE as an Input Port, 8-15 TOUT as an Output Port, 8-15 Variable Duty-Cycle Square-Wave Generator, 8-8--8-9, 8-21, 8-25 Variable-Width Single-Shot Pulse Generation, 8-1 Variable-Width Single-Shot Pulse Generator, 8-10--8-11, 8-21
9-16 MC68840 USER'S MANUAL MOTOROLA
Zero Mode, 8-7, 8-21--8-22 section 9 SS , 9-30 Assignable Data Space, 9-2 Bit/Field Quick Reference, 9-6 BITS, 9-18, 9-38, 9-40 Bits Per Transfer, 9-18 BITSE, 9-29, 9-37, 9-38, 9-40 Clock Phase, 9-19 Clock Polarity, 9-19 Coherent Accesses, 9-26 COMD RAM, 9-26 Command RAM (COMD.RAM), 9-27 Completed Queue Pointer, 9-26 CONT, 9-28, 9-38, 9-39 CPHA, 9-19, 9-38, 9-40 CPOL, 9-19, 9-38, 9-40 CPTQP, 9-26, 9-27, 9-30, 9-38 Delay After Transfer, 9-21, 9-29 Delay Before SCK, 9-21 DSCK, 9-29, 9-38, 9-40 DSCKL, 9-21, 9-38 DT, 9-29, 9-38, 9-40 DTL, 9-21 Ending Queue Pointer, 9-23 ENDQP, 9-22, 9-23, 9-28, 9-30, 9-41 Freeze0, 9-9 Freeze1, 9-9 FRZ0, 9-9 FRZ1, 9-9 HALT, 9-24, 9-41 Halt Acknowledge Flag, 9-26 HALTA, 9-22, 9-26 HALTA and MODF Interrupt Enable, 9-24 HMIE, 9-24 IARB, 9-10 ILQSPI, 9-10 Interrupt Level for QSPI, 9-10 Length of Delay After Transfer, 9-21 LOOPQ, 9-24 Master In Slave Out, 9-13 Master Mode, 9-1, 9-37 Master Out Slave In, 9-13 Master Wraparound, 9-38 Master/Slave Mode Select, 9-18
MOTOROLA MC68840 USER'S MANUAL 9-17
MISO, 9-3, 9-13 MISO--Master In Slave Out, 9-12 Mode Fault Flag, 9-25 MODF, 9-22, 9-25, 9-36 MOSI, 9-3, 9-13, 9-37, 9-39 MOSI--Master Out Slave In, 9-12 MSTR, 9-18, 9-30, 9-37, 9-39 New Queue Pointer Value, 9-23 NEWQP, 9-22, 9-23, 9-30, 9-37, 9-39, 9-40 PCS to SCK Delay, 9-21, 9-29 PCS0/SS, 9-12 PCS1, 9-12, 9-13 PCS1, and PCS0, 9-3 PCS1-PCS0/SS, 9-29 Peripheral Chip Select, 9-1, 9-12, 9-13, 9-14, 9-29 Programmable Queue, 9-14 PSC0/SS, 9-13 QDDR, 9-3, 9-37, 9-39 QPAR, 9-3, 9-29, 9-37, 9-39 QPDR, 9-3, 9-29 QSM Block Diagram, 9-16 Master Mode Operation, 9-37 Operating Modes, 9-30 QSPI /Registers, 9-17 SPCR3, 9-24 SPSR, 9-25 QSPI, 9-1 QSPI CONTROL REGISTER 0 (SPCR0), 9-18 QSPI Control Register, 9-1, 9-20 QSPI Control Register 2 (SPCR2), 9-22 QSPI Control Register 3 (SPCR3), 9-24 QSPI Enable, 9-20 QSPI Finished Flag, 9-25 QSPI Loop Mode, 9-24 QSPI Master Operation, 9-32 QSPI Pins, 9-16 QSPI RAM, 9-2, 9-23, 9-26, 9-29, 9-30 QSPI Slave Operation, 9-35 QSPI Submodule, 9-13 QSPI Submodule Diagram, 9-16 QSPM QPDR, 9-11 QSPM Configuration, 9-7 QSPM Configuration Register (QMCR), 9-8 QSPM Data Direction Register, 9-13 QSPM Global Registers, 9-2, 9-8
9-18 MC68840 USER'S MANUAL MOTOROLA
QSPM Interrupt Level Register (QILR), 9-10 QSPM Interrupt Vector Register, 9-11 QSPM Memory Map, 9-2 QSPM Pin Assignment Register, 9-12 QSPM Pin Summary, 9-4 QSPM Pins, 9-3 QSPM Port Data Register, 9-12 QSPM Test Enable, 9-10 QSPM Test Register (QTEST), 9-10 Queue Pointer, 9-15 REC.RAM, 9-26 Receive Data RAM (REC.RAM), 9-27 Registers, 9-4 SCK, 9-3, 9-12, 9-13, 9-37, 9-39 SCK Baud Rate, 9-20 Serial Clock, 9-13 Serial Clock Baud Rate, 9-19 Slave Mode, 9-1, 9-39 Slave Operation, 9-39 Slave Wraparound Mode, 9-41 SPBR, 9-19, 9-20 SPCR0, 9-3, 9-30 SPCR1 9-17, 9-37 SPCR2, 9-18, 9-28, 9-30 SPE, 9-17, 9-20, 9-37, 9-39, 9-41 SPI Bus Master, 9-30 SPI Master Arbitration, 9-37 SPIF, 9-22, 9-25, 9-40, 9-41 SPIFIE, 9-38, 9-41 SPIFIE--SPI Finished Interrupt Enable, 9-22 SPSR, 9-27, 9-30, 9-38, 9-41 STOP, 9-9 SUPV, 9-9 TQSM, 9-10 TRAN.RAM, 9-26 Transfer Delay, 9-15 Transfer Length, 9-15 Transfer Mode, 9-15 Transmit Data RAM (TRAN.RAM), 9-27 TSBD, 9-10 Wired-OR Mode for QSPI Pins, 9-18 WOMQ, 9-3, 9-18, 9-37 Wrap Enable, 9-23 Wrap To, 9-23 Wraparound Transfer Mode, 9-14 WREN, 9-23, 9-39 WRTO, 9-23
MOTOROLA MC68840 USER'S MANUAL 9-19
section 10 Boundary Scan Bit Definitions, 10-4, 10-5 Register, 10-1, 10-2, 10-3, 10-4, 10-11, 10-12 Bypass Register, 10-2, 10-11, 10-12 Cell Types Active-High Output Control Cell Diagram, 10-8 Active-Low Output Control Cell Diagram, 10-9 Bidirectional Data Cell Diagram, 10-9 Input Pin Cell Diagram, 10-8 Output Latch Cell Diagram, 10-7 IEEE 1149.1 Block Diagram, 10-2 Capabilities, 10-1 Control Bits, 10-3, 10-4 Implementation, 10-1 Restrictions, 10-12 Instruction Register, 10-1, 10-2, 10-10, 10-11 TAP Controller, 10-2, 10-3, 10-12, 10-13 TCK Signal, 10-2 TDI Signal, 10-2 TDO Signal, 10-2 Test Access Port, 10-1, 10-2 section 11 Address Access Time, 11-6 Advantages, 11-11 Battery Operation, 11-10 Calculating Frequency-Adjusted Outputs, 11-5, 11-7 CD-I, 11-10 CD-ROM, 11-10 Current Drain, 11-11 EXTAL, 11-1 External Reset, 11-3 Frequency-Adjusted Signal Skew, 11-9 Width, 11-8 Memory Access Times, 11-7 Interfacing, 11-5, 11-10 Phase-Locked Loop (PLL), 11-1
9-20 MC68840 USER'S MANUAL MOTOROLA
Power Consumption, 11-3, 11-10, 11-11 Power Dissipation, 11-11 Power-On Reset (POR), 11-3 Processor Clock Circuitry, 11-1 Propagation Delay, 11-7 Reset Power-On Reset (POR), 11-3 ROM Interface, 11-1, 11-4 RS-232 interface, 11-4 Serial Interface, 11-1, 11-4, 11-5 Signal Relationships to CLKOUT, 11-7 Signal Width, 11-8 Skew Between Outputs, 11-9 Use of Chip Selects, 11-3, 11-4, 11-5, 11-7 Using 8-Bit Boot ROM, 11-5 VCCSYN, 11-2, 11-3 XFC Pin, 11-2, 11-3 XTAL Pins, 11-1 Appendix A
MOTOROLA
MC68840 USER'S MANUAL
9-21

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