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Features
* * * * * * * * * * * * * * * *
Full Range of Matrices up to 490k Cells 0.5 m Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG) 3 and 5 volts operation: single or dual supply mode High Speed Performances: - 640 ps max. NAND2 propagation Delay @5V and FO = 1/4 FO max. - min. 440 MHz Toggle Frequency @4.5V, 230 MHz @2.7V Programmable PLL available on request High System Frequency Skew Control: - 200 MHz max. PLL for Clock Generation @4.5V. - Clock Tree Synthesis Software Low Power Consumption: - 2 W/Gate/MHz @5V - 0.6 W/Gate/MHz @3V Matrices With a max of 484full programmable Pads Standard 3, 6, 12 and 24mA I/Os Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator CMOS/TTL/PCI Interface ESD (2 kV) And Latch-up Protected I/O Wide Selection of MQFPs and CLGA packages up to 564 pins High Noise & EMC Immunity: - I/O with Slew Rate Control - Internal Decoupling - Signal Filtering between Periphery & Core - Application Dependent Supply Routing & Several Independant Supply Sources Delivery in Die Form with 110m pad pitch Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management Cadence, Mentor, Vital & Synopsys Reference Platforms EDIF & VHDL Reference Formats Available In Military and Space Quality Grades (SCC, MIL-PRF-38535) Latch up immune Total dose better than 300 Krads (TM1019.5) QML Q & V with SMD 5962-00B03
Rad Hard 350K used gates 0.5m CMOS Sea of Gates MG2RTP
* * * * * * * *
Description
The MG2RTP series is a 0.5 micron, array based, CMOS product family. Several arrays up to 490k cells cover all system integration needs. The MG2RTP is manufactured using a 0.5 micron drawn, 3 metal layers CMOS process. The MG2RTP series base cell architecture provides high routability of logic with extremely dense compiled memories: RAM and DPRAM. ROM can be generated using synthesis tools. Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery: three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.
Rev. F-23-Aug-01
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MG2RTP
The MG2RTP is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle.
Its Library allows straight forward migration from the MG1, MG1RT, MG2 and MG2RT Sea of Gates.
A netlist based on this library can be simulated as either MG2RTP or MG2RT: for MG2, it must not use SEU free cells. Table 1. List of Available MG2RTP matrix
Type MG2014P MG2044P MG2092P MG2142P MG2204P MG2270P MG2495P* Total Cells 14000 44600 91800 142100 204100 270000 495000 Usable Gates 10500 33400 68900 106600 153100 202200 371300 Maximum I/O 86 146 212 262 312 360 484 Total Pads 103 165 229 281 331 377 501
Note:
(*)contact factory
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Rev. F-23-Aug-01
Libraries
The MG2RTP cell library has been designed to take full advantage of the features offered by both logic and test synthesis tools. Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST methodologies. More complex macro functions are available in VHDL, as example: I2C, UART, Timer,...
Block Generators
Block generators are used to create a customer specific simulation model and metallisation pattern for regular functions like RAM & DPRAM. The basic cell architecture allows one bit per cell for RAM and DPRAM. The main characteristics of these generators are summarised below.
Function
Maximum Size (bits)
bits/word
Typical characteristics (16k bits) @5V access time (ns) Used cells 20 k 23 k
RAM DPRAM
36 k 36 k
1-36 1-36
8 8.6
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MG2RTP
Rev. F-23-Aug-01
MG2RTP
I/O buffer interfacing
I/O Flexibility Inputs
All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator is located close to each buffer. Input buffers with CMOS or TTL thresholds are non inverting and feature versions with and without hysteresis. The CMOS and TTL input buffers may incorporate pull-up or pull down terminators. For special purposes, a buffer allowing direct input to the matrix core is available. Several kinds of CMOS and TTL output drivers are offered: fast buffers with 3, 6, 12 and 24 mA drive at 5V, low noise buffers with 12 mA drive at 5V.
Outputs
Clock generation & PLL
Clock generation
Atmel Wireless & Microcontrollers offers 5 different types of oscillators: 3 high frequency crystal oscillator and 2 RC oscillators. For all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10 ms.
Frequency (MHz) Max 5V Xtal 7M Xtal 50M Xtal 100M RC 10M RC 32M 10 60 120 10 32 Max 3V 6 35 70 10 32 Typical 5V 1.2 7 16 2 3 consumption (mA) 3V 0.4 2 5 1 1.5
PLL
Contact factory.
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Rev. F-23-Aug-01
Power supply & noise protection
The speed and density of the SCMOS3/2RTP technology causes large switching current spikes for example when: * * either 16 high current output buffers switch simultaneously or 10% of the 490 000 gates are switching within a window of 1ns.
Sharp edges and high currents cause some parisitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the settling time of the current and causes voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the MG core matrix, several mechanisms have been implemented inside the MG arrays. Two kinds of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix.
I/O Buffers switching protection
Three features are implemented to limit the noise generated by the switching current: * * * The power supplies of the input and output buffers are separated. The rise and fall times of the output buffers can be controlled by an internal regulator. A design rule concerning the number of buffers connected on the same power supply line has been imposed.
Matrix switching current protection
This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: * * Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. A power supply network has been implemented in the matrix. This solution reduces the number of parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers.
*
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MG2RTP
Rev. F-23-Aug-01
MG2RTP
Power consumption
The power consumption of an MG2RTP array is due to three factors: leakage (P1), core (P2) and I/O (P3) consumption. P = P1 + P2 + P3
Leakage (Standby) Power Consumption
The consumption due to leakage currents is defined as: P1 = (VDD - VSS) * ICCSB * NCELL Where ICCSB is the leakage current through a polarized basic gate and NCELL is the number of used cells.
Core Power Consumption
The power consumption due to the switching of cells in the core of the matrix is defined as: P2 = NCELL * PGATE * CACTIVITY * F Where NCELL is the number of used cells, F the data toggling frequency, which is equal to half the clock frequency for random data and PGATE is the power consumption per cell. PGATE = PCA + PCO
C
ACTIVITY is the fraction of the total number of cells toggling per cycle.
Capacitance Power
PCA = C * (VDD - VSS)2/2 C is the total output capacitance and may be expressed as the sum of the drain capacitance of the driver, the wiring capacitance and the gate capacitance of the inputs. Worst case value: PCA # 1.8 W/gate/MHz @ 5 V
Commutation Power
PCO = (VDD - VSS) * Idsohm Where Idsohm is the current flowing into the driver between supply and ground during the commutation. Idsohm is about 15% of the Pmos saturation current. Worst case value: Pco # 0.7 W/gate/MHz @ 5 V
I/O Power Consumption
The power consumption due to the I/Os is: P3 = Ni * CO * (VDD - VSS)2 * Fi/2 With Ni equals to the number of buffers running at Fi and CO is the output capacitance. Note: If a signal is a clock, Fi = F, if it is a data with random values, Fi = F/4.
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Rev. F-23-Aug-01
Table 2. Typical Power Consumption Example
Matrix Used gates (70%) Frequency Standby Power Iccsb (125C) P1 = (VDD - VSS) * ICCSB * NCELL Core Power Power Consumption per Cell Cactivity P2 = NCELL * PGATE * Cactivity * F I/O Power Total Number of Buffers Number of Outputs and I/O Buffers (NI) Output Capacitance P3 = Ni * CO * (VDD - VSS)2 * Fi/2 Total Power P = P1 + P2 + P3 1.39 W 0.54 W 360 100 50 pF 625 mW 360 100 50 pF 220 mW 2.7 W/Gate/MHz 20% 1026 mW 0.86 W/Gate/MHz 20% 323 mW 1 nA 1 mW 1 nA 0.6 mW MG2270P@5V 190 k 10 MHz MG2270P@3V 190 k 10 MHz
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MG2RTP
Rev. F-23-Aug-01
MG2RTP
Packaging
Atmel Wireless & Microcontrollers offers a wide range of packaging options which are listed below:
Pins** Package Type MLCC min/max 68 84 100 352 349 564 Lead spacing (mils) 50 50 25.6 20 50 50
CERAMIC
MQFP
CLGA*
Note:
For plastic, call factory; this is a customer decision to use plastic packages in environmental conditions which are beyond those for which they have been developed.
* Ceramic Land Grid Array: contact factory. ** contact Atmel local design centers to check the availability of the used matrix and the package.
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Rev. F-23-Aug-01
Design flows & tools
Design Flows and modes A generic design flow for an MG2RTP array is illustrated below.
A top down design methodology is proposed which starts with high level system description and is refined in successive design steps. At each step, structural verification is performed which includes the following tasks: * * * * * * * * * * * Gate level logic simulation and comparison with high level simulation results. Design and test rule check. Power consumption analysis. Timing analysis (only after floor plan). System specification, preferably in VHDL form. Functional description at RTL level. Logic synthesis. Floor planning and bonding diagram generation. Test/Scan insertion, ATG and/or fault simulation. Physical cell placement, JTAG insertion and clock tree synthesis. Routing
The main design stages are:
To meet the various requirements of designers, several interface levels between the customer and Atmel are possible. For each of the possible design modes a review meeting is required for data transfer from the user to Atmel. In all cases the final routing and verifications are performed by Atmel Wireless & Microcontrollers. The design acceptance is formalized by a design review which authorizes Atmel to proceed with sample manufacturing.
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MG2RTP
Rev. F-23-Aug-01
MG2RTP
Figure 1. MG2RT Design Flow
System Specifications
RTL Simulation
Logic synthesis
Floor Plan Bonding diagram
Scan insertion ATG & Fault Simulation
Placement
JTAG insertion Clock Tree Synthesis
Routing
Backannotated Simulation
Sign-off
Samples Manufacturing and Test
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Rev. F-23-Aug-01
Design tool and design kits (DK)
The basic content of a design kit is described in the table below. The interface formats to and from Atmel Wireless & Microcontrollers rely on IEEE or industry standard: * * * * * VHDL for functional descriptions VHDL or EDIF for netlists Tabular, log or .CAP for simulation results SDF (VITAL format) and SPF for back annotation LEF and DEF for physical floor plan information
The design kit supported for several commercial tools are listed below. Design Kit Support * * * * Cadence (VHDL and gate) Mentor (VHDL and gate) Synopsys (VHDL and gate) Vital (VHDL and gate)
Table 3. Design kit Description
Atmel Software Name Third Party Tools * * * * STAR COMET * * PIM MISS *
Design Tool or library Design manual & libraries VHDL library for blocks Synthesis library Gate level simulation library Design rules analyser Power consumption analyser Floor plan library Timing analyser library Package & bonding software Scan path & JTAG insertion ATG & fault simulation library * refer to "Design kits cross reference tables" ATD-TS-WF-R0181
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MG2RTP
Rev. F-23-Aug-01
MG2RTP
Operating characteristics
Absolute Maximum Ratings
Ambient temperature under bias (TA) Military -55 to +125C Junction temperature TJ < TA + 20C Storage temperature -65 to +150C TTL/CMOS: Supply voltage VDD-0.5 V to +6 V I/O voltage -0.5 V to VDD + 0.5 V
Note: Stresses above those listed may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended period may affect device reliability.
DC Characteristics Table 4. DC Characteristics Specified at VDD = +5 V +/- 10%
Symbol VIL
Parameter Input LOW voltage CMOS input TTL input Input HIGH voltage CMOS input TTL input Output low voltage TTL Output high voltage CMOS TTL Schmitt trigger positive threshold CMOS input TTL input Schmitt trigger negative threshold CMOS input TTL input Input leakage No pull up/down Pull up Pull down 3-State Output Leakage current Output Short circuit current IOSP IOSN
Min 0 0
Typ
Max 0.3VDD 0.8
Unit V
Conditions
VIH
0.7 VDD 2.2
VDD VDD 0.4
V
VOL
V
IOL = -12, 6, 3 mA*
VOH
3.9 2.4 3.3 1.5 1.1 0.9 +/-5 -100 300 +/-5 48 36 1.0 0.39 10.0 0.53
V
IOH = -12, 6, 3 mA*
VT+
V
VT-
V
IL
-44 75
+/-1 -66 118 +/-1
A A A A BOUT12 mA mA nA A/MHz VOUT = 4.5V VOUT = VSS
IOZ IOS ICCSB ICCOP
Leakage current per cell Operating current per cell
* According buffer: Bout12, Bout6, Bout3, VDD = 4.5V
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Rev. F-23-Aug-01
Table 5. DC Characteristics Specified at VDD = +3 V +/- 10%
Symbol Parameter Input LOW voltage LVCMOS input LVTTL input Min Typ Max Unit Conditions
VIL
0 0
0.3VDD 0.8
V
VIH
Input HIGH voltage LVCMOS input Output LOW voltage TTL Output HIGH voltage TTL Schmitt trigger positive threshold LVCMOS input LVTTL input LVTTL input
0.7VDD 2.0
VDD VDD
V
VOL
0.4 2.4
V
IOL = -6, 3, 1.5 mA*
VOH
V
IOH = -4, 2, 1 mA*
VT+
2 1
V
VT-
Schmitt trigger negative threshold CMOS input TTL input
0.8 0.7
V
IL
Input leakage up/down
No pull Pull up Pull down -16 31 -20 42
+/-1 -50 140 +/-1
A A A A BOUT12
IOZ
3-State Output Leakage current Output Short circuit current IOSP IOSN
IOS
24 12 0.6 0.2 5
m mA nA A/MHz
VOUT = VDD VOUT = VSS
ICCSB ICCOP
Leakage current per cell Operating current per cell
* According buffer: Bout12, Bout6, Bout3
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MG2RTP
Rev. F-23-Aug-01
MG2RTP
AC Characteristics
Table 6. AC Characteristics TJ = 25C, Process typical (all values in ns)
Buffer Description Load Transition 5V BOUT12 Output buffer with 12 mA drive 60pf Tplh Tphl BOUT3 Output buffer with 3 mA drive 60pf Tplh Tphl BOUTQ Low noise output buffer with 12 mA drive 60pf Tplh Tphl B3STA3 3-state output buffer with 3 mA drive 60pf Tplh Tphl B3STA12 3-state output buffer with 12 mA drive 60pf Tplh Tphl B3STAQ Low noise 3-state output buffer with 12 mA drive 60pf Tplh Tphl 3.332 2.131 5.358 3.436 3.742 5.515 5.468 3.510 3.475 2.195 3.703 7.320 VDD 3V 5.277 2.842 8.512 4.440 5.696 8.616 8.622 4.617 5.426 2.990 5.776 11.711
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Rev. F-23-Aug-01
Cell
Description
Load
Transition 5V
VDD 3V 1.430 1.085 1.423 1.081 0.864 0.487
BINCMOS
CMOS input buffer
15 fan
Tplh Tphl
0.936 0.776 0.983 0.687 0.564 0.382
BINTTL
TTL input buffer
16 fan
Tplh Tphl
INV
Inverter
12 fan
Tplh Tphl
NAND2 2 - input NAND 12 fan Tplh 0.726 1.076
Tphl FDFF D flip-flop, Clk to Q 8 fan Tplh Tphl Ts Th BUF4X High drive internal buffer 51 fan Tplh Tphl NOR2 2-Input NOR gate 8 fan Tplh Tphl OAI22 4-input OR AND INVERT gate 8 fan Tplh Tphl OSFF D flip-flop with scan input, Clk to Q 8 fan Tplh Tphl Ts Th
0.599 1.011 0.889 0.400 -0.158 0.813 0.605 0.722 0.347 0.773 0.398 0.981 1.143 0.501 -0.480
0.809 1.504 1.360 0.615 -0.290 1.182 0.876 1.204 0.433 1.287 0.510 1.462 1.656 0.976 -0.791
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MG2RTP
Rev. F-23-Aug-01
Atmel Wireless & Microcontrollers Sales Offices
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Web site
http://www.atmel-wm.com
(c) Atmel Nantes SA, 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
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