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May 13 1998 (ver.2)
ML7019
SINGLE RAIL DUAL CHANNEL CODEC
Preliminary
v General Description
The ML7019 is a two-channel single-rail CODEC CMOS IC for voice signals ranging from 300 to 3400Hz.This device contains two-channel analog-to-digital (A/D) and digital-to-analog (D/A) converters on a single chip. The ML7019 is designed especially for a single power supply and low power applications and achieves a reduced footprint. The ML7019 is best suited for line card applications with easy interface to subscriber line interface circuits (SLICs). The SLIC interface latches are embedded onto this CODEC, thus eliminating the need for external components and optimizing board space.
v Features
* * Single 5-V power supply Operation Low power consumption - operating mode: typical: 35mW max.: 74mW - power save mode: typical: 7.0mW max.: 16mW - power down mode: typical: 0.05mW max.: 0.3mW ITU-T Companding law - -law / A-law pin selectable Built-in phase-locked loop(PLL) eliminates master clock Built-in dual 3-bit latches with CMOS drive capability Serial PCM interface Transmission clocks: - 256 / 384 / 512 / 768 / 1024 / 1536 / 1544 / 2048 / 4096Kbps Adjustable Transmit gain Built-in reference voltage supply Analog output can directly drive a 600 line transformer Latched content echo-back function Packaging:24SOP
* * * * * * * * * *
The information contained herein can change without notice owing to product and / or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date.
l ML7019
Preliminary
v FUNCTIONAL BLOCK DIAGRAM
AIN1 GSX1 AIN2 GSX2 +
+
RC LPF
8th BPF
AD CONV.
TCONT
DOUT
RC LPF
8th BPF AUTO ZERO 5th LPF 5th LPF S&H DA CONV. S&H
PLL RTIM
XSYNC BCLK RSYNC ALAW
AOUT1
+
RCONT
DIN C1A C2A C3A C1B C2B C3B PDN
AOUT2
+
LATCH SG GEN VR GEN
SGC VDD AG DG
PWD Logic
v PIN ASSIGNMENT
ML7019MA SGC 1 AOUT2 2 NC 3 AOUT1 4 VDD 5 DG 6 C1A 7 C2A 8 C3A 9 ALAW 10 RSYNC 11 DIN 12 24 23 22 21 20 19 18 17 16 15 14 13 AIN2 GSX2 GSX1 AIN1 AG PDN C1B C2B C3B BCLK XSYNC DOUT
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l ML7019
Preliminary
v PIN DESCRIPTION
AIN1, AIN2, GSX1, GSX2 AIN1 and AIN2 are the transmit analog inputs for channels 1 and 2. GSX1 and GSX2 are the transmit level adjustments for channels 1 and 2. AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output of the op-amp and are used to adjust the level, as shown below. When not using AIN1 and AIN2, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving and power down mode, the GSX1 and GSX2 outputs are at AG voltage.
GX1
CH1
Analog Input
C1
R1
R2
AIN1
+
SG GX2
CH1 Gain Gain = R2/R1 10 R1: Variable R2 > 20K C1 > 1/ (2x3.14x30xR1) CH2 Gain Gain = R4/R3 10 R3: Variable R4 > 20K C2 > 1/ (2x3.14x30xR3)
CH2
Analog Input
C2
R3
R4
AIN2
+
SG
AOUT1, AOUT2 AOUT1 is the receive analog output for channel1 and AOUT2 is used for channel2. The output signal has an amplitude of 3.4Vpp above and below the signal ground voltage(SG).When the digital signal of +3dBm0 is input to DIN, it can drive a load of 600 or more. During power saving or power down mode, these outputs are at the voltage level of SG with a high impedance.
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l ML7019
Preliminary
VDD Power supply for +5V. A power supply for an analog circuit of the system which the device is applied should be used a bypass capacitor of 0.1F with excellent high frequency characteristics and a capacitor of 10F to 20F should be connected between this pin and the AG pin if needed. AG Analog signal ground. DG Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground. SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1F capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. BCLK Shift clock signal input for the DIN signals. The frequency, equal to the data rate, is 256, 384, 512, 768, 1024, 1536, 1544, 2048, 4096KHz.Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. RSYNC Receive synchronizing signal input. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK (generated from the same clock source as BCLK). The frequency should be 8KHz 50ppm to guarantee the AC characteristics which are mainly the frequency characteristic of the receive section. However, if the frequency characteristic of the system used is not strictly specified, this device can operate in the range of 6KHz to 9KHz, but the electrical characteristics in this specifications are not guaranteed.
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l ML7019
Preliminary
XSYNC Transmit synchronizing signal input. The PCM output signal from the DOUT pin is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with the BCLK. The frequency should be 8KHz 50ppm to guarantee the AC characteristics which are mainly the frequency characteristic of the transmit section. However, if the frequency characteristic of the system used is not strictly specified, this device can operate in the range of 6KHz to 9KHz, but the electrical characteristics in this specifications are not guaranteed. Setting this signal to logic "1" or "0" drives both CH1 and CH2 circuits to power saving state. DIN DIN is a data input pin. Signals which consist of a total 28 bits configured by the voice band PCM signal(16 bits for 2CH), the general-purpose latch signal(6 bits for both channel), the power down control signal for each channel(2 bits) and empty bit(4 bits), The signal is shifted at a falling edge of the BCLK signal and latched into the internal register when shifted by 28 bits. The voice band signal is converted to an analog signal in synchronization with the RSYNC signal and BCLK. The analog signal of channel 1 is output from AOUT1 pin and the analog signal of channel 2 is output from AOUT2 pin. The general purpose latch signal(C3A,C2A,C1A,C3B,C2B,C1B) are output from six latch output pins. When the PD1 bit of DIN is at logic "0" level, CH1 block is in a power down state. When the PD2 bit of DIN is at logic "0" level, CH2 block is in a power down state.
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l ML7019
Preliminary
DOUT DOUT is a data output pin. Signal which consist of a total 28 bits configured by the voice band PCM signal(16 bits for 2CH), the echo bit(6 bits for latch signal and 2 bits for power down state indication), and empty bit(4 bits), The output signal is output from CH1's MSD bit in a sequential order, synchronizing with the rising edge of the BCLK signal. The first bit of DOUT may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state during power saving state or power down state. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with ITU-T recommendation on coding law and output coding format.
INPUT / OUTPUT Level + Full scale +0 -0 - Full scale PCMIN / PCMOUT ALOW = 0 ( -law ) MSD 10000000 11111111 01111111 00000000 ALOW = 1 ( A-law ) MSD 10101010 11010101 01010101 00101010
PDN Power down control signal. When PDN is at logic "0" level, both CH1 and CH2 circuits are in a power down state. Also the all internal latches are in initial state(logic "0" level). ALAW Control signal input of the companding law selection. The CODEC will operate in the -law when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the -law if the pin is left open, as this pin is internally pulled down.
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l ML7019
Preliminary
C1A, C2A, C3A, C1B, C2B, C3B General-purpose Latched output signal. C1A, C2A, C3A, C1B, C2B, C3B bits of DIN are latched at internal timing. These outputs can drive a LSTTL/CMOS device without external resistor.
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l ML7019
Preliminary
v ABSOLUTE MAXIMUM RATING
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Operating Temperature Storage Temperature Symbol VDD VAIN VDIN TOP TSTG Conditions AG=0V, DG=0V AG=0V, DG=0V Ratings - 0.3 ~ 7.0 - 0.3 ~ VDD+0.3 - 0.3 ~ VDD+0.3 - 40 ~ 85 - 55 ~ 150 C V Unit
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l ML7019
Preliminary
v RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Analog Input Voltage Digital Input High Voltage Digital Input Low Voltage Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time Sync Pulse Width DIN set-up Time DIN Hold Time Symbol VDD VAIN VIH VIL FCLK FSYNC DCLK TIR TIF TXS TSX TRS TSR TWS TDS TDH RDL Digital Output Load CDL Conditions Voltage must be fixed Gain = 1 XSYNC, RSYNC, BCLK, DIN, PDN
Min. Typ. Max.
Unit V VPP V V KHz KHz % ns ns ns ns ns ns s ns ns K pF pF mV mV ns
4.75 2.2 0
256 768 1544
5.0 384 1024 2048
5.25 3.4 VDD 0.8
512 1536 4096
BCLK XSYNC, RSYNC BCLK XSYNC, RSYNC, BCLK, DIN, PDN BCLK to XSYNC XSYNC to BCLK BCLK to RSYNC RSYNC to BCLK XSYNC, RSYNC DIN DIN Pull-up register, DOUT DOUT C1A, C2A, C3A, C1B, C2B, C3B Transmit gain stage, Gain = 1 Transmit gain stage, Gain = 10 XSYNC, RSYNC
40 50 50 50 50
1 BCLK
8 50 -
60 50 50 100 50 50
VDD/2 +100 VDD/2 +10
50 50 0.5 VDD/2 -100 VDD/2 -10
Analog Input Allowable DC offset
VOFF
Allowable Jitter Width
-
500
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l ML7019
Preliminary
v ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
Parameter Power Supply Current Symbol IDD1 IDD2 IDD3 Input High Voltage Input Low Voltage High Level Input leakage current Low Level Input leakage current Digital Output low voltage VIH VIL IIH XSYNC, RSYNC, BCLK, DIN IIL PDN, ALAW DOUT R pull-up: 0.5K VOL C1A, C2A, C3A, C1B, C2B, C3B IOL = 0.4mA C1A,C2A,C3A, Digital Output High Voltage Digital Output current leakage IO CIN VOH C1B,C2B,C3B IOH = 0.4mA C1A,C2A,C3A, C1B,C2B,C3B IOH = 10uA DOUT high impedance state 4.5 5 10 V A pF 2.5 V
0 0.2 0.4
VDD=5V5%, Ta= -40 85C
Min. Typ. Max.
Conditions Operating mode, No signal Power saving mode, PDN=1, XSYNC or BCLK OFF Power down mode, PDN=0 XSYNC, RSYNC, BCLK, DIN PDN, ALAW
Unit mA mA mA V V A A V V
2.2 0 0
7.0 1.3 0.01 0.2
14.0 3.0 0.05 VDD 0.8 2 0.5
0.4
Input capacitance
Transmit Analog interface Characteristics
Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RINX RLGX CLGX VOGX VOSGX Conditions AIN1, AIN2 GSX1, GSX2 With respect to SG
VDD=5V5%, Ta= -40 85C
Min. Typ. Max.
Unit M K pF V mV
10 20 - 1.7
-
30 1.7 20
Gain = 1
- 20
10
l ML7019
Preliminary
Receive Analog interface Characteristics
Parameter Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RLAO CLAO VOAO VOSAO Conditions
VDD=5V5%, Ta= -40 85C
Min. Typ. Max.
Unit K PF V mV
AOUT1, AOUT2 (each) With respect to SG AOUT1, AOUT2 AOUT1, AOUT2,RL=0.6K With respect to SG AIN1, AIN2 With respect to SG
0.6 - 1.7 - 100
-
50 1.7 100
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l ML7019
Preliminary
AC Characteristics
Parameter Symbol freq. (Hz) Transmit Frequency Response Loss T1 Loss T2 Loss T3 Loss T4 Loss T5 Loss T6 Receive Frequency Response Loss R1 Loss R2 Loss R3 Loss R4 Loss R5 Transmit Signal to Distortion Ratio SDT1 SDT2 SDT3 SDT4 SDT5 Receive Signal to Distortion Ratio SDR1 SDR2 SDR3 SDR4 SDR5 Transmit gain Tracking GTT1 GTT2 GTT3 GTT4 GTT5 Receive gain Tracking GTR1 GTR2 GTR3 GTR4 GTR5 1020 1020 1020 1020 60 300 1020 2020 3000 3400 300 1020 2020 3000 3400 3 0 - 30 - 40 - 45 3 0 - 30 - 40 - 45 3 - 10 - 40 - 50 - 55 3 - 10 - 40 - 50 - 55 DIN to DIN to 0 Conditions level
(dBmO)
VDD=5V5%, Ta= -40 85C
Min. Typ. Max.
Unit
20 GSXn to DOUT
(attenuation)
26 0.07 Reference - 0.04 0.06 0.4 - 0.03 Reference - 0.02 0.15 0.56 43 41 38 31.5 27 43 41 40 33.5 30 0.01 Reference 0 - 0.03 0.15 - 0.06 Reference - 0.02 - 0.02 - 0.27
0.2 dB 0.2 0.2 0.8 0.2 0.2 0.2 0.8 0.3 0.3 0.5 1.2 0.3 0.3 0.5 1.2 dB dB dB dB dB
- 0.15 - 0.15 - 0.15 0 - 0.15
DIN to AOUTn
(attenuation)
- 0.15 - 0.15 0 35 35 35 29 24 36 36 36 30 25
GSXn to DOUT *1
AOUTn *1
GSXn to DOUT
- 0.3 - 0.3 - 0.5 - 1.2 - 0.3 - 0.3 - 0.5 - 1.2
AOUTn
*1 psophometric filter is used
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l ML7019
Preliminary
AC Characteristics (Continued)
Parameter Symbol freq. (Hz) Idle channel noise NIDLET NIDLER AVT AVR AVTt AVRt TD Tgd T1 Transmit group delay Tgd T2 Tgd T3 Tgd T4 Tgd T5 Tgd R1 Receive group delay Tgd R2 Tgd R3 Tgd R4 Tgd R5 Cross talk attenuation CRT CRR CRCH 1020 0 1020 500 600 1000 2600 2800 500 600 1000 2600 2800 0 *3 0 *3 0 Conditions level
(dBmO)
VDD=5V5%, Ta= -40 85C
Min. Typ. Max.
Unit
-
AIN=SG DIN:0 code DIN to AOUT
*1 *1
0.82 0.82 - 0.3 - 0.3 -
- 73.5 - 71.5 - 78 0.85 0.85 0.19
- 70 - 68 - 75 0.88 Vrms 0.88 0.3 0.3 0.6 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 dB ms ms ms dB dBmOp
AIN to DOUT *2
GSXn to DOUT VDD=5V,Ta=25C DIN to AOUTn 1020 0 VDD=5V,Ta=25C
Absolute level (Initial Difference) Absolute level
( Deviation of Temperature and Power) Absolute Delay
VDD=5V5, Ta= -40 85C
A to A mode BCLK=2048KHz
-
0.11 0.02 0.05 0.07 0.00 0.00 0.00 0.09 0.12 80 76 78
Trans to Recv. Recv to Trans
channel to channel
75 70 75
*1 Psophometric filter is used *2 Upper is specified for the -law, lower for the A-law *3 Minimum value of the group delay distortion
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l ML7019
Preliminary
AC Characteristics (Continued)
Parameter
Symbol
VDD=5V5%, Ta= -40 85C
Conditions
Min. Typ. Max.
Unit
freq. (Hz) Discrimination Out of band spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Digital output delay time DIS S IMD PSRT PSRR Tsd Txd1 Txd2 Txd3 TpdC 4.6K to 72K 300 to 3400 fa=470 fb=320 0 to 50K DOUT
level
(dBmO)
0 0 -4
0 to 4000Hz 4.6KHz to 100KHz 2 fa - fb
30 -
32 -37.5 - 52
-35 - 35
dB dBmOp dBmO
50mVPP
*4
20 20 20 20
30 -
100 100 100 100 1000
dB
Pull-up register = 0.5K CL = 50pF and 1 LSTTL C1A, C2A, C3A, C1B, C2B, C3B CL = 50pF and 1 LSTTL
ns
20
ns
*4 The measurement under idle channel noise
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l ML7019
Preliminary
v TIMING DIAGRAM
TRANSMIT SIDE BCLK XSYNC DOUT TXS TXD1 1 2 TSX TWS TSD D2 MSD 3 4 5 6 7 8 9 10 11
D3
TXD2 D4 D5
D6
D7
D8
EPD1EC3A
RECEIVE SIDE BCLK RSYNC DIN1 DIN2 TRS 1 2 TSR TWS TDS TDH MSD D2 D3 D4 Figure 1 TRANSMIT SIDE BCLK XSYNC DOUT 1 9 17 25 1 D5 D6 D7 D8 PD1 C3A C2A 3 4 5 6 7 8 9 10 11
TIMING DIAGRAM
MSDD4 5 DD8 EE E D2 3 DD67 EC3A D PD1C1A C2A CH1PCM DATA bits ECHO
MSDD4 D6 7E EE E D2 3 D5 DD8C3B D PD2 C1B C2B CH2PCM ECHO bits DATA 17 25 1
RECEIVE SIDE BCLK RSYNC DIN 1 9
C2A MSD3DDD7PD1 C1A D2D4 5 6D8C3A D
MSDD4D6D8C3B D2 3D5D7PD2 C1B D C2B
CH2PCM DATA DATA CH1PCM DATA DATA Latch Latch CH2 bit CH1 p ower down control p ower down control bit Figure 2 BIT CONFIGURATION
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l ML7019
Preliminary
BCLK 1 9 17 25 29 1 17 25 29 9 XSYNC Control RSYNC CH1 PCM Control CH2 PCM Control CH1 PCM ControlCH2 PCM IN PUT DATA IN PUT DATA IN PUT DATA IN PUT DATA DATA DDDD C MD D D P C MDD D D C C D DD P C MD DD D C C DD DP C DIN M D D D PC C X X D D D D C C S2 4 67 D 21X X S23 567 D 2 35 83 4 8 31 S2 4 6 8D 21 X X 2 4 6 8 32 3 5 7 3 X XS 3 5 7 D 1 D 1A A A D 2B B B D 1A AA D 2B B B
EE EE MDD DP C D DDDC C S234 67 D 21 5 83 DOUT D 1A AA
EE EE M D D D PC C DD DD C S23 56 8 32 4 7D 1 D BB BB ECHO CH1 PCM ECHO CH2 PCM BIT OUTPUT OUTPUT BIT DATA DATA
EE EE M D D D PC C DD DD C S23 567 D 21 4 83 D 1A A A
E MD D D P E DD DDE E S2 456 8D C 3 7 CC 32 1 D 2B BB
ECHO CH1 PCM ECHO CH2 PCM BIT OUTPUT BIT OUTPUT DATA DATA tpdC tpdC
C3A C2A C1A C3 B C2B C1B Figure 3 CONTROL BIT TIMING and ECHO BACK TIMING
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l ML7019
Preliminary
v Application circuit
ML7019
Ch1 analog input Ch1 analog output Ch2 analog input AIN2 GSX2 AIN1 GSX1 DIN AOUT1 BCLK XSYNC RSYNC PDN ALAW C1A C2A C3A C1B C2B VDD C3B DOUT
1K
+5V 2CH Multiplex PCM signal output 2CH Multiplex PCM signal input Bit clock input Sync Pulse input Power down control 1:operation 0:power down Companding law control 1:A-LAW 0:-LAW
Ch2 analog output
0.1F
AOUT2 SGC AG DG
0V 10F +5V 0 to 20 + 1F
Latch Output
v RECOMMENDATIONS FOR ACTUAL DESIGN
* * * * * * To assure electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. Connect the AG pin and DG pin each other as close as possible. Connect to the system ground with low impedance. unavoidable, use the short lead type socket. When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. Keep the voltage on the VDD pin not lower than -0.3V even instantaneously to avoid latch-up phenomenon when turning the power on. Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these device.
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