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Gray Scale Font Engine IC
MN55720
Gray Scale Font Engine
s Overview
The MN55720 is a high-quality character generator IC that rapidly generates multilevel grayscale data from outline (path) data for characters and similar images. This IC includes input and output FIFO memory units to assure highspeed processing, and provides a local interface (16 or 32 bits) to allow the use of this IC in a wide range of equipment.
s Features
* STB and DTV
s Block Diagrams
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RAM
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MN55720
Bus-bridge Local Bus ROM CPU
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s Applications
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* Package:
Publication date: June 2002
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* Gray scale levels: * Bit sizes: * Interface specifications: * Operating frequency: * Operating supply voltage:
Can be set to any level from 2 to 128 levels. Can generate characters of any size. Local bus (Supports both 16-bit and 32-bit busses.) 50 MHz to 70 MHz External supply: 3.3 V0.3 V Internal supply: 2.5 V0.2 V 80 pin TQFP (12 mm x 12 mm)
MN55720
s Pin Assignments
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
D9 D10 D11 VSS VDD3 D12 D13 D14 D15 VSS VDD3 D16 D17 VSS VDD2 D18 D19 VSS VDD3 D20
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TEST OCLOCK VDD2 VSS MINTEST CLKSEL NRST BUSSEL VDD3 HOSTCLK VSS AVSS TCPOUT AVDD PLLON AD2 AD1 AD0 IRQ NWE
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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(TOP VIEW)
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D8 VDD3 VSS VDD2 D7 D6 D5 D4 VDD3 VSS D3 D2 D1 D0 VSS LON VDD3 VDDREG REGOUT VSS
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
D21 D22 D23 VSS VDD3 D24 D25 D26 D27 VSS VDD3 D28 D29 D30 D31 VDD2 VSS VDD3 NCS NRE
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MN55720
s Pin Descriptions
1) Local 32-bit mode Pin HOSTCLK NRST AD[2:0] NCS NWE NRE D[31:0] IRQ BUSSEL CLKSEL MINTEST TEST PLLON OCLOCK TCPOUT LON VDD3 VDDREG REGOUT VDD2 VSS AVDD AVSS I/O I I I I I I I/O O I I I I I O O I I I O I I Clock input from the host Hardware reset (active low) Address signal from the host Chip select signal from the host (active low) Write enable signal from the host (active low) Read enable signal from the host (active low) Data I/O (32-bit) Interrupt output to the host (active high) Description
Data bus width setting (Must be held fixed at the high level)
Clock selection (0: Low-speed clock used, 1: High-speed clock used) Test pin Test pin Test pin Test pin Test pin
Note) 1. Connect the MINTEST pin to ground. 2. The NRST (hardware reset) signal pulse width must be at least 100 ns.
2) Local 16-bit mode Pin I/O I I I I I I I/O I/O Clock input from the host Hardware reset (active low) Address signal from the host Chip select signal from the host (active low) Write enable signal from the host (active low) Read enable signal from the host (active low) Unused (These lines output fixed low-level signals.) Data I/O (16-bit) Description HOSTCLK NRST AD[2:0] NCS NWE NRE D[31:16] D[15:0]
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Regulator control (active high) 3.3 V system power supply (I/O) 3.3 V power supply (regulator) Regulator output (2.5 V) PLL system analog ground
2.5 V system power supply (internal logic circuits) Common ground for I/O and internal logic circuits
PLL system analog power supply (3.3 V)
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MN55720
s Pin Descriptions (continued)
2) Local 16-bit mode (continued) Pin IRQ BUSSEL CLKSEL MINTEST TEST PLLON OCLOCK TCPOUT LON VDD3 VDDREG REGOUT VDD2 VSS AVDD AVSS I/O O I I I I I O O I I I O I I Description Interrupt output to the host (active high) Data bus width setting (Must be held fixed at the high level) Clock selection (0: Low-speed clock used, 1: High-speed clock used) Test pin Test pin Test pin Test pin Test pin Regulator control (active high) 3.3 V system power supply (I/O) 3.3 V power supply (regulator) Regulator output (2.5 V)
2.5 V system power supply (internal logic circuits) Common ground for I/O and internal logic circuits PLL system analog power supply (3.3 V)
Note) 1. Connect the MINTEST pin to VSS. 2. The NRST (hardware reset) signal pulse width must be at least 100 ns.
s Power supply
2. Using the regulator The MN55720 includes a built-in 2.5 V output regulator, which allows this device to function as a single 3.3 V power supply IC. However, since the voltage drop in the regulator is 0.8 V, the power consumption in just the regulator will be 80 mW when the IC draws 100 mA. If a 2.5 V level is provided externally and the regulator is not used, provide a 3.3 V level to VDDREG as shown in the figure below. Note that the 2.5 V regulator output cannot be used to supply other devices.
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1. Power on and off sequences Do not apply power to one of the VDD2 and VDD3 supplies without applying power to the other at the same time. Failing to observe this may cause the problems listed below. The internal logic power supply VDD2 and the external I/O power supply VDD3 should be applied and cut as close to simultaneously as possible. * Degradation of I/O block devices * Inability to establish the states of the output and bidirectional pins even by setting NRST low.
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PLL system analog ground
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MN55720
s Power supply (continued)
2. Using the regulator (continued) 1) When using the regulator output to supply a 2.5 V level
LON VDDREG
REGOUT
VDD2
VDD2
VDD2
VDD2
10 F 3.3 V
2) When supplying the 2.5 V level externally
LON VDDREG
REGOUT
VDD2
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VDD2 2.5 V
3.3 V
s Functional Description
1. Register memory addresses 1) Memory address map AD2 0 0 AD1 0 0
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AD0 0 1
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Open
NAME POINT
Content Outline data input port Grayscale data output port
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VDD2 VDD2
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RASTER
2) Register address map
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AD2 0 0 1 1
AD1 1 1 0 0
AD0 0 1 0 1
NAME PSTATUS RSTATUS CONTROL
Content POINT FIFO status RASTER FIFO status Control register
VAL_LEVEL Level value conversion register
3) Other items AD2 1 AD1 1 AD0 0 NAME SRESET Content Software reset R/W W
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R/W W R R/W R R R/W R/W
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MN55720
s Functional Description (continued)
2. Memory and register contents 1) Outline data input port (POINT FIFO) The POINT FIFO is a memory ports for input of the outline data that the MN55720 will expand. It can hold up to 256 double-word data items at the same time. Data in excess of 256 double-word items must be processed separately. The total capacity of the POINT FIFO is 256 double words. * Outline data format (32-bit data) bit 31 Outline data bit 0
* POINT FIFO memory map
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depth 256 word
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width 32-bit
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MN55720
s Functional Description (continued)
2. Memory and register contents (continued) 2) Grayscale data output port (RASTER FIFO) The RASTER FIFO is a memory port for output of the grayscale data created by the MN55720. It can hold up to 256 double-word data items at the same time. Data in excess of 256 double-word items must be processed separately. The total capacity of the RASTER FIFO is 256 double words. * Grayscale data format (32-bit data) bit 31 Grayscale data bit 0
* RASTER FIFO memory map
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bit 15 0
3) POINT FIFO status register (PSTATUS REGISTER) This is a read-only register that indicates the status of the MN55720 POINT FIFO. This register consists of 16 bits and uses the low-order 16 bits of the data bus. 14 0 13 0 12 0 11 0 10 1 9 PNM 1 0 PAL
PNM(R): Indicates the amount of data written to the POINT FIFO. A maximum of 256 double words of data that can be written to the POINT FIFO. Maximum amount of data that can be written: 256 double words (0x001 to 0x100) PAL(R): Indicates the LSB of the POINT FIFO address. This bit is used for debugging when a 16-bit bus is used.
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depth 256 word
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width 32-bit
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MN55720
s Functional Description (continued)
2. Memory and register contents (continued) 4) RASTER FIFO status register (STATUS REGISTER) This is a read-only register that indicates the status of the MN55720 RASTER FIFO. This register consists of 16 bits and uses the low-order 16 bits of the data bus. bit 15 1 14 13 12 CNM 11 10 9 RNM 1 0 PAL
bit 15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
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6 5 4
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3 2 1 IM 0 RR END SLP
5)
CONTROL register (CONTROL REGISTER) This is a read/write register that sets the MN55720 operating state. This register consists of 16 bits and uses the low-order 16 bits of the data bus.
PLI RFL PR
: Indicates the initialization status after a hardware reset, software reset, or the clearing of sleep mode. 0 : Initialization complete 1 : Initialization in progress RFL(R) : Indicates the data storage status of the RASTER FIFO. 1 : RASTER FIFO full (Read wait) 0 : RASTER FIFO not full PR(R) : Indicates the status of the POINT FIFO. 1 : POINT FIFO writable 0 : POINT FIFO not writable RR(R) : Indicates the status of the RASTER FIFO. 1 : RASTER FIFO readable 0 : RASTER FIFO not readable END(R/W) : Sets the data output operation when a 16-bit bus is used. This setting is only valid when the external pin BUSSEL is set to the low level. 1 : Lower 16 bits first, then upper 16 bits 0 : Upper 16 bits first, then lower 16 bits SLP(R/W) : Sets sleep mode. 1 : Sets the MN55720 to sleep mode. 0 : Clears sleep mode. IM(R/W) : The interrupt pin (the external IRQ pin) can be controlled by setting these bits. 00 : Interrupts are generated on all conditions. (default) 01 : POINT FIFO empty interrupt disabled. 10 : All interrupts are disabled for all conditions. 11 : All interrupts are disabled for all conditions.
PLI(R)
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CNM (R) : Indicates the number of characters the data stored in the RASTER FIFO corresponds to. RNM (R) : Indicates the amount of data that can be read from the RASTER FIFO. This value indicates the amount of data for the first character. Up to 256 double words (0x001 to 0x100) RAL (R) : Indicates the LSB of the RASTER FIFO address. This bit is used for debugging when a 16-bit bus is used.
MN55720
s Functional Description (continued)
2. Memory and register contents (continued) 6) Level values conversion register (VAL_LEVEL REGISTER) This is a read/write register that indicates the status of the level value conversion table. This register consists of 16 bits and uses the low-order 16 bits of the data bus. This IC is limited to converting 16-level data to 4-level data, and those conversion characteristics can be set freely using this register. bit 15 0 0 13 0 12 SW 11 THRESH2 8 7 THRESH1 4 3 THRESH0 0
Note) Conversion example is shown below when VAL_LEVEL is set to 0x1a50.
16-level data 15 14 13 12
THRESH2 = 10 11 10
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9 8 7 6 Level value conversion 2
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THRESH1 = 5 5 1
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THRESH0 = 0 4 3 2 1 0 0
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4-level data
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SW(R/W)
: Indicates the on/off state of 16-level to 4-level conversion. 1 : ON 0 : OFF THRESH2(R/W) : Conversion threshold Set this field to a value in the range 0x0 to 0xF. However, THRESH2 must be greater than THRESH1. THRESH1(R/W) : Conversion threshold Set this field to a value in the range 0x0 to 0xF. However, THRESH1 must be greater than THRESH0. THRESH0(R/W) : Conversion threshold Set this field to a value in the range 0x0 to 0xF.
MN55720
s Functional Description (continued)
3. Input data format This section presents the format of the outline data input to the MN55720. * Overall structure
32-bit Header data
Outline data
Footer data
* Header structure
bit 31 30 0
28 27 26 25 24 23 ev o t bpp tag fh
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16 15 max. cov
14 13 vect. x
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87 bbox. x 0 bbox. y
0 vect. y 0
* Outline data structure
bit 31 30 0 tag 28 27
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* Footer data structure
bit 31 30 0 tag 28 27
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0000000000000000000000000000
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MN55720
s Functional Description (continued)
3. Input data format (continued) * Parameter descriptions
tag
eof
vth
Threshold setting used when binary data is expanded. 0 : Off 1 : On Setting for the number of output bits per pixel 00 : 1-bit 01 : 2-bit 10 : 4-bit 11 : 8-bit Level value setting for the frame being expanded. 0x01h to 0x7Fh (Two levels) (128 levels) Output data width (X) for the frame being expanded. 0x00h to 0x1Fh (1 pixel) (32 pixel) Output data width (Y) for the frame being expanded. 0x00h to 0x1Fh (1 pixel) (32 pixel) Vector data axis (X) Vector data axis (Y)
bpp
max. cov
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bbox. x
bbox. y
vect. x vect. y
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Fill rule setting 0 : Use internal fill when outline segments cross. 1 : Do not use internal fill when outline segments cross.
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11
Data attributes 000 : header 001 : quadratic's or cubic's control point 1 010 : cubic's control point 2 011 : end of data 100 : begin contour 101 : end of line 110 : end of quadratic 111 : end of cubic
MN55720
s Functional Description (continued)
4. Output data format This section presents the format of the grayscale data output by the MN55720. * When bpp = 11 (Assuming bbox.x = n and bbox.y = m)
0 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pix[0] pix[1] pix[2] pix[3] pix[4] pix[5] pix[6] pix[7] line 0 pix[8] pix[9] pix[10] pix[11] ..... ..... ..... ..... pix[n-2] pix[0] pix[4] pix[8] ..... pix[n-2] pix[n-1] pix[1] pix[5] pix[9] ..... pix[n-1] pix[n] pix[2] pix[6] pix[10] ..... pix[n] pix[3] pix[7] pix[11] .....
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.....
pix[3] pix[7] pix[11] .....
line 1
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pix[n]
pix[0] pix[4] pix[8] ..... pix[n-2]
pix[1] pix[5] pix[9] ..... pix[n-1]
pix[2] pix[6] pix[10] .....
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pix[5] pix[13] .....
* When bpp = 10 (Assuming bbox.x = n and bbox.y = m) 0 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pix[1] pix[3] pix[5] pix[7] pix[0] pix[2] pix[4] pix[6] pix[9] pix[11] pix[13] pix[15] pix[8] pix[10] pix[12] pix[14] line 0 ..... ..... ..... ..... ..... ..... ..... ..... pix[n-4] pix[0] pix[8] ..... pix[n-3] pix[1] pix[9] ..... pix[n-3] pix[n-2] pix[2] pix[10] ..... pix[n-2] pix[n-1] pix[3] pix[11] ..... pix[n-1] pix[n] pix[4] pix[12] ..... pix[n] pix[6] pix[14] ..... pix[7] pix[15] .....
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..... ..... .....
pix[3] pix[11] ..... pix[n-1] pix[4] pix[12] ..... pix[n]
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pix[n-4]
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......
.....
.....
line m
line 1
.....
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pix[0] pix[8] .....
pix[n-4]
......
pix[1] pix[9] ..... pix[n-3]
......
.....
.....
.....
.....
pix[2] pix[10] ..... pix[n-2]
pix[5] pix[13] .....
pix[6] pix[14] .....
pix[7] pix[15] .....
line m
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MN55720
s Functional Description (continued)
4. Output data format (continued) * When bpp = 01 (Assuming bbox.x = 26 and bbox.y = m)
0 1 2 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 pix[0] pix[1] pix[2] pix[3] pix[4] pix[5] pix[6] pix[7] pix[8] pix[9] pix[10] pix[11] pix[12] pix[13] pix[16] pix[17] pix[18] pix[19] pix[20] pix[21] pix[22] pix[23] pix[24] pix[25] pix[26] pix[0] pix[1] pix[2] pix[3] pix[4] pix[5] pix[6] pix[7] pix[8] pix[9] pix[10] pix[11] pix[12] pix[13] pix[16] pix[17] pix[18] pix[19] pix[20] pix[21] pix[22] pix[23] pix[24] pix[25] pix[26] 3210 pix[14] pix[15] line 0 pix[14] pix[15] line 1
pix[0] pix[1] pix[2] pix[3] pix[4] pix[5] pix[6] pix[7] pix[8] pix[9] pix[10] pix[11] pix[12] pix[13] pix[14] pix[15] line m pix[16] pix[17] pix[18] pix[19] pix[20] pix[21] pix[22] pix[23] pix[24] pix[25] pix[26]
* When bpp = 00 (Assuming bbox.x = 29 and bbox.y = m)
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0 1 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pix[0:29] - - line 0 pix[0:29] - - line 1 pix[0:29] - - line 2
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line 0 to line m
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pix[0] to pix[n]
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......
......
......
......
.....
.....
.....
.....
pix[0:29]
..... .....
.....
.....
.....
.....
.....
.....
.....
- - line m
.....
.....
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MN55720
s Operational Description
1. Pin settings This section presents the pin settings and conditions that control the operating state of the MN55720. 1) Clock setting Set the clock setting pin (CLKSEL) according to the table below. * Clock pin settings CLKSEL 0 1 HOSTCLK frequency 25 MHz to 35 MHz 50 MHz to 70 MHz Internal operating frequency 50 MHz to 70 MHz 50 MHz to 70 MHz
BUSSEL 0 1
Bus width 16-bit bus 32-bit bus
* Interrupt signal wait The interrupt signal wait operation consists of waiting until the issues of external interrupts. * Outline data write The outline data write operation consists of the input processing required to generate multilevel grayscale data.
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* Grayscale data readout The grayscale data readout operation consists of the output processing for the generated multilevel grayscale data.
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2. Operating procedures This section presents the operating procedures used with the MN55720. 1) Overview of operating procedures * Initialization Initialization is the processing performed after a hardware reset, and consists of clearing the memory and setting the operating conditions.
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2) Bus width setting Set the bus width setting pin (BUSSEL) according to the table below. * Bus width pin settings
MN55720
s Operational Description (continued)
2. Operating procedures (continued) 2) Initialization * Flowchart for the initialization operation
start
Hardware reset
Set the CONTROL register.
IM, END
end
* Description of the initialization flowchart steps The registers are initialized by the reset operation due to a hardware reset (NRST), and memory initialization processing starts automatically. * Set the CONTROL register. This operation consists of setting the conditions for the interrupts (IRQ) generated and setting the endian type if a 16-bit bus is used. If the CONTROL register is not set explicitly, the MN55720 will operate at the initial conditions. * Verify the CONTROL register state. This operation consists of reading out the CONTROL register and verifying that PLI is 0. If PLI is not 0, wait for a brief period and read the CONTROL register again.
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Verify the CONTROL register state. (Verifies the completion of the initialization operation)
PLI = O
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MN55720
s Operational Description (continued)
2. Operating procedures (continued) 3) Interrupt signal wait operation * Flowchart for the interrupt signal wait operation
start
Check the interrupt signal.
IRQ = high
IRQ = low
Check the CONTROL register.
PR = 1
Check the POINT FIFO status register. (Status read)
PNM < 256
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Check the RASTER FIFO status register. (Status read)
PNM > 0
Write the outline data.
* Description of the interrupt signal wait operation flowchart steps Changes in the internal state can be verified by recognizing the interrupt signal issued.
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* Check the CONTROL register. Read the CONTROL register and verify that either PR or RR is 1. If neither PR nor RR is 1, read the CONTROL register again. After checking the PR and RR bits and determining the interrupt type, determine which processing must be performed next. * Check the POINT/RASTER FIFO status register. Read either the POINT or RASTER FIFO status register, depending on the status of the PR and RR bits. Perform the outline data write or grayscale data read operation required according to the PNM or RNM value in the POINT or RASTER FIFO status register. * Notes If the IRQ pin signal is not used, check the CONTROL register periodically and perform the processing that follows the CONTROL register check operation in the flowchart above according to bits 4 and 5 in the CONTROL register.
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* Check the interrupt signal. Monitor the interrupt signal (IRQ) until the conditions set in the CONTROL register are met and the MN55720 asserts the interrupt signal (IRQ).
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Read the grayscale data.
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Verify PR and RR.
RR = 1
MN55720
s Operational Description (continued)
2. Operating procedures (continued) 4) Outline data write operation * Flowchart for the outline data write operation
start
Check the CONTROL register.
PR = 1
PNM read
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Did that complete one frame?
Yes
end
* Check the CONTROL register. Read the CONTROL register. If PR is 1, then outline data can be written.
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* Check the POINT FIFO STATUS register. Read the POINT FIFO STATUS register and determine the value of the PNM field. * Write the outline data. Input up to (<256 double words> - ) of outline data to the outline data input port (POINT FIFO). * Terminate a single frame If the outline data write operation complete the input of outline data for a single character, the processing required for this operation has been completed. If there is remaining outline data that must be input, check the CONTROL register again and perform the write operation described above again.
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* Description of the outline data write operation flowchart steps This operation writes the outline data for processing.
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No
Write the outline data. (Write up to (<256 double words> - ).)
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Check the POINT FIFO STATUS register. (status read)
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MN55720
s Operational Description (continued)
2. Operating procedures (continued) 5) Grayscale data read operation * Flowchart for the grayscale data read operation
start
RR = 1
Read the grayscale data. (Read out RNM double words of data.)
* Description of the grayscale data read operation flowchart steps This operation reads out the grayscale data generated.
* Read the grayscale data. The multilevel grayscale data for a single character can be read out from the grayscale data output port (RASTER FIFO). The maximum amount of grayscale data that can be output at a time is 256 double words. The amount of grayscale data that can be read out is indicated by RNM. Read individual double words RNM times to read out all the grayscale data. Reading out the number of double words indicated by RNM completes the readout of the grayscale data for a single multilevel character. * Terminate a single frame When reading out the grayscale data completes the grayscale data output for a single character, that completes the processing. If the data for multiple characters is stored (that is, if CNM is greater than 1), read out grayscale data CNM times.
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* Check the RASTER FIFO STATUS register. Read the RASTER FIFO STATUS register, and determined the value of the RNM field.
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* Check the CONTROL register. Read the CONTROL register. If the RR bit is 1, then there is grayscale data to read.
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end
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Check the RASTER FIFO STATUS register. (status read)
RNM read
RNM : 001h (1 double-word) to 100h (256 double-word)
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Check the CONTROL register.
MN55720
s Operational Description (continued)
3. Sleep mode settings 1) Sleep mode operation The internal operating clock can be stopped and the device set to sleep mode by setting bit 2 (SLP) in the CONTROL register to 1. After using this IC's internal outline data processing, write a 1 to bit 2 in the CONTROL register when that processing has completed. Note that this IC's internal data is not guaranteed after it is switched to sleep mode. Sleep mode can be cleared by writing a 0 to bit 2 in the CONTROL register. Note that after sleep mode is cleared, the IC automatically applies an internal reset. The CONTROL register does not need to be set up again after sleep mode has been cleared, that is, it retains the state it had prior to sleep mode. * Sleep mode flowchart
start
Write the CONTROL register. (Write a 1 to bit 2.)
Write the CONTROL register. (Write a 0 to bit 2.)
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Sleep mode end
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This sets up sleep mode. This clears sleep mode.
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MN55720
s Operational Description (continued)
4. Software reset procedure 1) Software reset operation A software reset can be applied by writing the SRESET register. Any value whatsoever can be used as the data written. A software reset can be applied before or after writing data to, or reading data from, FIFOs or registers. However, since whole internal data is reset, it will be necessary to set up the CONTROL register again after the software reset. * Software reset flowchart
end
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Write to the SRESET register. (Any data may be used as the write data.)
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start
MN55720
s External Connection Examples
1. Connections used in 32-bit mode The figure presents an example of external connections used with the MN55720.
D[31:0] AD[2:0] NCS NWE NRE HOST NRST HOSTCLK IRQ
BUSSEL LON PLLON CLKSEL MINTEST TEST
0.1 F
VDD3 VSS
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0.1 F AVDD AVSS
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MN55720
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TCPOUT VCOOUT VDDREG VSS REGOUT VSS VDD2 VSS 10 F 10 F 0.1 F
Note) The CLKSEL setting (fixed at the high level) shown here is used when a high-speed clock (50 MHz to 70 MHz) is used. If a low-speed clock (25 MHz to 25 MHz) is used, CLKSEL must be connected to a low level. The example shown here is a circuit that uses the built-in regulator. See the section Power Supply, 2. Regulator usage, for the circuit required to use an external 2.5 V supply.
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MN55720
s External Connection Examples (continued)
2. Connections used in 16-bit mode The figure presents an example of external connections used with the MN55720.
D[31:16] D[15:0] AD[2:0] NCS NWE HOST NRE NRST HOSTCLK IRQ
LON PLLON CLKSEL BUSSEL MINTEST TEST
VSS
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0.1 F AVDD AVSS
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MN55720
0.1 F
VDD3
m
TCPOUT OCLOCK VDDREG VSS REGOUT VSS VDD2 VSS 10 F 10 F 0.1 F
Note) The CLKSEL setting (fixed at the high level) shown here is used when a high-speed clock (50 MHz to 70 MHz) is used. If a low-speed clock (25 MHz to 25 MHz) is used, CLKSEL must be connected to a low level. The example shown here is a circuit that uses the built-in regulator. See the section Power Supply, 2. Regulator usage, for the circuit required to use an external 2.5 V supply.
22
U
nd
er
SDF00027AEM
en t
MN55720
s Electrical Characteristics
1. Absolute Maximum Ratings at VSS = 0 V Parameter External supply voltage Internal supply voltage Input pin voltage Output pin voltage Output current (Type HL4 pins) Output current (Type HL8 pins) Power supply input current Power dissipation Operating temperature Storage temperature
*
Symbol VDD VDDI VI VO IO IO IV PD Topr Tstg
Rating - 0.3 to +4.6 - 0.3 to +3.6 - 0.3 to VDD+0.3 (Upper limit: 4.6 V) - 0.3 to VDD+0.3 (Upper limit: 4.6 V) 12 24 70 (Per pin) T.B.D. -10 to +70 -55 to +125
Unit V V V V mA mA mA
*
2. Recommended Operating Conditions at VSS = 0 V Parameter External supply voltage Internal supply voltage * Operating temperature Input rise time Input fall time Symbol VDD
de ve l
Condition Topr tr tf Condition VDD = VI = 0 V f = 1 MHz Topr = 25C CI CO CI/O
SDF00027AEM
op
Note) 1. *: Apply and remove the power supply voltages at as close to the same time as possible. 2. Type HL4 pins: IRQ and CLOCK Type HL8 pins: D0 to D31 3. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed. Operation is not guaranteed within these ranges. 4. All the VDD and VSS pins must be connected to the external corresponding power supply or ground.
m
en t
Min 3.0 2.3 -10 0 0 Typ 3.3 2.5 Max 3.6 2.7 70 100 100 Min Typ 7 7 7 Max 8 8 8
mW C C
Unit V V C ns ns
VDDI
3. I/O Capacitances at VSS = 0 V
U
Parameter
nd
Note) : The guaranteed values for the internal supply voltage apply when power is provided directly from and external supply. (When the regulator is not used.)
er
Symbol
Unit pF pF pF
Input pins
Output pins I/O pins
23
MN55720
s Electrical Characteristics (continued)
4. DC Characteristics VDD = 3.0 V to 3.6 V, VDDI = 2.3 V to 2.7 V, VSS = 0 V, fTEST = 70 MHz, Topr = -10C to +70C Parameter Operating current drain Symbol IDDO Condition VI = VDD or VSS , f = 70 MHz, VDD = 3.3 V VDDI = 2.5 V, outputs open VI = VDD or VSS , f = 70 MHz, VDD = 3.3 V VDDI = 2.5 V, outputs open Min Typ Max 20 * Unit mA
Current drain with the internal supply operating
IDDIO
180 *
mA
LVCMOS input level pins: HOSTCLK, NRST, AD0 to AD2, NCS, NWE, NRE, BUSSEL, CLKSEL, TEST, PLLON, LON High-level input voltage Low-level input voltage Input leakage current VIH VIL ILI VI = VD or VSS VDD x 0.7 0
en t
VDD 10 VDD x 0.3 30 VDD VDD x 0.3 90 10 VDD VDD x 0.3 VDD x 0.3 10 VDD x 0.3
V V A
LVCMOS input level pins with built-in pull-down resistor: MINTEST High-level input voltage Low-level input voltage Pull-down resistor Input leakage current LVCOM I/O level pins: D0 to D31 High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current VIH VIL RIL ILIL VI = VDD VI = VSS
m
VDD x 0.7 0 10 VDD x 0.7 0 VDD x 0.7 VDD x 0.7
V V k A
de ve l
VIH VIL IOH = -8.0 mA VI = VDD or VSS IOL = 8.0 mA VI = VDD or VSS ILO VO = high-impedance state VI = VDD or VSS VO = VDD or VSS IOH = -4.0 mA VI = VDD or VSS IOL = 4.0 mA VI = VDD or VSS
SDF00027AEM
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V V V V A
VOH VOL
Push-pull outputs: OCLOCK and IRQ
Low-level output voltage
Note) *: These values are preliminary.
U
High-level output voltage
nd
er
VOH VOL
V V
24
MN55720
s Electrical Characteristics (continued)
5. AC Characteristics 1) Register and memory access timing Parameter Address setup Address hold Data setup Data hold NCS setup NCS hold NCS negated period NWE hold time during the NCS negated period NRE hold time during the NCS negated period NWE pulse width NWE negated period NCS hold time during the NWE negated period NRE pulse width NRE negated period NCS hold time during the NRE negated period NRE access time Data output hold time Symbol tSA tHA tSD tHD tSC tHC tNC tHWC tHRC tWW tNW tHCW tWR tNR tHCR tAR Min 0 2 0 2 0 2 HCK+1 5 5 HCK+2 HCK+1 5 Max 1HCK+12.3 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note) HCK is the HOSTCLK clock cycle time
er
tSA
VIH VIL
* Write cycle
AD[2:0]
nd
tNC
tSC
de ve l
5 2 tHRD
tHA tHC tWW
VIL
op
2 x HCK+5 HCK+1
tHWC tHD
m
U
NCS
VIH
VIL
tNW
VIH
NWE
tSD D(in)
VIH VIL
en t
tHCW
SDF00027AEM
25
MN55720
s Electrical Characteristics (continued)
5. AC Characteristics (continued) 1) Register and memory access timing (continued) * Read cycle tSA AD[2:0] tNC NCS
VIH VIH VIL
tHA
tSC
VIL
tHC
tHCR
tNR NRE
VIH VIL
tWR
tHRC
tAR D(out)
VIH VIL
tHRD
s Package Dimensions (Unit: mm)
* TQFP080-P-1212D (Lead free) 14.000.20 12.000.10 60 61
(1.25)
nd
80
21 20 0.200.05
U
1 0.50
12.000.10 14.000.20
er
de ve l
41 40 (1.00) 1.20 max. 0.10 M 1.000.10
(1.25)
op
0.150.05
0 to 8 0.10+0.10 -0.05 0.500.10 Seating plane
SDF00027AEM
0.10
26
m
en t
Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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