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| Color TFT LCD Driver MN83901ABG-C LCD Panel Source Driver s Overview The MN83901ABG-C is an LCD panel source driver that can display an analog video signal on a color TFT LCD panel in products such as LCD TV sets and camcorders. s Features * Number of driver outputs: 240 outputs * Lower power consumption and lower EMI due to a 2.7 to 5.5 V digital power supply system and a 5.0 V analog power supply system. * Wide dynamic range: 4.6 V (at supply voltage: 5.0 V) * Low inter-pin variation between output pins: 20 mV (typical) * Provides analog RGB signal switching to support both stripe and delta color filter arrays. * Mode input selects between sequential sampling (CLK1, CLK2, and CLK3 input) and simultaneous sampling (CLK1 input, with CLK2 and CLK3 held at VDD1). * Schmitt trigger circuit minimizes noise on the OE pin. * Supports serial cascade connection. * The clock is automatically stopped after a fixed amount of data is acquired. * Bidirectional shift register * Supports mounting in thin-frame panels. (The chip short side length is under 1 mm.) * Package type: bare chip s Applications * LCD panel driver for LCD TVs and camcorders Publication date: May 2002 SDF00022AEM 1 MN83901ABG-C s Block Diagram QA80 QB80 ***** ***** VDD2 VSS2 VBS OE Schmitt trigger circuit Bias control circuit Output buffers 240 3 VA , VB , VC D1 VDD1 VSS1 240 CLK1, CLK2, CLK3 MOD 3 Clock generator circuit Analog multiplexer 3 Two sample-and-hold circuit systems 240-bit bidirectional shift register RL STHR TEST1 TEST2 Shift register control circuit QC80 STHL QA1 QB1 2 SDF00022AEM QC1 MN83901ABG-C s Pin Descriptions Pin Name STHR STHL I/O I/O Function Shift data input and output Description Input and output pins for the data handled by the bidirectional shift register. The input and output functions are switched by the RL pin as shown below. RL High Low STHR I O STHL O I 1) Input The data input to the first stage of the shift register. This data is acquired in synchronization with the rising edge of CLK1. 2) Output Outputs data for input to the next stage when this IC is connected in cascade (series). This data is output in synchronization with the rising edge of CLK1. RL I Shift direction selection This pin specifies the shift direction of the bidirectional shift register. RL = high : QA1 QB1 QC1 * * * QC80 RL = low : QC80 QB80 QA80 * * * QA1 CLK1 to CLK3 I Clock inputs Clocks that shift the sample-and-hold signals for the data output to the LCD drive output pins (QA1 to QC80). The relation between these clocks and the output pins is as follows. 1) MOD = low (Sequential sampling mode) CLK1 : RL = high : QA1 to QA80 RL = low : QC1 to QC80 CLK2 : QB1 to QB80 CLK3 : RL = high : QC1 to QC80 RL = low : QA1 to QA80 2) MOD = high (Simultaneous sampling mode) CLK1 : QA1 to QA80 : QB1 to QB80 : QC1 to QC80 CLK2 : Connect to VDDI. CLK3 : Connect to VDDI. The rising edge of this signal switches between the two sampleand-hold circuit systems and starts the output of new data. When the output reaches the drive potential, the capacity is automatically lowered, and at the same time the drive potential is held steady. OE I Output enable SDF00022AEM 3 MN83901ABG-C s Pin Descriptions (continued) Pin Name D1 I/O I Function Analog signal switching Description Sets which of the analog input signals VA, VB, and VC, are output from which of the QA, QB, and QC outputs. D1 Low I VA VB VC High VA VB VC VBS VA VB VC QA1 to QA80 QB1 to QB80 QC1 to QC80 MOD I I Bias adjustment Analog signal inputs O QA1 to QA80 QB1 to QB80 QC1 to QC80 QB1 to QB80 QC1 to QC80 QA1 to QA80 The voltage applied to this pin adjusts the output buffer bias and modifies the drive capacity of the LCD drive outputs. Inputs for the analog signals for output from the LCD drive output pins The analog input signals VA, VB, or VC are sampled and held, and those levels are output from these pins. Selects whether the sampling of the 3 analog input signals VA, VB, and VC is performed simultaneously or sequentially. MOD = high: Simultaneous sampling MOD = low: Sequential sampling Connect to VDD1. Connect to VDD1. O LCD drive outputs I Mode selection input TEST1 TEST2 VDD1 VDD2 VSS1 VSS2 I I Test input Test input Digital system high potential High-level side of the digital (logic) system power supply power supply Analog system high potential High-level side of the analog system power supply used power supply for sample-and-hold and other circuits Digital system ground Analog system ground Digital system ground used for logic and other circuits Analog system ground used for sample-and-hold and other circuits 4 SDF00022AEM MN83901ABG-C s Functional Description 1. Output signals The MN83901ABG-C supports both stripe and delta color filter arrangement LCD panels. The relationship between the input pins and the output pins is switched by the DI pin. 1) Stripe arrangement * Left-shift mode (RL = low), DI = low R R ***** G G ***** B B ***** R R ***** G G ***** B B ***** R R ***** G G ***** B B ***** ***** ***** ***** G G ***** B B ***** R G B R G B R G B ***** G B QB1 QC1 QB2 QC2 QB3 QC3 QB80 QC80 QA1 QA2 QA3 ***** VA VB VC R G B Source drivers * Right-shift mode (RL = high), DI = low R R G G B B R R G G B B R R G G B B ***** ***** G G B B ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** G R G B R G B R G B ***** QA1 QB1 QC1 QA2 QB2 QC2 QA3 QB3 QC3 QB80 R G B VA VB VC ***** Source drivers QC80 ***** B SDF00022AEM 5 MN83901ABG-C s Functional Description (continued) 1. Output signals (continued) 2) Delta arrangement * Left-shift mode (RL = low) D1 : Low D1 : High R B ***** G R ***** B G ***** R B ***** G R ***** B G ***** R B ***** G R ***** B G ***** ***** ***** ***** G R ***** B G ***** D1 : High B R G B R G B R G ***** R G QB1 QC1 QB2 QC2 QB3 QC3 QB80 QC80 QA1 QA2 QA3 ***** VA VB VC R G B Source drivers * Right-shift mode (RL = high) D1 : High D1 : Low B R ***** R G ***** G B ***** B R ***** R G ***** G B ***** B R ***** R G ***** G B ***** ***** ***** ***** R G ***** G B ***** D1 : Low R G B R G B R G B ***** G B QB1 QC1 QB2 QC2 QB3 QC3 QB80 R G B VA VB VC ***** Source drivers 6 SDF00022AEM QC80 QA1 QA2 QA3 MN83901ABG-C s Functional Description (continued) 2. Recommended operating timing diagrams 1) QA1 QC80 transfer mode: DI = low, MOD = low * Sequential sampling mode 1 CLK1 CLK2 CLK3 STHR (Input side) STHL (Output side) VA VB VC 2 3 78 79 80 Output on the rising edge of CLK1 Data hold timing QA1 QA2 QA3 QA79 QA80 QB1 QB2 QB3 QB79 QB80 QC1 QC2 QC3 QC79 QC80 * Start of sampling When CLK1 rises, the start pulse (STHR = high) is acquired and sampling of the analog signal QA1 starts. The analog signal QA1 is held on the next CLK1 rising edge. * Auto standby function After sampling the analog signal QC80, the IC automatically goes to the standby state, the shift register is reset, and sampling is not performed until a high level is input to STHR again. When multiple start pulses are input, although all the start pulses are transmitted to the shift register, the IC goes to the standby state 81 clock cycles after the first start pulse. 1H = 63.5 s OE *1 CLK tr * 2 LCD drive outputs QA1 to QC80 Note) *1: The rising edge of this signal switches between the two sample-and-hold circuit systems and starts the output of new data. When the output reaches the drive potential, the capacity is automatically lowered, and at the same time the drive potential is held steady. *2: The settling time is adjusted with VBS. tf * 2 SDF00022AEM 7 MN83901ABG-C s Functional Description (continued) 2. Recommended operating timing diagrams (continued) 2) QA1 QC80 transfer mode: DI = low, MOD = high * Simultaneous sampling mode (Connect CLK2 and CLK3 to VDDI.) 1 CLK1 STHR (Input side) STHL (Output side) VA VB VC 2 3 78 79 80 Output on the rising edge of CLK1 Data hold timing QA1 QA2 QA3 QA79 QA80 QB1 QB2 QB3 QB79 QB80 QC1 QC2 QC3 QC79 QC80 3) QC80 QA1 transfer mode: DI = high, MOD = high * Simultaneous sampling mode (Connect CLK2 and CLK3 to VDDI.) 1 CLK1 STHR (Input side) STHL (Output side) VA VB VC 2 3 78 79 80 Output on the rising edge of CLK1 Data hold timing QB80 QB79 QB78 QB2 QB1 QC80 QC79 QC78 QC2 QC1 QA80 QA79 QA78 QA2 QA1 8 SDF00022AEM MN83901ABG-C s Functional Description (continued) 3. Operation when cascade connection is used * When RL is high When a start pulse is input to STHR, after one clock (CLK) cycle passes, driver A starts to acquire data. STHL (carry output) rises 80 clock cycles after the start pulse input, and one clock cycle later, data acquisition stops. Driver B accepts the driver A STHL output as a start pulse input, and starts data acquisition one clock cycle later. 80CLK CLK1 1CLK State 1 1CLK State 2 Data acquired by driver A 1CLK Data acquired by driver B 80 81 1 82 2 83 3 84 4 85 5 VA 1 2 3 79 Chromatic signal processing IC R, G, B analog values LCD controller 1 Start pulse STHR STHL Driver A 2 STHR STHL STHR STHL Driver B Driver C SDF00022AEM 9 MN83901ABG-C s Electrical Characteristics 1. Absolute Maximum Ratings at VSS1 = 0 V, VSS2 = 0 V Item Digital system supply voltage Analog system supply voltage Digital input voltage Analog input voltage Digital output voltage Analog output voltage Operating and storage temperature range Operating temperature Storage temperature Symbol VDD1 VDD2 VI1 VI2 VO1 VO2 Ta Topr Tstg Rating - 0.3 to +7.0 - 0.3 to +7.0 - 0.3 to VDD1 +0.3 - 0.3 to VDD2 +0.3 - 0.3 to VDD1 +0.3 - 0.3 to VDD2 +0.3 -30 to +85 -20 to +75 -40 to +110 Unit V V V V V V C C C Note) 1. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed. Operation is not guaranteed within these ranges. Also, the operating and storage temperature range is the temperature range over which the IC may be operated without damage to the IC. IC performance is not guaranteed within this range. 2. These ratings are guaranteed values when the standard Panasonic package is used. 2. Operating Conditions at VSS1 = 0 V, VSS2 = 0 V, Ta = -20C to +75C Item Operating digital system supply voltage Operating analog system supply voltage Analog reference voltage Operating frequency Analog input voltage Drive output load capacitance Digital signal input pin capacitance Analog signal input pin capacitance Symbol VDD1 VDD2 VBS fclk VIA to VIC CY CinD CinA For a 1 MHz input signal For a 1 MHz input signal Condition Min 2.7 4.5 1.0 0.5 0.2 Typ 3.0 5.0 2.0 8 10 Max 5.5 5.5 3.0 15 VDD2 - 0.2 100 20 20 Unit V V V MHz V pF pF pF Note) 1. The multiple VDD1 and VDD2 power supply pins must all be connected to the power supply level. 2. The multiple VSS1 and VSS2 ground pins must all be connected to ground. 3. When powering on this IC, first apply VDD1 and VDD2, and only then apply VA, VB, VC, VBS, and the logic inputs. When power down this IC, use the reverse sequence from the power on sequence. 90% VDD1 VSS1 , VSS2 Power on sequence 90% VDD2 VSS1 , VSS2 Timing with which VA , VB , VC , VBS , and the logic inputs may be applied 4. The operating supply voltages are the voltages applied to VDD1 and VDD2. 5. These ratings are guaranteed values when the standard Panasonic package is used. 10 SDF00022AEM MN83901ABG-C s Electrical Characteristics (continued) 3. DC Characteristics (continued) at VDD1 = 2.7 V to 5.5 V, VDD2 = 5.0 V, VSS1 = VSS2 = 0 V, VBS = 2.5 V, fclk = 15 MHz, Ta = 25C Item Operating analog system supply current 1 *1, 2, 3 Operating analog system supply current 2 *3, 4 Operating digital system supply current *1 Quiescent digital system supply current 1) Input pins: RL, CLK1, D1 High-level input voltage Low-level input voltage Input leakage current 2) Schmitt trigger input pins: OE High-level input voltage Low-level input voltage Schmitt voltage Input leakage current VIH2 VIL2 Vsmt VLI2 VDD1 = 3.3 V 0.8 x VDD1 0 -10 0.7 x VDD1 0 VDD1 = 3.6 V 1.5 0.7 x VDD1 0 VDD1 = 3.6 V 1.5 0.7 x VDD1 0 VDD1 = 3.6 V 30 0.7 x VDD1 0 IO = -1 mA IO = 1 mA Analog input (VA , VB , VC) frequency = 0.5 MHz Analog input (VA , VB , VC) amplitude = (VDD2 - 0.2) to 0.2 V VDD1 - 0.1 -150 0.5 5 5 100 VDD1 0.2 x VDD1 10 V V V A VIH1 VIL1 VLI1 0.7 x VDD1 0 -10 VDD1 0.3 x VDD1 10 V V A Symbol IDD1 IDD2 IDD3 IDD4 In the clock stopped state With no load Condition Min Typ 4.5 3.5 2.3 Max 10 6.5 100 Unit mA mA mA A 3) Conditional (when MOD is high) pull-up resistor input pins: CLK2, CLK3 High-level input voltage Low-level input voltage Pull-up resistance VIH3 VIL3 RPU3 VDD1 0.3 x VDD1 15 V V k 4) Pull-up resistor input pins: TEST1, TEST2 High-level input voltage Low-level input voltage Pull-up resistance VIH4 VIL4 RPU4 VDD1 0.3 x VDD1 15 V V k 5) Pull-down resistor input pins: MOD High-level input voltage Low-level input voltage Pull-down resistance 6) I/O pins: STHR, STHL High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage 7) Analog input pins: VA , VB , VC Input current IVA to IVC 150 mA VIH6 VIL6 VOH VOL VDD1 0.3 x VDD1 0.1 V V V V VIH5 VIL5 RPU5 VDD1 0.3 x VDD1 300 V V k SDF00022AEM 11 MN83901ABG-C s Electrical Characteristics (continued) 3. DC Characteristics (continued) at VDD1 = 2.7 V to 5.5 V, VDD2 = 5.0 V, VSS1 = VSS2 = 0 V, VBS = 2.5 V, fclk = 15 MHz, Ta = 25C Item Symbol Condition Min -10 Typ Max Unit 8) Reference voltage input pin: VBS Input leakage current IVBS IOH Analog input voltage (VA , VB , VC) = 4.8 V Output pin applied voltage (QA1 to QC80) = 3.8 V VBS = 2.7 V Analog input voltage (VA , VB , VC) = 0.2 V Output pin applied voltage (QA1 to QC80) = 1.2 V Analog input voltage (VA , VB , VC) = 0.2 V, 2.5 V, 4.8 V VO = V + VMIN VOUT - MAX 2 10 mA 9) Analog output pins: QA1 to QC80 Output current 0.03 0.05 mA IOL 0.15 2 Inter-pin output voltage deviation *5 VO 20 mV Note) 1. *1: Load conditions Analog input signals (VA, VB, VC) = 7.5 MHz, amplitude = 0.2 V to 4.8 V, OE = 100 kHz, VBS = 2.5 V IDD1 IDD2 A A IDD3 IDD4 DUT VDD2 VDD1 VSS1 QA1 QB1 * * * * * * * QC80 VSS2 (100 pF) VSS2 0V (DUT : Device Under Test) *2: The load on the analog output pins (QA1 to QC80) changes in certain cases. *3: The formula for calculating the power consumption when a load is connected is as follows. IDD1 x VDD2 + IDD3 x VDD1 Use the value for IDD2 for IDD1 in the formula above to calculate the power consumption when there is no load. *4: The no load power consumption value is provided for reference purposes only; this value is not guaranteed. *5: VOUT expresses the output voltage for each output pin, whereas VMAX and VMIN express the maximum and minimum values for the output voltage for the chip-internal output terminals. 2. These ratings are guaranteed values when the standard Panasonic package is used. 12 SDF00022AEM MN83901ABG-C s Electrical Characteristics (continued) 4. AC Characteristics at VDD1 = 2.7 V to 5.5 V, VDD2 = 5.0 V, VSS1 = VSS2 = 0 V, Ta = 25C Item Clock cycle time Clock high-level period Clock low-level period Clock delay time Start pulse setup time Start pulse hold time Start pulse width Carry signal output delay time Output switching signal high-level period Symbol tCLK tWCH tWCL td12 , td23 tst thd twsth tdl tOEW With a 25 pF load Condition Min 66.6 27 27 16.6 10 5 15 5 1 Typ Max 2 000 tCLK /2 tCLK -5 tCLK -10 2tCLK -15 56 Unit ns ns ns ns ns ns ns ns s Note) These ratings are guaranteed values when the standard Panasonic package is used. * Sequential sampling mode tCKL VIH tWCH tWCL CLK1 VIL td12 CLK2 td23 CLK3 thd Input mode STHR (RL = High) STHL (RL = Low) Output mode STHL (RL = High) STHR (RL = Low) tst thd tst twsth tdl tdl tOEW OE Note) In simultaneous sampling mode, both CLK2 and CLK3 are held fixed at the high level. SDF00022AEM 13 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company. Please read the following notes before using the datasheets A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited. 2001 MAR |
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