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| March 1997 NDS8434A Single P-Channel Enhancement Mode Field Effect Transistor General Description SO-8 P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. Features -7.8 A, -20 V. RDS(ON) = 0.024 @ VGS = -4.5 V RDS(ON) = 0.032 @ VGS = -2.5V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. ___________________________________________________________________________________________ 5 6 7 4 3 2 1 8 Absolute Maximum Ratings Symbol VDSS VGSS ID PD Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed T A = 25C unless otherwise noted NDS8434A -20 8 (Note 1a) Units V V A W -7.8 -25 2.5 1.2 1 -55 to 150 Maximum Power Dissipation (Note 1a) (Note 1b) (Note 1c) TJ,TSTG RJA RJC Operating and Storage Temperature Range C THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 50 25 C/W C/W (c) 1997 Fairchild Semiconductor Corporation NDS8434A Rev.D Electrical Characteristics (TA = 25C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = -250 A VDS = -16 V, VGS = 0 V TJ =55C Gate - Body Leakage, Forward Gate - Body Leakage, Reverse Gate Threshold Voltage Static Drain-Source On-Resistance VGS = 8 V, VDS = 0 V VGS = -8 V, VDS= 0 V VDS = VGS, ID = -250 A TJ = 125C VGS = -4.5 V, ID = -7.9 A TJ = 125C VGS = -2.5 V, ID = -7.2 A ID(on) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd On-State Drain Current Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = -10 V, ID = -7.9 A, VGS = -4.5 V VDD = -5 V, ID = -1 A, VGEN = -4.5 V, RGEN = 6 VGS = -4.5 V, VDS = -5 V VGS = -2.5 V, VDS = -5 V VDS = -4.5 V, ID = -7.9 A VDS = -10 V, VGS = 0 V, f = 1.0 MHz DYNAMIC CHARACTERISTICS 1730 1100 300 13 38 210 78 35 3.8 8.2 25 70 300 150 55 pF pF pF ns ns ns ns nC nC nC -25 -10 28 S -0.4 -0.3 -0.51 -0.32 0.021 0.032 0.027 -20 -1 -10 100 -100 -1 -0.8 0.024 0.043 0.032 A V A A nA nA V ON CHARACTERISTICS (Note 2) SWITCHING CHARACTERISTICS (Note 2) NDS8434A Rev.D Electrical Characteristics (TA = 25C unless otherwise noted) Symbol IS VSD Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design. Parameter Conditions Min Typ Max -2.1 Units A V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = -2.1 A (Note 2) -0.64 -1.2 PD(t) = R JA(t) T J -TA = R JC+RC (t) A T J -TA = I 2 (t ) x RDS(ON ) D TJ Typical RJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 50oC/W when mounted on a 1 in2 pad of 2oz copper. b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper. c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%. NDS8434A Rev.D Typical Electrical Characteristics -30 V GS = -4.5V I D , DRAIN-SOURCE CURRENT (A) -25 R DS(on), NORMALIZED DRAIN-SOURCE ON-RESISTANCE -3.0 -2.5 -2.0 1.8 V GS =-2.0V 1.6 -20 1.4 -15 -1.5 -2.5 1.2 -2.7 -10 -3.0 -3.5 -4.5 -5 1 0 0 -0.5 V DS -1 -1.5 , DRAIN-SOURCE VOLTAGE (V) -2 0.8 0 -6 -12 -18 ID , DRAIN CURRENT (A) -24 -30 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 DRAIN-SOURCE ON-RESISTANCE R DS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1.8 1.4 I D = -7.9A V GS = -4.5V 1.6 1.4 1.2 1 0.8 0.6 0.4 0 V GS = -4.5V TJ = 125C R DS(ON) , NORMALIZED 1.2 25C -55C 1 0.8 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C) 125 150 -5 -10 I D -15 -20 -25 -30 , DRAIN CURRENT (A) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Drain Current and Temperature. V DS = -5 V -20 T J = -55C VGS(th) , NORMALIZED GATE-SOURCE THRESHOLD VOLTAGE -25 1.4 1.2 1 0.8 0.6 0.4 0.2 -50 25C 125C VDS = VGS I D =-250A I , DRAIN CURRENT (A) -15 -10 D -5 0 0 -0.5 -1 -1.5 V , GATE TO SOURCE VOLTAGE (V) GS -2 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C) 125 150 Figure 5. Transfer Charateristics. Figure 6. Gate Threshold Variation with Temperature. NDS8434A Rev.D Typical Electrical Characteristics (continued) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.075 1.05 -I S , REVERSE DRAIN CURRENT (A) I D = -250A 20 10 VGS = 0V 1 TJ = 125C 0.1 1.025 25C -55C 1 0.01 0.975 0.001 0.95 -50 0.0001 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (C) 125 150 0 0.2 0.4 0.6 0.8 1 -V SD , BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 7. Breakdown Voltage Variation with Temperature. Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 6000 4000 3000 CAPACITANCE (pF) 2000 5 -V GS , GATE-SOURCE VOLTAGE (V) I D = -7.9A 4 VDS = -5V -15V -10V Ciss Coss 3 1000 2 500 f = 1 MHz V GS = 0 V 150 0 .1 0 .2 Crss 1 0 .5 1 2 5 -V , DRAIN TO SOURCE VOLTAGE (V) DS 10 20 0 0 10 Q g 20 , GATE CHARGE (nC) 30 40 Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics. -VDD V IN D ton t d(on) tr 90% t off t d(off) 90% tf RL V OUT DUT VGS VOUT 10% R GEN 10% 90% G V IN S 10% 50% 50% PULSE WIDTH INVERTED Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDS8434A Rev.D Typical Electrical and ThermalCharacteristics (continued) g FS, TRANSCONDUCTANCE (SIEMENS) 60 STEADY-STATE POWER DISSIPATION (W) 2.5 V DS = - 4.5V 50 40 30 20 10 0 TJ= -55C 25C 125C 1a 2 1.5 1b 1c 1 4.5"x5" FR-4 Board TA = 2 5 C Still Air o 0 -6 -12 -18 I D , DRAIN CURRENT (A) -24 -30 0.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 Figure 13. Transconductance Variation with Drain Current and Temperature. Figure 14. SO-8 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 8.5 -I D , STEADY-STATE DRAIN CURRENT (A) 8 7.5 7 6.5 1b 50 30 1a -I D, DRAIN CURRENT (A) 10 5 2 1 0.5 R (O DS N) LIM IT 100 us 1m s 10m s 10 0m s 6 5.5 5 1c 4.5"x5" FR-4 Board TA = 2 5 C Still Air VG S = - 4 . 5 V o 0.1 0.05 VGS = -4.5V SINGLE PULSE RJA = See Note 1c T A = 25C A 0.2 1s 10s DC 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 0.01 0.1 0.5 1 2 5 10 - V , DRAIN-SOURCE VOLTAGE (V) DS 20 40 Figure 15. Maximum Steady- State Drain Current versus Copper Mounting Pad Area. 1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE Figure 16. Maximum Safe Operating Area. 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0001 D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse P(pk) RJA (t) = r(t) * R JA R JA = See note 1c t1 t2 TJ - TA = P * R JA (t) Duty Cycle, D = t1 /t 2 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 17. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDS8434A Rev.D TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM DISCLAIMER ISOPLANARTM MICROWIRETM POPTM PowerTrenchTM QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 TinyLogicTM UHCTM VCXTM FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. |
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