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NJU6533
1/3, 1/4 Duty LCD Driver
GENERAL DESCRIPTION
NJU6533 is a 1/3 or 1/4 duty segment type LCD driver. It incorporates 4 common driver circuits and 32 segment driver circuits. NJU6533 can drive maximum 96 segments in 1/3 duty ratio and maximum 128 segments in 1/4 duty ratio. Be addition, the NJU6533's useful functions and small
PACKAGE OUTLINE
package meet a wide range of applications.
NJU6533C
NJU6533 KQ1
FEATURES
LCD driving circuit Programmable Duty Ratio 1/3 duty ratio 1/4 duty ratio Programmable Bias Ratio Serial Data Transfer Built-in Oscillator :Max. 32outputs (4 outputs as for general purpose ports)
NJU6533FG1
:Driving max. 96 segments :Driving max. 128 segments :1/2, 1/3 bias ratio :Shift clock max. 2MHz :CR oscillation with external resistor, or external oscillation signal input
Display OFF
Operating Voltage C-MOS Technology Package Outline
:INHb terminal
:3V / 5.0V :P-Sub :Bare Chip, QFN48, QFP64
BLOCK DIAGRAM
COM1 VDD VLCD V1 V2 VSS INHb OSC1 OSC2 CSb SCK SI RSTb COM Drivers COM4 SEG1 SEG8 SEG9 SEG16 SEG17 SEG24 SEG25 SEG32/P4
Segment Drivers /General Purpose Output Ports
Data Latch Circuit Oscillator
Display Data Register
Decoder
Command Register
Power ON Reset Circuit
Ver.2004-08-09
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NJU6533
PAD LOCATION
36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 1 234 56 78 9 10 11 12 TOP VIEW 24 23 22 21 20 19 18 17 16 15 14 13 Chip Center Chip Size Chip Thickness PAD Size PAD Pitch Sub Striate : X=0m, Y=0m : X= 2.60 mm, Y= 2.36 mm : 625m 25 m : 90.0 m x 90.0 m : 126m :P
PAD COORDINATES
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PAD NAME COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 X= m -686 -560 -434 -308 -182 -56 70 196 322 448 574 700 1138 1138 1138 1138 1138 1138 1138 1138 1138 1138 1138 1138 Chip Size 2.60 x 2.36 mm(Chip Center X=0m, Y=0m) PAD No. PAD NAME Y= m X= m Y= m -1019 25 SEG21 784 1019 -1019 26 SEG22 658 1019 -1019 27 SEG23 532 1019 -1019 28 SEG24 406 1019 -1019 29 SEG25 280 1019 -1019 30 SEG26 154 1019 -1019 31 SEG27 28 1019 -1019 32 SEG28 -98 1019 -1019 33 SEG29/P1 -356 1019 -1019 34 SEG30/P2 -482 1019 -1019 35 SEG31/P3 -837 1019 -1019 36 SEG32/P4 -963 1019 -739 37 VLCD -1138 914 -613 38 V1 -1138 790 -487 39 V2 -1138 557 -361 40 VSS -1138 432 -235 41 INHb -1138 236 -109 42 RSTb -1138 112 17 43 CSb -1138 -121 143 44 SI -1138 -245 269 45 SCK -1138 -479 395 46 VDD -1138 -603 521 47 OSC1 -1138 -845 647 48 OSC2 -1138 -971
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Ver.2004-08-09
NJU6533
PIN CONFIGURATION
*
QFN48
SEG32/P4 SEG31/P3 SEG30/P2 SEG29/P1 SEG22 SEG21 26 25 24 23 22 21 20 19 18 17 16 15 14 13 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 27
36
35 34 33
32 31
30
VLCD V1 V2 VSS INHb RSTb CSb SI SCK VDD OSC1 OSC2
37 38 39 40 41 42 43 44 45 46 47 48
29 28
SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
NJU6533KQ1
10 SEG6
COM1 COM2
COM3 COM4
SEG1 SEG2
SEG3
SEG4
SEG5
*
QFP64
NC SEG32/P4 SEG31/P3
SEG30/P2
SEG29/P1 SEG28
SEG27 SEG26
SEG25
SEG24 SEG23
SEG22 SEG21 NC 35
NC
SEG7 SEG8 34 33 32 31 30 29 28 27 26 NC
48
47 46 45 44
43 42 41
40 39
38
NC NC VLCD V1 V2 VSS INHb RSTb CSb SI SCK VDD OSC1 OSC2 NC NC
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 8 9 1 2 3 4 5 6 7
37 36
11 12
8 9
1
2
3 4 5
6 7
NC NC SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 NC NC
NJU6533FG1
25 24 23 22 21 20 19 18 17 16 NC
NC COM1 COM2
COM3
COM4 SEG1
SEG2 SEG3
SEG4
SEG5 SEG6
Ver.2004-08-09
SEG7 SEG8 NC
NC
-3-
NJU6533
TERMINAL DISCRIPTION
Bare Chip 46 37 38, 39 40 No. QFN48 46 37 38, 39 40 QFP64 60 51 52, 53 54 Pad Name VDD VLCD V1, V2 VSS Function Power supply: 3V /5V LCD driving voltage VLCD V1 V2 VSS, VLCD VDD Bias At 1/3 bias ratio, keep V1- V2 open. At 1/2 bias ratio, short V1- V2. GND VSS =0V Display OFF * When INHb is "H", display is ON, and when INHb is "L", display is off. When SEG29(P1)~SEG32 (P4) are selected as general purpose output ports, even if input "0" to INHb terminal, SEG29~32 will still be recognized as general purpose output ports. Reset When RSTb is "L", command register and latch circuit is reset. Chip select When CSb is "L", data can be read in. Serial data input (8 bit=1word) Serial clock External resistor connection terminal for CR oscillation, or external clock input terminal When external clock is used, input the signal to OSC1 and keep OSC2 open. Common driver outputs Segment driver outputs
41
41
55
INHb
42 43 44 45 47, 48 1~4 5~32
42 43 44 45 47, 48 1~4 5~32
56 57 58 59 61, 62 3~6 7~14, 19~30, 35~42
RSTb CSb SI SCK OSC1, OSC2 COM1 ~ COM4 SEG1 ~ SEG28
33~36
33~36
43~46
SEG29/P1~ SEG32/P4
1,2, 15~18, 31~34, 47~50, 63, 64 *: For details about INHb, please refer to "
Segment driver outputs/general purpose output ports These 4 terminals can be used as segment outputs or general purpose output ports by setting Command Register. When selected as general purpose ports, data can be outputted via these ports during COM1 timing. According to transferred data, "H"=VDD or "L"=VSS will be outputted. Non Connection These pins must be open.
NC
FUNCTION DESCRIPTION (5) Display OFF function (INHb terminal)".
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Ver.2004-08-09
NJU6533
FUNCTION DESCRIPTION
(1) Block Function * Oscillator The oscillator includes a built-in capacitor and an external resistor. It generates clock signal for LCD driving. use external clock, input the clock signal to OSC1 and keep OSC2 open.
*
When
Decoder Input serial data is decoded and sent to the appropriate block. Command Register Command data is written to this 8 bits command register to control NJU6533 operation. Display Data Register Data is written to this 8 bits register as display data. Latch Circuit Data stored in display data register is assigned to the corresponding SEG/port. Segment Driver/General Purpose Ports Basing on display data, segment drivers output LCD SEG driving signal. And, SEG29/P1 ~ SEG32/P4 terminals can be selected as segment driver output or general-purpose ports by instruction. Common Driver Common drivers output LCD COM driving signal. Power On Reset When power is on, NJU6533 is automatically initialized. And if RSTb="L", NJU6533 is reset too.
*
*
*
*
*
*
Ver.2004-08-09
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NJU6533
(2) Serial Data Transfer The transfer of an 8-bit/word serial data is conducted by synchronizing clock via interface with CPU. serial data is obtainable and will be read in at the rising edge of SCK signal. During CSb="L",
After CSb becoming low, if the first word is address data, the after data can be transferred continually and interrupted as display data even if CSb maintained low. In this case, every 8 bits data will be confirmed as a word either by the falling edge of the8th SCK clock or by the rising edge of the CSb clock. After CSb becoming low, if the first word is command data, the after data is invalid even though transfer can be continued without changing the polarity of CSb. At the falling edge of CSb, SCK can be either "H" or "L", but, at the rising edge of CSb, SCK must be low. At this falling edge, one word is confirmed
*
SCK and SI SCK
SI
D7
D6
D5
D4
D3
D2
D1
D0
Timing of Serial Data Transfer At this rising edge of CSb, SCK="Lo", one word is confirmed. when
CSb
SCK
WORD 1 WORD2 WORD n
SI
Serial Interface Format
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Ver.2004-08-09
NJU6533
(3) Command Register Command Register is used to set the duty ratio, the bias ratio, and the SEG driver/general purpose ports. When the D7 to D5 bits of the 1st word are (1,0,0), the D4 ~ D0 bits are recognized as command data. The contents of Command Register will be initialized as following when applying Power On Reset or Reset. The Default Value of Command Register * Duty ratio : 1/4 * Bias ratio : 1/3 * SEG driver/General purpose ports : SEG drivers(SEG29, SEG30, SEG31, SEG32) D7 1 D6 0 D5 0 D4 DS D3 BS D2 TSEL2 D1 TSEL1 D0 TSEL0
Flag bits Duty Ratio
Duty ratio
Bias ratio
SEG driver or general purpose ports
*
DS Duty ratio 0 1/4 1 1/3 *) Do not change the duty ratio during display ON. Bias ratio BS 0 1 Bias ratio 1/3 1/2
*
*
SEG driver or general purpose ports TSEL2 TSEL1 TSEL0 SEG29/P1 SEG30/P2 SEG31/P3 SEG32/P4 0 0 0 SEG29 SEG30 SEG31 SEG32 0 0 1 SEG29 SEG30 SEG31 P4 0 1 0 SEG29 SEG30 P3 P4 0 1 1 SEG29 P2 P3 P4 1 0 0 P1 P2 P3 P4 **) If TSEL2 ~ TSEL0 is set to (1, 0, 1), (1, 1, 0), (1, 1, 1) all outputs are used as segment drivers.
Ver.2004-08-09
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NJU6533
(4) Output Address Counter Output Address Counter will specify the addresses of the SEG and COM drivers for the display data. When the MSB (D7 to D4) of the 1st data is "0111", the LSB 4 bits (D3 to D0) specify the addresses of COM and SEG drivers, and the 2nd data is the display data which will be sent to the 1st-data-specified drivers. At the same time, SEG and COM driver addresses will be increased automatically in turn as shown in Table 1. In other words, as of the SEG and COM driver addresses specified by the first data in the Output Address Counter, display data can be transferred to the SEG and COM drivers without further address setting. The address setting range is from "0000" to "1111", if transfer data outnumber the address number which are from D3 ~ D0 to "1111", the SEG and COM driver address will be reset to "0000" and renew the auto-increment operation.
*
Address Data D7 0
D6 1
D5 1
D4 1
D3 C1
D2 C0
D1 S1
D0 S0
Flag bits
COM driver Address
SEG driver Address
Table 1. The Relationship Between Output Address and SEG/COM Drivers SEG Driver COM C1 C0 S1 S0 Driver D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 0 1 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 1 0 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 1 1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 0 1 0 0 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 0 1 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 1 0 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 1 1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 1 0 0 0 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 0 1 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 1 0 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 1 1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 1 1 0 0 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 0 1 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 1 0 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 1 1 If general purpose ports are selected by Command Register, under (C1, C0, S1, S0)=(0, 0, 1, 1), D4 ~ D7 bits are the addresses of (P1, P2, P3, P4) ports which corresponds to (SEG29, SEG30, SEG31, SEG32). When SEG29~SEG32 are set as general purpose output ports, data for SEG29~SEG32 during COM2~COM4 scanning will be ignored. When duty ratio is 1/3, do not set address between"1100"~"1111". Otherwise, unexpected address way be setup.
Increment Direction
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Ver.2004-08-09
NJU6533
(5) Display OFF Function (INHb) When INHb="L" * All segment and common terminal output VSS (When general purpose output ports are selected, even INHb="L", these ports can output data) * Suspending Oscillation (but, if RSTb="L", oscillator works) * V1 and V2 beome "H" (no current pass through the bleeder resistors) Even during INHb="L", interface can be accessed, and data can be written into the command register, address counter and data register. (6) Power ON Reset After power ON, NJU6533 is initialized to the following values: * Address counter (C1, C0, S1, S0)=(0, 0, 0, 0) * Duty ratio 1/4duty * Bias ratio 1/3 bias * Segment/General purpose port: Segment output(SEG29, SEG30, SEG31, SEG32) (7) Sequence of Initialization (7-1) 1/3duty, SEG32 used as general purpose port, data written in from COM2. Power on
Set INHb to "L"
Pixels off D7 1 D7 0 D6 0 D6 1 D5 0 D5 1 D4 1 D4 1 D3 0 D3 0 D2 0 D2 1 D1 0 D1 0 D0 1 D0 0
Set Command Register
Duty ratio=1/3, SEG32 as general purpose port COM driver address=01 SEG driver address=00
Set output address
Display data written in
Set INHb to "H"
Pixels on
(7-2) 1/4duty, SEG29 ~ 32 used as SEG drivers, data written in from COM1. Power on
Set INHb to "L"
Pixels off D7 1 D7 0 D6 0 D6 1 D5 0 D5 1 D4 0 D4 1 D3 0 D3 0 D2 0 D2 0 D1 0 D1 0 D0 0 D0 0
Set Command Register
Duty ratio =1/4
Set output address
COM driver address =00 SEG driver address=00
Display data written in
Set INHb to "H"
Pixels on
Ver.2004-08-09
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NJU6533
ABSOLUTE MAXIMAM RATINGS
PARAMETER Supply Voltage 1 Supply Voltage 2 Supply Voltage 3 Input Voltage Operating Temp. Storage Temp. Dissipation Power Note-1) Note-2) Note-3) Note-4) SYMBOL VDD VLCD V 1, V 2 VIN Topr Tstg PD RATINGS -0.3 ~ +6.0 -0.3 ~ +6.0 -0.3 ~ VLCD+0.3 -0.3 ~ VDD+0.3 -40 ~ +85 -55 ~ +125 710(QFN48) 750(QFP64-G1) UNIT V V V V C C mW (VSS=0V, Ta=25C) CONDITIONS
INHb, CSb, SCK, SI, RSTb, OSC1 applicable.
The power dissipation is value mounted on a glass epoxy board in size 50mm x50mm x1.6mm(QFN48), 76.2mm x114.3mm x1.6mm(QFP64-G1). Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also recommended that the IC be used within the range specified in the DC electrical characteristics, or the electrical stress may cause mulfunctions and impact on the reliability. All voltages are relative to VSS = 0V reference. The following relationship shall be maintained. VLCD V1 V2 VSS, VLCD VDD, and VLCD shall be input after VDD. To stabilize the LSI operation, place decoupling capacitors between VDD-VSS and between VLCD-VSS.
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Ver.2004-08-09
NJU6533
ELECTRICAL CHARACTERISTICS
*
DC characteristics 1 (VDD=2.4 to 3.6V, VSS=0V, Ta=-40 to 85C) PARAMETER
Power Supply LCD Driving Voltage LCD Bias Voltage "H" Level Input Voltage "L" Level Input Voltage Hysteresis Voltage "H" Level Input Current "L" Level Input Current "H" Level Output Voltage "L" Level Output Voltage Driver-on Resistance (COM) Driver-on Resistance (SEG) Oscillating Frequency External Clock Frequency External Clock Duty Bleeder Resistor
SYM BOL
VDD VLCD V1 V2 VIH VIL VH IIH IIL VOH VOL RCOM RSEG fOSC fCP duty RB IDD1 IDD2
CONDITIONS VLCD VDD
Ta=25C Testing via COM/SEG terminals COM/SEG without load INHb, CSb, SCK, SI, RESb, OSC1 INHb, CSb, SCK, SI, RESb, OSC1 INHb, CSb, SCK, SI, RESb VIN= VDD INHb, CSb, SCK, SI, RESb VIN= VSS INHb, CSb, SCK, SI, RESb VDD =3V, IO=5mA, P1 to P4 VDD =3V, IO=5mA, P1 to P4 Id=1A, VLCD=3V/5.5V Id=1A, VLCD=3V/5.5V VDD =3V, ROSC=750k, Ta=25C Input into OSC1 Input into OSC1 VLCD-VSS Ta=25C VDD =3V, INHb="L", RSTb="H", Ta=25C VDD =3V, VLCD=5V, Ta=25C, Checker flag display, 1/3 bias Using internal oscillator, no output VDD=3V, VLCD=5V, RSTb="H", INHb="L", Ta=25C VDD =3V, VLCD=5V, Ta=25C, Checker flag display, 1/3 bias Using internal oscillator, no output
MIN
2.4 2.4
TYP
MAX
3.6 5.5
UNIT Note V V V V V V V A A V
2/3 VLCD-0.2 2/3 VLCD 2/3 VLCD+0.2 1/3 VLCD-0.2 1/3 VLCD 1/3 VLCD+0.2 0.8 VDD 0 0.2VDD 1.0 1.0 VDD-0.6 0.6 12.6 12.6 45 127 15.4 15.4 50 150 1.7 7.0 0.1 34 10 10 18.2 18.2 55 173 8.0 25 1.0 60 VDD 0.2 VDD
V k k kHz kHz % k A A A A 5 5
Operating Current ILCD1 ILCD2
Note-5) Driver-On resistance (RSEG/RCOM) is measured from VLCD, VSS, V1 or V2 terminal to each SEG/COM terminal when Id current flows through COM/SEG terminals. Note-6) ["H" Level Input Voltage], ["L" Level Input Voltage], [Hysteresis Voltage], ["H" Level Input Current], ["L" Level Input Current], [External Clock Frequency] and [External Clock Duty] are as the same as if VDD=4.5 to 5.5V.
Ver.2004-08-09
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NJU6533
*
DC characteristics 2 (VDD=4.5 to 5.5V, VSS=0V, Ta=-40 to 85C) PARAMETER
Power Supply LCD Driving Voltage LCD Bias Voltage "H" Level Input Voltage "L" Level Input Voltage Hysteresis Voltage "H" Level Input Current "L" Level Input Current "H" Level Output Voltage "L" Level Output Voltage Driver-on Resistance (COM) Driver-on Resistance (SEG) Oscillating Frequency External Clock Frequency External Clock Duty Bleeder Resistor
SYM BOL
VDD VLCD V1 V2 VIH VIL VH IIH IIL VOH VOL RCOM RSEG fOSC fCP duty RB IDD1 IDD2
CONDITIONS VLCD VDD
Ta=25C Testing via COM/SEG terminals COM/SEG without load INHb, CSb, SCK, SI, RESb, OSC1 INHb, CSb, SCK, SI, RESb, OSC1 INHb, CSb, SCK, SI, RESb VIN= VDD INHb, CSb, SCK, SI, RESb VIN= VSS INHb, CSb, SCK, SI, RESb VDD =3V, IO=5mA, P1 to P4 VDD =3V, IO=5mA, P1 to P4 Id=1A, VLCD=3V/5.5V Id=1A, VLCD=3V/5.5V VDD =3V, ROSC=750k, Ta=25C Input into OSC1 Input into OSC1 VLCD-VSS Ta=25C VDD =3V, INHb="L", RSTb="H", Ta=25C VDD =3V, VLCD=5V, Ta=25C, Checker flag display, 1/3 bias Using internal oscillator, no output VDD =3V, VLCD=5V, INHb="L", RSTb="H",Ta=25C VDD =3V, VLCD=5V, Ta=25C, Checker flag display, 1/3 bias Using internal oscillator, no output
MIN
4.5 4.5
TYP
MAX
5.5 5.5
UNIT Note
V V V V V V V A A V
2/3 VLCD-0.2 2/3 VLCD 2/3 VLCD+0.2 1/3 VLCD-0.2 1/3 VLCD 2/3 VLCD+0.2 0.8VDD 0 0.2VDD 1.0 1.0 VDD-1.0 1.0 12.6 12.6 45 127 15.4 15.4 50 150 3.2 15 0.1 34 10 10 18.2 18.2 55 173 10 35 1.0 60 VDD 0.2 VDD
V k k kHz kHz % k A A A A 7 7
Operating Current ILCD1 ILCD2
Note-7) Driver-On resistance (RSEG/RCOM) is measured from VLCD, VSS, V1 or V2 terminal to each SEG/COM terminal when Id current flows through COM/SEG terminals. Note-8) ["H" Level Input Voltage], ["L" Level Input Voltage], [Hysteresis Voltage], ["H" Level Input Current], ["L" Level Input Current], [External Clock Frequency] and [External Clock Duty] are as the same as if VDD=2.4 to 3.6V.
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Ver.2004-08-09
NJU6533
*
AC characteristics
(VDD=VLCD=2.4 to 5.5V, VSS=0V, Ta=-40 to 85C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Note "L" Level Clock Pulse Width tWCLL 230 ns "H" Level Clock Pulse Width tWCLH 230 ns Data Setup Time tDS 20 ns Data Hold Time tDH 20 ns CSb Wait Time tCP 50 ns 9 CSb Setup Time tCS 50 ns CSb Hold Time tCH 50 ns CSb"H" Level Pulse Width tWCH 50 ns Rising Time tr 20 ns Falling Time tf 20 ns Note-9) tCP is the time when SCK is kept at "H" during CSb changed from "H" to "L".
*
Input Timing tWCH CSb tCP tCS VIL VIL tDS SI tDH tWCLH tWCLL tf tr tCH
SCK
*
Input condition when hardware reset circuit is used PARAMETER Reset Input "L" Level Width Reset Rising Time Reset Falling Time SYMBOL tRSL trRS tfRS tfRS VIH RSTb VIL CONDITIONS fOSC= 15.4kHz MIN 1.5 TYP MAX 100 100 tRSL trRS (Ta=25C) UNIT ms ns ns
*
Power supply condition when hardware reset circuit is used PARAMETER Power-on Rising Time Power-off Time SYMBOL trDD tOFF 2.2V VDD 0.2V 0.2V CONDITIONS MIN 0.1 1 TYP (Ta=-40 to 85C) MAX UNIT 5 ms ms
trDD tOFF Note 10) tOFF is the off time when power-supply turns off suddenly or cycles on/off.
Ver.2004-08-09
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NJU6533
LCD DRIVING WAVEFORM
(a) 1/3 duty, 1/2 bias COM1
VLCD V1,V2 VSS
COM2
VLCD V1,V2 VSS
COM3
VLCD V1,V2 VSS
COM4
VLCD V1,V2 VSS
"OFF" segment output correspond to COM1, 2 and 3.
VLCD V1,V2 VSS
"ON" segment output correspond to COM1.
VLCD V1,V2 VSS
"ON" segment output correspond to COM2.
VLCD V1,V2 VSS
"ON" segment output correspond to COM1 and COM2.
VLCD V1,V2 VSS
"ON" segment output correspond to COM3.
VLCD V1,V2 VSS
"ON" segment output correspond to COM1 and COM3.
VLCD V1,V2 VSS
"ON" segment output correspond to COM2 and COM3.
VLCD V1,V2 VSS
"ON" segment output COM1, 2 and COM3.
correspond
to 1/3 duty, 1/2 bias
VLCD V1,V2 VSS
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Ver.2004-08-09
NJU6533
(b) 1/3 duty, 1/3 bias COM1
VLCD V1 V2 VSS
COM2
VLCD V1 V2 VSS
COM3
VLCD V1 V2 VSS
COM4
VLCD V1 V2 VSS
"OFF" segment output correspond to COM1, 2 and 3.
VLCD V1 V2 VSS
"ON" segment output correspond to COM1.
VLCD V1 V2 VSS
"ON" segment output correspond to COM2.
VLCD V1 V2 VSS
"ON" segment output correspond to COM1 and COM2.
VLCD V1 V2 VSS
"ON" segment output correspond to COM3.
VLCD V1 V2 VSS
"ON" segment output correspond to COM1 and COM3.
VLCD V1 V2 VSS
"ON" segment output correspond to COM2 and COM3.
VLCD V1 V2 VSS
"ON" segment output correspond to COM1, 2 and COM3. 1/3 duty, 1/3 bias
VLCD V1 V2 VSS
Ver.2004-08-09
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NJU6533
(c) 1/4 duty, 1/2 bias COM1
VLCD V1,V2 VSS
COM2
VLCD V1,V2 VSS VLCD V1,V2 VSS VLCD V1,V2 VSS
COM3
COM4
"OFF" segment output correspond to COM1, 2, 3 and 4. "ON" segment output correspond to COM1. "ON" segment output correspond to COM2. "ON" segment output correspond to COM1 and 2. "ON" segment output correspond to COM3. "ON" segment output correspond to COM1 and 3. "ON" segment output correspond to COM2 and 3. "ON" segment output correspond to COM1, 2 and 3. "ON" segment output correspond to COM4. "ON" segment output correspond to COM2 and 4. "ON" segment output correspond to COM1, 2, 3 and 4. 1/4 duty, 1/2 bias
VLCD V1,V2 VSS VLCD V1,V2 VSS VLCD V1,V2 VSS VLCD V1,V2 VSS
VLCD V1,V2 VSS VLCD V1,V2 VSS
VLCD V1,V2 VSS VLCD V1,V2 VSS VLCD V1,V2 VSS
VLCD V1,V2 VSS VLCD V1,V2 VSS
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Ver.2004-08-09
NJU6533
(d) 1/4 duty, 1/3 bias COM1
VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS VLCD V1 V2 VSS
COM2
COM3
COM4
"OFF" segment output correspond to COM1, 2, 3 and 4. "ON" segment output correspond to COM1. "ON" segment output correspond to COM2. "ON" segment output correspond to COM1 and 2. "ON" segment output correspond to COM3. "ON" segment output correspond to COM1 and 3. "ON" segment output correspond to COM2 and 3. "ON" segment output correspond to COM1, 2 and 3. "ON" segment output correspond to COM4. "ON" segment output correspond to COM2 and 4. "ON" segment output correspond to COM1, 2, 3 and 4. 1/4 duty, 1/3 bias
Ver.2004-08-09
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NJU6533
APPLICATION CIRCUIT
*
1/4 duty, 1/3 bias VLCD VDD + + VLCD VDD VSS V1 V2 RSTb INHb CSb SCK SI OSC1 COM1 COM2 COM3 COM4 OSC2 SEG32/P4 SEG1
*Typical Capacitance:1F
NJU6533
From MPU
LCD Panel
*
1/4 duty, 1/2 bias VLCD VDD + + VLCD VDD VSS V1 V2 RSTb INHb CSb SCK SI OSC1 COM1 COM2 COM3 COM4 OSC2 SEG32/P4 SEG1
*Typical Capacitance:1F
NJU6533
From MPU
LCD Panel
Note)
Because display data is not yet stable just after VDD on, if LCD panel is turned on, unexpected pattern will be displayed, therefore, keep INHb terminal to "L" level until data transfer from MPU is over.
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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Ver.2004-08-09

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