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| NJU7706/07 VOLTAGE DETECTOR ! GENERAL DESCRIPTION The NJU7706/07 is a high precision voltage detector with a built-in delay time generator of fixed time. The NJU7706/07 are useful for preventing malfunction of microcomputer or DSP etc. through detect a drop in voltage of battery or power supply. The delay function achieves set wait time when supply voltage is unstable. Moreover, the delay function can make a sequence that other devices in application work and stabilize before microcomputer or DSP works. The detection voltage is internally fixed with an accuracy of 1.0%, and three fixed delay times 50ms, 100ms and 200ms are available. Manual reset function can output reset signal irrespective of detection voltage. NJU7706 is Nch. Open Drain and NJU7707 is a C-MOS output type. Small packaging makes NJU7706 and NJU7707 suitable for space conscious applications. ! PACKAGE OUTLINE NJU7706/07F ! FEATURES " High Precision Detection Voltage 1.0% " Low Quiescent Current 1.3A typ. " Detection Voltage Range 1.5 6.0V(0.1V step) " Delay Time(Built-in Fixed Type) 50ms /100ms /200ms(Built-in Fixed Type) " ON/OFF switch of delay time(DS pin) " Manual Reset Active "L" : NJU770*F**A Active "H" : NJU770*F**B " Output Configuration NJU7706: Nch. Open Drain type NJU7707: C-MOS Output type " Package Outline SOT-23-5 ! PIN CONFIGURATION 5 4 123 NJU7706/07F PIN FUNCTION 1.DS 2.VSS 3.MR 4.VOUT 5.VDD Ver.2005-02-28 -1- NJU7706/07 ! EQUIVALENT CIRCUIT V DD VDD Delay Circuit Vref V OUT Vref Delay Circuit V OUT VSS DS MR VSS DS MR NJU7706**A* VDD V DD NJU7706**B* Delay Circuit Vref V OUT Vref Delay Circuit V OUT V SS DS MR VSS DS MR NJU7707**A* ! DETECTION VOLTAGE RANK LIST Device Name NJM770*F27A1 NJU770*F39A1 NJU770*F42A1 NJM770*F27B1 NJU770*F15A2 NJU770*F19A2 NJU770*F21A2 NJU770*F22A2 NJU770*F25A2 NJU770*F27A2 NJU770*F28A2 NJU770*F29A2 NJU770*F03A2 NJU770*F42A2 NJU770*F43A2 NJU770*F45A2 NJU770*F06A2 NJU770*F25B2 NJU770*F27B2 NJU770*F42B2 NJU770*F27A3 NJU770*F39A3 NJU770*F42A3 NJU770*F27B3 VDET 2.7V 3.9V 4.2V 2.7V 1.5V 1.9V 2.1V 2.2V 2.5V 2.7V 2.8V 2.9V 3.0V 4.2V 4.3V 4.5V 6.0V 2.5V 2.7V 4.2V 2.7V 3.9V 4.2V 2.7V MR Logic Active "L" Active "H" Delay Time 50ms NJU7707**B* Active "L" 100ms Active "H" Active "L" Active "H" 200ms -2- Ver.2005-02-28 NJU7706/07 ! NJU7706 ! ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Input Voltage VDD Output Voltage VOUT Output Current IOUT (Ta=25C) RATINGS UNIT +10 V V VSS-0.3 +10 50 mA 350(*1) Power Dissipation PD SOT-23-5 mW 200(*2) Operating Temperature Topr -40 +85 C Storage Temperature Tstg -40 +125 C (*1) : Mounted on glass epoxy board based on EIA/JEDEC. (114.3x76.2x1.6mm: 2Layers) (*2) : Device itself ! ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Detection Voltage VDET Hysteresis Voltage VHYS Quiescent Current Output Current ISS IOUT (Ta=25C) MAX. UNIT +1.0% V 130 mV 1.7 A 2.2 - mA - 0.1 A - 57.5 115 230 300 VDD 0.3 VDD 0.3 VDD VDD-1.5 ppm/C ms ms ms s V V V V V V TEST CONDITION VDD=VDET+1V Nch,VDS=0.5V VDET=1.5V 1.9V Version VDET=2.0V 6.0V Version VDD=1.2V VDD=2.4V (2.7V Version) Output Leak Current ILEAK VDD=VOUT=9V Detection Voltage Temperature VDET /Ta Ta=0 +85C Coefficient Delay Time 1 td1 VDD=VDET+1V, DS="L Level" NJU7706F***1 NJU7706F***2 NJU7706F***3 VDD=VDET+1V, DS="H Level" MIN. -1.0% 70 - - 0.75 4.5 - - 42.5 85 170 25 1.5 0 1.5 0 VDD-0.3 0 TYP. - 90 1.0 1.3 2.0 7.0 - 100 50 100 200 100 - - - - - - Delay Time 2 td2 VDS_H Input Voltage of DS pin VDS_L VMR_H Input Voltage of MR pin (Active "L") VMR_L VMR_H Input Voltage of MR pin (Active "H") VMR_L Impedance of 1.0 2.0 3.0 RMR M MR pin Operating Voltage 0.8 9 V VDD RL=100k - (*3) (*3): The minimum operating voltage(VOPL) indicates the same value of the input voltage(VDD) on condition that VOUT becomes 10% or less of the input voltage(VDD). Ver.2005-02-28 -3- NJU7706/07 ! TEST CIRCUIT " Circuit Operating Current TEST CIRCUIT " Detection voltage / Minimum operating voltage TEST CIRCUIT ISS A V DD V OUT V DD MR V DET / V OPL V RL V DD V OUT V MR V OUT NJM7706 V DD DS V SS NJM7706 DS V SS " MR pin Input voltage TEST CIRCUIT " Leak current / Output current TEST CIRCUIT RL V DD V DD DS V OUT V MR V MR V V MR V DD DS V DD V OUT ILEAK/ IOUT A NJM7706 NJM7706 MR V OUT / V DS V SS V SS " Delay time1 TEST CIRCUIT Oscilloscope " Delay time2 TEST CIRCUIT Oscilloscope RL V DD V DD DS V OUT ch1 ch2 RL V DD V DD V OUT ch1 ch2 NJM7706 MR NJM7706 DS MR V SS V SS -4- Ver.2005-02-28 NJU7706/07 ! TYPICAL APPLICATION 1 Power Supply Monitor Circuit (VDD line COMMON) V DD RL V DD V OUT Reset Signal INPUT Micro-Processor etc NJM7706 DS MR V SS 2 Power Supply Monitor Circuit (VDD line SEPARATE) V DD1 V DD2 RL V DD V OUT Reset Signal INPUT Micro-Processor etc NJM7706 DS MR V SS Ver.2005-02-28 -5- NJU7706/07 ! NJU7707 ! ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Input Voltage VDD Output Voltage VOUT Output Current IOUT (Ta=25C) RATINGS UNIT +10 V V VSS-0.3 VDD+0.3 50 mA SOT-23- 350(*4) mW Power Dissipation PD 5 200(*5) Operating Temperature Topr -40 +85 C Storage Temperature Tstg -40 +125 C (*4) : Mounted on glass epoxy board based on EIA/JEDEC. (114.3x76.2x1.6mm: 2Layers) (*5) : Device itself ! ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Detection Voltage VDET Hysteresis Voltage VHYS Quiescent Current ISS (Ta=25C) MAX. UNIT +1.0% V 130 mV 1.7 A 2.2 - - - mA - - - 57.5 115 230 300 VDD 0.3 VDD 0.3 VDD VDD-1.5 ppm/C ms ms ms s V V V V V V TEST CONDITION VDD=VDET+1V Nch, VDS=0.5V Output Current IOUT Pch, VDS=0.5V VDET=1.5V 1.9V Version VDET=2.0V 6.0V Version VDD=1.2V VDD=2.4V (2.7V Version) VDD=4.8V (3.9V Version) VDD=6.0V (4.0V 5.6V Version) VDD=8.4V (5.7V Version) MIN. -1.0% 70 - - 0.75 4.5 2.0 2.5 3.0 - 42.5 85 170 25 1.5 0 1.5 0 VDD-0.3 0 TYP. - 90 1.0 1.3 2.0 7.0 3.5 4.0 5.0 100 50 100 200 50 - - - - - - Detection Voltage Temperature Coefficient Delay Time 1 VDET /Ta Ta=0 +85C VDD=VDET+1V, DS="L Level" NJU7707F***1 NJU7707F***2 NJU7707F***3 VDD=VDET+1V, DS="H Level" td1 Delay Time 2 td2 VDS_H Input Voltage of DS pin VDS_L VMR_H Input Voltage of MR pin (Active "L") VMR_L VMR_H Input Voltage of MR pin (Active "H") VMR_L Impedance of 1.0 2.0 3.0 RMR M MR pin Operating Voltage 0.8 9 V VDD RL=100k - (*6) (*6): The minimum operating voltage(VOPL) indicates the same value of the input voltage(VDD) on condition that VOUT becomes 10% or less of the input voltage(VDD). -6- Ver.2005-02-28 NJU7706/07 ! TEST CIRCUIT " Circuit Operating Current TEST CIRCUIT ISS A V DD V DET V OUT V DD MR DS V V DD " Detection voltage TEST CIRCUIT V OUT V MR V OUT NJM7707 DS NJM7707 V SS V SS " MR pin Input voltage TEST CIRCUIT " Nch Output current TEST CIRCUIT IOUT V DD V DD DS V OUT V MR V MR V V MR V OUT V DD DS V DD V OUT A NJM7707 NJM7707 MR V DS V SS V SS " Pch Output current TEST CIRCUIT V DS IOUT V DD V DD DS V OUT A NJM7707 MR V SS Ver.2005-02-28 -7- NJU7706/07 " Delay time1 TEST CIRCUIT Oscilloscope " Delay time2 TEST CIRCUIT Oscilloscope ch1 ch2 ch1 ch2 V DD V DD V OUT V DD V DD V OUT NJM7707 DS MR NJM7707 DS MR V SS V SS " Minimum operating voltage TEST CIRCUIT RL V OPL V V DD DS V DD V OUT V MR V OUT NJM7707 V SS ! TYPICAL APPLICATION 1 Power Supply Monitor Circuit (VDD line COMMON) V DD V DD V OUT NJM7707 DS MR Reset Signal INPUT Micro-Processor etc V SS -8- Ver.2005-02-28 NJU7706/07 ! Functional Description (1) Basic operation Supply voltage (VDD) Detection voltage (VDET) Minimum operation voltage (VOPL) VSS Hysteresis voltage (VHYS) Release voltage (VDET + VHYS) Output voltage (VOUT) (1) When supply voltage(VDD) drops below detection voltage(VDET), Output voltage(VOUT) changes "H" to "L" to alert reset state. (2) The reset state is kept while VDD is lower than release voltage. The release voltage is a sum of VDET and Hysterisis voltage (VHYS). Please refer to the (*7) below. (3) When VDD becomes higher than the release voltage and reset release delay time fixed by internal is past, then VOUT changes from "L" to "H" to resume normal state. VSS (*7) VHYS is to avoid unstable VOUT state caused by rapid voltage change at nearby VDET. Delay time (*8): C-MOS output product (NJU7707) : When VDD less than VOPL, VOUT is free of the shaded region. (2) Description of Manual Reset Reset signal can output independently with MR. Logic of MR Operation Active "L" VMR= "L" => Reset "ON" Active "H" VMR= "H" => Reset "ON" If Manual Reset is not required, please connect MR terminal as following. Logic of MR Connection Active "L" Connect MR terminal to VDD or open Active "H" Connect MR terminal to GND or open [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2005-02-28 -9- |
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