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| NJU8716A/B PRELIMINARY Switching Driver with Regulator for Class-D Headphone Amplifier GENERAL DESCRIPTION The NJU8716A/B is switching driver with regulator for class-D headphone amplifier. It incorporates optimum regulator for the driver of headphone amplifier. The NJU8716A/B converts 1bit audio signals such as PWM/PDM to analog audio signals with simple external LC low-pass filter. The NJU8716A/B provides completed digital system and high power-efficiency with class-D operation. Therefore it is suitable for portable audio applications. PACKAGE OUTLINE NJU8716AV, NJU8716BV FEATURES 2-channel 1bit Audio Signal Input Headphone Output Built-in Regulator for Driver Logic Operating Voltage 1.7~3.0V(VDD) Driver Operating Voltage 1.6~3.5V(VDDO1, VDDO2) Regulator Operating Voltage 4.0~5.75V(VREG1) 1.9~4.0V(VREG2) C-MOS Technology Package Outline SSOP16 PIN CONFIGURATION VREGO CFB VREG1 VCONT VSS MCK VDD DIN2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VREG2 VDDO2 OUT2 VSSO VSSO OUT1 VDDO1 DIN1 Version Lineup Version NJU8716A NJU8716B Data Latch The rising edge of MCK The falling edge of MCK BLOCK DIAGRAM VCONT VREG1 VREG2 CFB VREGO Low Voltage Detector VREGO VDD VSS DIN1 Low Voltage Detector VDD Regulator VDDO1 Level Shifter Pre Driver HP Amp OUT1 VSSO VDDO2 Level Shifter MCK Level Shifter Pre Driver DIN2 Level Shifter HP Amp OUT2 VSSO Ver.2005-03-09 -1- NJU8716A/B TERMINAL DESCRIPTION No. 1 2 3 16 4 5 6 7 9 8 10 15 11 14 12 13 SYMBOL VREGO CFB VREG1 VREG2 VCONT VSS MCK VDD DIN1 DIN2 VDDO1 VDDO2 OUT1 OUT2 VSSO I/O O I I I I O FUNCTION Regulator Output Terminal Regulator Output Voltage Sense Terminal Regulator Power Supply Regulator Output Voltage Control Terminal Power GND:VSS=0V Master Clock Input Terminal Audio signals are latched on the edge of MCK. A Version: latched on the rising edge B version: latched on the falling edge Power Supply: VDD=2.0V Audio Signal Input Terminal 1,2 Driver Power Supply 1,2 Output Terminal 1,2 Driver GND: VSSO=0V INPUT TERMINAL STRUCTURE MCK, DIN1, DIN2 VDD Input Terminal VSS Internal Circuit -2- Ver.2005-03-09 NJU8716A/B NJU3555 FUNCTIONAL DESCRIPTION (1) Power Supply VDD : Power supply for input circuit and control logic. Keep the input logic level less than VDD. If VDD reaches less than sleep detection voltage, power consumption can be saved with halts of built-in regulator. VREG1 : Power supply for built-in regulator. Even after power-on, VREG1 line is shut off with transistor switch until VDD has been started up. VREG2 : Power supply for built-in regulator. Apply the required voltage with additional dropout voltage of regulator. By connecting VREGO (regulator output) to VDDO1, VDDO2 (Driver power supply), the power is provided at the drivers. And furthermore, the regulator output should be supplied to VDDO1 and VDDO2 by connecting de-coupling capacitor to get highly smoothed power supply. (2) Regulator Output Voltage Control Terminal (VCONT) VCONT is the control terminal for regulator output voltage. VREGO terminal generates double the voltage of supplied voltage to VCONT. (Shorted between VREGO-CFB) (3) Master Clock (MCK) Master clock (MCK) synchronizes the audio signal inputs (DIN1 and DIN2). The setup time and the hold time should be kept in the AC characteristics because DIN1 and DIN2 are fetched with the rising edge of MCK in A version, and the falling edge of MCK in B version. During the standby condition, MCK requires "L" level to avoid unnecessary power consumption. In addition, MCK requires jitter-free or jitter as small as possible because the jitter could lead to poor S/N ratio. (4) Signal Output (OUT1 / OUT2) OUT1 and OUT2 terminals keep the Hi-z condition if output voltage of VREGO is lower than detection voltage. Output signals are appeared as PWM signals through the use of VDDO1 and VDDO2 in the OUT1 and OUT2 terminals If the output voltage is over than detection voltage. Output signals will be converted to analog signals via 2nd-order or higher LC filter. POWER ON/DOWN SEQUENCE The pop-noise can be effectively suppressed with the following sequence when power ON and OFF. (1) Power ON Sequence 1) Start up VDD, VREG1 and VREG2. 2) Input the master clock (MCK) and audio signals (DIN1, DIN2) after the start-up of VDD, VREG1 and VREG2. At this time, audio signals must be input as "Sound-less data". 3) Increase VCONT. 4) Input the audio data after VCONT reaches a steady state. (2) Power Down Sequence The sequence must be executed in inverse order of the power ON sequence. VDD, VREG1, VREG2 VCONT MCK DIN1, DIN2 OUT1, OUT2 Sound-less Data High impedance Audio Data Sound-less Data High impedance Audio signal output Ver.2005-03-09 -3- NJU8716A/B ABSOLUTE MAXMUM RATINGS (Ta=25C) PARAMETER SYMBOL VDD Supply Voltage VDDO1, 2 VREG1 VREG2 Input Voltage Operating Temperature Storage Temperature Power Dissipation Vin Ta Tstg PD RATING -0.3 ~ +4.0 -0.3 ~ +4.0 VREG2 ~ +6.0 -0.3 ~ +5.5 -0.3 ~ VDD+0.3 -20 ~ +85 -40 ~ +125 300 (SSOP16) UNIT V V V V V C C mW Note.1) The relations of "VDDO1,VDDO2 (1) DC CHARACTERISTIC (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.8V, VREG2=2.15V, VREG1=5.0V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) PARAMETER SYMBOL VDD Supply Voltage VDDO Output Driver High side Resistance Output Driver Low side Resistance Power Supply Current At Operating (Mute signal input) RH RL IDD IDDO VIH Digital Input Voltage VIL Input Leakage Current ILK MCK, DIN1, DIN2 MCK, DIN1, DIN2 0 0.3VDD 1 V A OUT1, 2=VDDO-0.1V OUT1, 2=0.1V No-load operating DIN1, DIN2=16fS MCK=256fS MCK, DIN1, DIN2 1.6 0.7VDD 1.8 1.5 1.5 0.05 0.25 3.5 2 2 0.10 0.5 VDD V V CONDITIONS MIN 1.7 TYP 2.0 MAX 3.0 UNIT V MA -4- Ver.2005-03-09 NJU8716A/B NJU3555 (2) REGULATOR CHARACTERRITICS (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.8V, VREG2=2.15V, VREG1=5.0V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) PARAMETER Power Supply SYMBOL VREG1 VREG2 Power Supply Current At Operating Off-Leakage Current Input Voltage Input Leakage Current Output Voltage Output Current Output Sink Current VREG2-VREGO Dropout Voltage Ripple Rejection Load Regulation Voltage VREGO Low Voltage Detection Sleep Detection Voltage IREG2 IREG1 IREG1OFF VCONT ILK VREGO1 VREGO2 IOUT ISINK VIO RR VLR VDET1 VDET2 VDET3 Ta=-20 ~+70C Vr=0.1Vrms,Iout=70mA fr=1kHz VOUT1=VOUT2=-6dBm fOUT1=fOUT2=1kHz VCONT VREG2=2.5V, VCONT=1.0V VREG2=2.5V, VCONT=0V VDD=0.5V or lower No-load DIN1=L DIN2=L MCK=L CONDITIONS MIN 4.0 1.9 0 1.9 70 60 36 1.1 1.0 0.5 TYP 0.4 0.1 2.0 44 690 1.25 1.25 0.75 MAX 5.75 4.0 0.8 mA 0.2 1 VREG2 1 2.1 0.1 0.2 1228 1.4 1.5 1.0 A V A V V mA mA V dB Vrms UNIT V V V V V Note.5) VLR (Load Regulation Voltage) is effective with our measurement PCB only. The following figure shows a representative example of VREGO versus VCONT at VREG2=2.5V. 3.0 2.5 VREGO (V) 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Note.6) Output voltage of VREGO is maximum VREG2. In VDDO1 and VDDO2 terminals supplied from VREGO, please set VREG2 and VCONT not to exceed their operating voltage. VCONT (V) Ver.2005-03-09 -5- NJU8716A/B (3) AC CHARACTERISTICS (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.8V, VREG2=2.15V, VREG1=5.0V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) PARAMETER MCK Frequency MCK Pulse Width (H) MCK Pulse Width (L) DIN1, DIN2 Setup Time DIN1, DIN2 Hold Time SYMBOL fMCKI tMCKH tMCKL tDS tDH CONDITION MIN 8 12 12 20 20 TYP MAX 25 UNIT MHz ns ns ns ns tMCKH MCK (A Version) tMCKL MCK (B Version) tMCKI tMCKL tMCKH DIN1, DIN2 tDS tDH -6- Ver.2005-03-09 NJU8716A/B NJU3555 APPLICATION CIRCUIT Master Clock 6 9 MCK DIN1 DIN2 100H 0.47F 220F 1k OUT1 11 Audio Signal 16 Headphone 8 Logic Power 10F 0.1F 7 100H 220F 0.47F 1k 220F [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. VDD VSS VCONT 5 VREGO Control Voltage NJU8716A/B OUT2 14 CFB VREGO VDDO1 VSSO VDDO2 2 1 4 Regulator Power 2 10F Regulator Power 1 1F 2.2F 16 VREG2 12 3 VREG1 VSSO 13 Note.7) De-coupling capacitors must be connected between each power supply pin and GND. The capacitor value should be adjusted on the application circuit and the temperature. It may malfunction if capacity value is small. Note.8) A large-capacitance for the de-coupling capacitors for headphone speaker is recommended to improve a low-frequency characteristics. In addition, a low-ESR(Equivalent series resistance) capacitor is recommened for high power efficiency. Note.9) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please test the circuit carafully to fit your application. Ver.2005-03-09 1F 15 1F 10 -7- |
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