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DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
PRELIMINARY
April 1999
DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
General Description
The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data streams. Control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent during blanking intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a total throughput of 5.38Gbps (672 Megabytes per second). Two other modes are also supported. 24-bit color data (single pixel) can be clocked into the transmitter at a maximum rate of 170MHz. In this mode, the transmitter provides single-to-dual pixel conversion, and the output LVDS clock rate is 85MHz maximum. The third mode provides inter-operability with FPD-Link devices. The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum pixel clock rate is increased to 112 (170) MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew of up to +/-1 LVDS data bit time. These three enhancements allow cables 5 to 10+ meters in length to be driven. This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the "Applications Information" section of this datasheet.
Features
n Complies with OpenLDI specification for digital display interfaces n 32.5 to 112/170MHz clock support n Supports SVGA through QXGA panel resolutions n Drives long, low cost cables n Up to 5.38Gbps bandwidth n Pre-emphasis reduces cable loading effects n DC balance data transmission provided by transmitter reduces ISI distortion n Deskews +/-1 LVDS data bit time of pair-to-pair skew at receiver inputs; intra-pair skew tolerance of 300ps n Dual pixel architecture supports interface to GUI and timing controller; optional single pixel transmitter inputs support single pixel GUI interface n Transmitter rejects cycle-to-cycle jitter n 5V tolerant on data and control input pins n Programmable transmitter data and control strobe select (rising or falling edge strobe) n Backward compatible configuration select with FPD-Link n Optional second LVDS clock for backward compatibility w/ FPD-Link n Support for two additional user-defined control signals n Compatible with TIA/EIA-LVDS Standard
Generalized Block Diagram
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TRI-STATE (R) is a registered trademark of National Semiconductor Corporation.
(c) 1999 National Semiconductor Corporation
DS100073
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Transmitter Block Diagram
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Receiver Block Diagram
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec.) -0.3V to +4V -0.3V to +5.5V -0.3V to (VCC + 0.3V) -0.3V to +3.6V -0.3V to +3.6V Continuous +150C -65C to +150C +260C
Maximum Package Power Dissipation Capacity @ 25C 100 TQFP Package: DS90C387 2.8W DS90CF388 2.8W Package Derating: DS90C387 18.2mW/C above +25C DS90CF388 18.2mW/C above +25C ESD Rating: DS90C387 > 6 kV (HBM, 1.5k, 100pF) > 300 V (EIAJ, 0, 200pF) DS90CF388 > 2 kV (HBM, 1.5k, 100pF) > 250 V (EIAJ, 0, 200pF)
Recommended Operating Conditions
Min Nom Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) 3.0 -10 0 3.3 +25 Max 3.6 +70 2.4 Units V C V
100 mVp-p
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VIH VIL VOH VOL VCL IIN IOS VOD VOD VOS VOS IOS IOZ VTH VTL IIN Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Clamp Voltage Input Current Output Short Circuit Current Differential Output Voltage Change in VOD between Complimentary Output States Offset Voltage Change in VOS between Complimentary Output States Output Short Circuit Current Output TRI-STATE (R) Current Differential Input High Threshold Differential Input Low Threshold Input Current VIN = +2.4V, VCC = 3.6V VIN = 0V, VCC = 3.6V VOUT = 0V, RL = 100 PD = 0V, VOUT = 0V or VCC VCM = +1.2V -100 -3.5 1.125 1.25 IOH = -0.4 mA IOH = -2 mA IOL = 2 mA ICL = -18 mA VIN = 0.4V, 2.5V or VCC VIN = GND VOUT = 0V RL = 100 250 345 LVDS DRIVER DC SPECIFICATIONS 450 35 1.375 35 -10 mV mV V mV mA A mV mV -15 Conditions Min 2.0 GND 2.7 2.7 2.9 2.85 0.1 -0.79 +1.8 0 -120 0.3 -1.5 +15 Typ Max VCC 0.8 Units V V V V V V A A mA CMOS/TTL DC SPECIFICATIONS (Tx inputs, Rx outputs, control inputs and outputs)
1
10
+100
LVDS RECEIVER DC SPECIFICATIONS
10 10
A A
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Electrical Characteristics
Symbol ICCTW Parameter Transmitter Supply Current Worst Case
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified. Conditions RL = 100, CL = 5 pF, Worst Case Pattern (Figures 1, 3), DUAL=High (48-bit RGB), BAL=High (enabled) RL = 100, CL = 5 pF, 16 Grayscale Pattern (Figures 2, 3), DUAL=High (48-bit RGB), BAL=High (enabled) PD = Low Driver Outputs in TRI-STATE under Powerdown Mode CL = 8 pF, Worst Case Pattern (Figures 1, 4), DUAL (48-bit RGB), BAL=High (enabled) CL = 8 pF, 16 Grayscale Pattern (Figures 2, 4), DUAL (48-bit RGB), BAL=High (enabled) f = 32.5 MHz f = 65 MHz f = 85 MHz f = 112 MHz f = 32.5 MHz f = 65 MHz f = 85 MHz f = 112 MHz 115 200 240 250 60 95 115 150 255 150 250 275 300 95 125 150 270 300 mA mA mA mA mA mA mA mA A f = 32.5 MHz f = 65 MHz f = 85 MHz f = 112 MHz f = 32.5 MHz f = 65 MHz f = 85 MHz f = 112 MHz Min Typ 91.4 106 135 155 62.6 84.4 89.0 94.5 4.8 Max 140 160 170 190 120 130 145 155 50 Units mA mA mA mA mA mA mA mA A TRANSMITTER SUPPLY CURRENT
ICCTG
Transmitter Supply Current 16 Grayscale
ICCTZ
Transmitter Supply Current Power Down
RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current Worst Case
ICCRG
Receiver Support Current 16 Grayscale
ICCRZ
Receiver Supply Current Power Down
PD = Low Receiver Outputs stay low during Powerdown mode.
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and T A = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and VOD).
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Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Symbol TCIT TCIP TCIH TCIL TXIT Parameter TxCLK IN Transition Time (Figure 5) TxCLK IN Period (Figure 6) TxCLK in High Time (Figure 6) TxCLK in Low Time (Figure 6) TxIN Transition Time DUAL=Gnd or Vcc DUAL=1/2Vcc DUAL=Gnd or Vcc DUAL=1/2Vcc Min 1.0 1.0 8.928 5.88 0.35T 0.35T 1.5 0.5T 0.5T Typ 2.0 1.5 T Max 3.0 1.7 30.77 15.38 0.65T 0.65T 6.0 Units ns ns ns ns ns ns ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Symbol LLHT Parameter LVDS Low-to-High Transition Time (Figure 3), PRE = 0.75V (disabled) LVDS Low-to-High Transition Time (Figure 3), PRE = Vcc (max) LHLT LVDS High-to-Low Transition Time (Figure 3), PRE = 0.75V (disabled) LVDS High-to-Low Transition Time (Figure 3), PRE = Vcc (max) TBIT TCCS TSTC THTC TJCC Transmitter Output Bit Width TxOUT Channel to Channel Skew TxIN Setup to TxCLK IN (Figure 6) TxIN Hold to TxCLK IN (Figure 6) Transmitter Jitter Cycle-to-cycle (Figures 13, 14) (Note 5), DUAL=Vcc f = 112 MHz f = 85 MHz f = 65 MHz f = 56 MHz f = 32.5 MHz TPLLS TPDD Transmitter Phase Lock Loop Set (Figure 8) Transmitter Powerdown Delay (Figure 10) 2.7 0 85 60 70 100 75 100 75 80 120 110 10 100 DUAL=Gnd or Vcc DUAL=1/2Vcc Min Typ 0.14 0.11 0.16 0.05 1/7 TCIP 2/7 TCIP 100 Max 0.7 0.6 0.8 0.7 Units ns ns ns ns ns ns ps ns ns ps ps ps ps ps ms ns
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Symbol CLHT CHLT RCOP RCOH RCOL RSRC RHRC RPLLS RPDD RSKM Parameter CMOS/TTL Low-to-High Transition Time (Figure 4), Rx data out CMOS/TTL Low-to-High Transition Time (Figure 4), Rx clock out CMOS/TTL High-to-Low Transition Time (Figure 4), Rx data out CMOS/TTL High-to-Low Transition Time (Figure 4), Rx clock out RxCLK OUT Period (Figure 7) RxCLK OUT High Time (Figure 7)(Note 4) RxCLK OUT Low Time (Figure 7)(Note 4) RxOUT Setup to RxCLK OUT (Figure 7)(Note 4) RxOUT Hold to RxCLK OUT (Figure 7)(Note 4) Receiver Phase Lock Loop Set (Figure 9) Receiver Powerdown Delay (Figure 11) Receiver Skew Margin without Deskew (Figure 12) (Notes 4, 6) Receiver Skew Margin with Deskew (Note 7) Receiver Skew Margin without Deskew (Figure 12) (Notes 4, 6) Receiver Skew Margin with Deskew (Note 7) f = 85 MHz f = 112 MHz 170 1.27 160 1.68 f = 112 MHz f = 85 MHz f = 112 MHz f = 85 MHz f = 112 MHz f = 85 MHz f = 112 MHz f = 85 MHz 8.928 3.5 4.5 3.5 4.5 2.4 3.0 3.4 4.75 10 1 Min Typ 1.52 0.5 1.7 0.5 T Max 2.0 1.0 2.0 1.0 30.77 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ms s ps ns ps ns
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested at 112MHz to verify functional performance. Note 5: The limits are based on bench characterization of the device's jitter response over the power the power supply voltage range. Output clock jitter is measured with a cycle-to-cycle jitter of 3ns applied to the input clock signal while data inputs are switching (see figures 15 and 16). A jitter event of 3ns, represents worse case jump in the clock edge from most graphics VGA chips currently available. This parameter is used when calculating system margin as described in AN-1059. Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable) and clock jitter. RSKM cable skew (type, length) + source clock jitter (cycle to cycle). Note 7: This limit is based on the capability of deskew circuitry. This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/ length of cable) and clock jitter. RSKM with deskew is 1 LVDS bit time (1/7th clock period) data to clock skew.
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AC Timing Diagrams
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FIGURE 1. "Worst Case" Test Pattern
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FIGURE 2. "16 Grayscale" Test Pattern (Notes 8, 9, 10)
Note 8: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 9: The 16 grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 10: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
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AC Timing Diagrams
(Continued)
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FIGURE 3. DS90C387 (Transmitter) LVDS Output Load and Transition Times
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FIGURE 4. DS90CF388 (Receiver) CMOS/TTL Output Load and Transition Times
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FIGURE 5. DS90C387 (Transmitter) Input Clock Transition Time
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FIGURE 6. DS90C387 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
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FIGURE 7. DS90CF388 (Receiver) Setup/Hold and High/Low Times
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AC Timing Diagrams
(Continued)
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FIGURE 8. DS90C387 (Transmitter) Phase Lock Loop Set Time
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FIGURE 9. DS90CF388 (Receiver) Phase Lock Loop Set Time
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AC Timing Diagrams
(Continued)
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FIGURE 10. Transmitter Power Down Delay
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FIGURE 11. Receiver Power Down Delay
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C -- Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos -- Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 11) + ISI (Inter-symbol interference) (Note 12) Cable Skew -- typically 10 ps-40 ps per foot, media dependent Note 11: Cycle-to-cycle jitter is less than 100 ps at 112 MHz Note 12: ISI is dependent on interconnect length; may be zero
FIGURE 12. Receiver Skew Margin
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AC Timing Diagrams
(Continued)
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FIGURE 13. TJCC Test Setup - DS90C387
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FIGURE 14. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter
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DS90C387 Pin Description -- FPD Link Transmitter
Pin Name Rn, Gn, Bn, DE, HSYNC, VSYNC AnP AnM CLKIN R_FB R_FDE CLK1P CLK1M PD PLLSEL BAL PRE I/O I No. 51 Description TTL level input. This includes: 16 Red, 16 Green, 16 Blue, and 3 control lines HSYNC, VSYNC, DE (Data Enable).(Note 13) Positive LVDS differential data output. Negative LVDS differential data output. TTL level clock input. Programmable data strobe select. Rising data strobe edge selected when input is high. (Note 13) Programmable control (DE) strobe select. Data active when DE = High when input is high. (Note 13) Positive LVDS differential clock output. Negative LVDS differential clock output. TTL level input. Assertion (low input) tri-states the outputs, ensuring low current at power down. (Note 13) PLL range select. This pin must be tied to Vcc. No connect or tied to Gnd is reserved for future use.(Note 13) Mode select for dc balanced (new) or non-dc balanced (backward compatible) interface. DC balance is active when input is high. (Note 13) Pre-emphasis level select. Pre-emphasis is active when input is tied to VCC through external pull-up resistor. Resistor value determines pre-emphasis level (see table in application section). For normal LVDS drive level (No pre-emphasis) leave this pin open (do not tie to ground).(Note 13) Three-mode select for dual pixel, single pixel, or single pixel input to dual pixel output operation. Single pixel mode when input is low (only LVDS channels A0 thru A3 and CLK1 are active) for power savings. Dual mode is active when input is high. Single in - dual out when input is at 1/2 Vcc. (Note 13)Figure 15 Power supply pins for TTL inputs and digital circuitry. Ground pins for TTL inputs and digital circuitry. Power supply pin for PLL circuitry. Ground pins for PLL circuitry. Power supply pin for LVDS outputs. Ground pins for LVDS outputs. Additional positive LVDS differential clock output. Identical to CLK1P. No connect if not used. Additional negative LVDS differential clock output. Identical to CLK1M. No connect if not used.
O O I I I O O I I I I
8 8 1 1 1 1 1 1 1 1 1
DUAL
I
1
VCC GND PLLVCC PLLGND LVDSVCC LVDSGND CLK2P/NC CLK2M/NC
I I I I I I O O
4 5 2 3 2 4 1 1
Note 13: Inputs default to "low" when left open due to internal pull-down resistor.
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DS90CF388 Pin Description -- FPD Link Receiver
Pin Name AnP AnM Rn, Gn, Bn, DE, HSYNC, VSYNC RxCLK INP RxCLK INM RxCLK OUT R_FDE PLLSEL BAL DESKEW I/O I I O No. 8 8 51 Description Positive LVDS differential data inputs. Negative LVDS differential data inputs. TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3 control lines -- HSYNC (LP), VSYNC (FLM), DE (Data Enable). Positive LVDS differential clock input. Negative LVDS differential clock input. TTL level clock output. The falling edge acts as data strobe. Programmable control (DE) strobe select. Tied high for data active when DE is high. (Note 13) PLL range select. This pin must be tied to Vcc. No connect or tied to Gnd is reserved for future use. (Note 13) Mode select for dc balanced (new) or non-dc balanced (backward compatible) interface. DC balance is active when input is high. (Note 13) Deskew and oversampling "on/off" select. Deskew is active when input is high. Only supported in DC balance mode (BAL=High). To complete the deskew operation, a minimum of four clock cycles is required during blanking time. (Note 13) TTL level input. When asserted (low input) the receiver data outputs are low and clock output is high. (Note 13) Indicates receiver clock input signal is not present with a logic high. With a clock input present, a low logic is indicated. Power supply pins for TTL outputs and digital circuitry. Ground pins for TTL outputs and digital circuitry Power supply for PLL circuitry. Ground pin for PLL circuitry. Power supply pin for LVDS inputs. Ground pins for LVDS inputs. TTL level data outputs. User-defined control signals - no connect when not used.
I I O I I I I
1 1 1 1 1 1 1
PD STOPCLK VCC GND PLLVCC PLLGND LVDSVCC LVDSGND CNTLE, CNTLF
I O I I I I I I O
1 1 6 8 1 2 2 3 2
Note 14: These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under test conditions receiver inputs will be in a HIGH state. If the clock input signal is present, outputs will be HIGH; if the clock input is also floating/terminated, outputs will remain in the last valid state.
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FIGURE 15. Resistor Network for "DUAL" pin input - recommend using R1 = R2 = 10k for single to dual mode
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LVDS Interface
TABLE 1. LVDS data bit naming convention X X=R X=G X=B Y=1 Y=2 Z=0-7 Y Z Description Red Green Blue Even Pixel Odd Pixel LVDS bit number (not VGA controller LSB to MSB)
Note 15: For a 48-bit dual pixel application - LSB (Less Significant Bit) = R16,G16,B16,R26,G26,B26 and MSB (Most Significant Bit) = R15,G15,B15,R25,G25,B25. Note 16: For a 36-bit dual pixel application - LSB (Less Significant Bit) = R10,G10,B10,R20,G20,B20 and MSB (Most Significant Bit) = R15,G15,B15,R25,G25,B25.
TABLE 2. Single pixel per clock input application data mapping (DUAL = Gnd) VGA - TFT Data Signals Color Bits 24-bit LSB R0 R1 R2 R3 R4 R5 R6 MSB LSB R7 G0 G1 G2 G3 G4 G5 G6 MSB LSB G7 B0 B1 B2 B3 B4 B5 B6 MSB B7 B0 B1 B2 B3 B4 B5 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4 R5 18-bit Transmitter input pin names DS90C387 R16 R17 R10 R11 R12 R13 R14 R15 G16 G17 G10 G11 G12 G13 G14 G15 B16 B17 B10 B11 B12 B13 B14 B15 Receiver output pin names DS90CF388 R16 R17 R10 R11 R12 R13 R14 R15 G16 G17 G10 G11 G12 G13 G14 G15 B16 B17 B10 B11 B12 B13 B14 B15 B0 B1 B2 B3 B4 B5 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4 R5 TFT Panel Data Signals 18-bit 24-bit R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7
TABLE 3. Dual pixel per clock input application data mapping (DUAL = Vcc) VGA - TFT Data Signals Color Bits 48-bit LSB RE0 RE1 RE2 RE3 RE4 RE0 RE1 RE2 36-bit Transmitter input pin names DS90C387 R16 R17 R10 R11 R12 Receiver output pin names DS90CF388 R16 R17 R10 R11 R12 RE0 RE1 RE2 TFT Panel Data Signals 36-bit 48-bit RE0 RE1 RE2 RE3 RE4
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LVDS Interface
(Continued)
TABLE 3. Dual pixel per clock input application data mapping (DUAL = Vcc) (Continued) VGA - TFT Data Signals Color Bits RE5 RE6 MSB LSB RE7 GE0 GE1 GE2 GE3 GE4 GE5 GE6 MSB LSB GE7 BE0 BE1 BE2 BE3 BE4 BE5 BE6 MSB LSB BE7 RO0 RO1 RO2 RO3 RO4 RO5 RO6 MSB LSB RO7 GO0 GO1 GO2 GO3 GO4 GO5 GO6 MSB LSB GO7 BO0 BO1 BO2 BO3 BO4 BO5 BO6 MSB BO7 BO0 BO1 BO2 BO3 BO4 BO5 GO0 GO1 GO2 GO3 GO4 GO5 RO0 RO1 RO2 RO3 RO4 RO5 BE0 BE1 BE2 BE3 BE4 BE5 GE0 GE1 GE2 GE3 GE4 GE5 RE3 RE4 RE5 Transmitter input pin names R13 R14 R15 G16 G17 G10 G11 G12 G13 G14 G15 B16 B17 B10 B11 B12 B13 B14 B15 R26 R27 R20 R21 R22 R23 R24 R25 G26 G27 G20 G21 G22 G23 G24 G25 B26 B27 B20 B21 B22 B23 B24 B25 Receiver output pin names R13 R14 R15 G16 G17 G10 G11 G12 G13 G14 G15 B16 B17 B10 B11 B12 B13 B14 B15 R26 R27 R20 R21 R22 R23 R24 R25 G26 G27 G20 G21 G22 G23 G24 G25 B26 B27 B20 B21 B22 B23 B24 B25 BO0 BO1 BO2 BO3 BO4 BO5 GO0 GO1 GO2 GO3 GO4 GO5 RO0 RO1 RO2 RO3 RO4 RO5 BE0 BE1 BE2 BE3 BE4 BE5 GE0 GE1 GE2 GE3 GE4 GE5 TFT Panel Data Signals RE3 RE4 RE5 RE5 RE6 RE7 GE0 GE1 GE2 GE3 GE4 GE5 GE6 GE7 BE0 BE1 BE2 BE3 BE4 BE5 BE6 BE7 RO0 RO1 RO2 RO3 RO4 RO5 RO6 RO7 GO0 GO1 GO2 GO3 GO4 GO5 GO6 GO7 BO0 BO1 BO2 BO3 BO4 BO5 BO6 BO7
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LVDS Interface
(Continued)
TABLE 4. Single pixel per clock input-to-dual pixel per clock output data mapping (DUAL = 1/2Vcc) VGA - TFT Data Signals Color Bits 24-bit LSB R0 R1 R2 R3 R4 R5 R6 MSB LSB R7 G0 G1 G2 G3 G4 G5 G6 MSB LSB G7 B0 B1 B2 B3 B4 B5 B6 MSB B7 B0 B1 B2 B3 B4 B5 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4 R5 18-bit Transmitter input pin names DS90C387 R16 R17 R10 R11 R12 R13 R14 R15 G16 G17 G10 G11 G12 G13 G14 G15 B16 B17 B10 B11 B12 B13 B14 B15 R16 R17 R10 R11 R12 R13 R14 R15 G16 G17 G10 G11 G12 G13 G14 G15 B16 B17 B10 B11 B12 B13 Receiver output pin names DS90CF388 R16 R17 R10 R11 R12 R13 R14 R15 G16 G17 G10 G11 G12 G13 G14 G15 B16 B17 B10 B11 B12 B13 B14 B15 R26 R27 R20 R21 R22 R23 R24 R25 G26 G27 G20 G21 G22 G23 G24 G25 B26 B27 B20 B21 B22 B23 BO0 BO1 BO2 BO3 GO0 GO1 GO2 GO3 GO4 GO5 RO0 RO1 RO2 RO3 RO4 RO5 BE0 BE1 BE2 BE3 BE4 BE5 GE0 GE1 GE2 GE3 GE4 GE5 RE0 RE1 RE2 RE3 RE4 RE5 TFT Panel Data Signals 36-bit 48-bit RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 GE0 GE1 GE2 GE3 GE4 GE5 GE6 GE7 BE0 BE1 BE2 BE3 BE4 BE5 BE6 BE7 RO0 RO1 RO2 RO3 RO4 RO5 RO6 RO7 GO0 GO1 GO2 GO3 GO4 GO5 GO6 GO7 BO0 BO1 BO2 BO3 BO4 BO5
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LVDS Interface
(Continued)
TABLE 4. Single pixel per clock input-to-dual pixel per clock output data mapping (DUAL = 1/2Vcc) (Continued) VGA - TFT Data Signals Color Bits Transmitter input pin names B14 B15 Receiver output pin names B24 B25 TFT Panel Data Signals BO4 BO5 BO6 BO7
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FIGURE 16. TTL Data Inputs Mapped to LVDS Outputs Non-DC Balanced Mode (Backward Compatible, BAL = Low)
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LVDS Interface
(Continued)
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FIGURE 17. 48 Parallel TTL Data Inputs Mapped to LVDS Outputs DC Balanced Mode - Data Enabled, BAL = High
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LVDS Interface
(Continued)
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FIGURE 18. Control Signals Transmitted During Blanking Control Signals Transmitted During Blanking
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Note 17: The control signal during blanking shown above is for R_FDE = High, when R_FDE = Low all the low/high patterns are reversed.
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Applications Information
How to configure the DS90C387 and DS90CF388 for most common application: 1. To configure for single input pixel-to-dual pixel output application, the DS90C387 "DUAL" pin must be set to 1/2 Vcc = 1.65V. This may be implemented using pull-up and pull-down resistors of 10k each as shown in Figure 15. This configuration will allow the user to interface to an LDI receiver (DS90CF388) or if in the non-DC Balanced mode (BAL = low) then two FPD-Link 'notebook' receivers (DS90CF384A). The DC balance feature is recommended for monitor applications which require >2meters of cable length. Notebook applications should disable this feature to reduce the current consumption of the chipset. Note that only the DS90C387/DS90CF388 support the DC balance data transmission feature. 2. To configure for single pixel or dual pixel application using the DS90C387/DS90CF388, the "DUAL" pin must be set to Vcc (dual) or Gnd (single). In dual mode, the transmitter-DS90C387 has two LVDS clock outputs enabling an interface to two FPD-Link 'notebook' receivers (DS90CF384A). In single mode, outputs A4-to-A7 and CLK2 are disabled which reduces power dissipation. Both single and dual mode also support the DC balance data transmission feature, which should only be used for monitor application. The DS90CF388 is able to support single or dual pixel interface up to 112MHz operating frequency. This receiver may also be used to interface to a VGA controller with an integrated LVDS transmitter without DC balance data transmission. In this case, the receivers "BAL" pin must be tied low (DC balance disabled). New features Description: 1. Pre-emphasis: adds extra current during LVDS logic transition to reduce the cable loading effects. Pre-emphasis strength is set via a DC voltage level applied from min to max (0.75V to Vcc) at the "PRE" pin. A higher input voltage on the "PRE" pin increases the magnitude of dynamic current during data transition. The "PRE" pin requires one pull-up resistor (Rpre) to Vcc in order to set the DC level. There is an internal resistor network, which cause a voltage drop. Please refer to the tables below to set the voltage level.
TABLE 5. Pre-emphasis DC voltage level with (Rpre) Rpre 1M or NC 50k 9k 3k 1k 100 Resulting PRE Voltage 0.75V 1.0V 1.5V 2.0V 2.6V Vcc 100% pre-emphasis 50% pre-emphasis Effects Standard LVDS
TABLE 6. Pre-emphasis needed per cable length Frequency 112MHz 112MHz 80MHz 80MHz 65MHz 56MHz PRE Voltage 1.0V 1.5V 1.0V 1.2V 1.5V 1.0V Typical cable length 2 meters 5 meters 2 meters 7 meters 10 meters 10 meters
Note 18: This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable, length and operating frequency.
2. DC Balance: In the balanced operating modes, in addition to pixel and control information an additional bit is transmitted on every LVDS data signal line during each cycle of active data as shown in Figure 17. This bit is the DC balance bit (DCBAL). The purpose of the DC Balance bit is to minimize the short- and long-term DC bias on the signal lines. This is achieved by selectively sending the pixel data either unmodified or inverted. The value of the DC balance bit is calculated from the running word disparity and the data disparity of the current word to be sent. The data disparity of the current word shall be calculated by subtracting the number of bits of value 0 from the number of bits value 1 in the current word. Initially, the running word disparity may be any value between +7 and -6. The running word disparity shall be calculated as a continuous sum of all the modified data disparity values, where the unmodified data disparity value is the calculated data disparity minus 1 if the data is sent unmodified and 1 plus the inwww.national.com 20
verse of the calculated data disparity if the data is sent inverted. The value of the running word disparity shall saturate at +7 and -6. The value of the DC balance bit (DCBAL) shall be 0 when the data is sent unmodified and 1 when the data is sent inverted. To determine whether to send pixel data unmodified or inverted, the running word disparity and the current data disparity are used. If the running word disparity is positive and the current data disparity is positive, the pixel data shall be sent inverted. If the running word disparity is positive and the current data disparity is zero or negative, the pixel data shall be sent unmodified. If the running word disparity is negative and the current data disparity is positive, the pixel data shall be sent unmodified. If the running word disparity is negative and the current data disparity is zero or negative, the pixel data shall be sent inverted. If the running word disparity is zero, the pixel data shall be sent inverted.
Applications Information
(Continued)
Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. These enhancements allow cables 5 to 10+ meters in length to be driven. The data enable control signal (DE) is used in the DC balanced mode to distinguish between pixel data and control information being sent. It must be continuously available to the device in order to correctly separate pixel data from control information. For this reason, DE shall be sent on the clock signals, LVDS CLK1 and CLK2, when operating in the DC balanced mode. If the value of the control to be sent is 1 (active display), the value of the control word sent on the clock signals shall be 1111000 or 1110000. If the value of the control to be sent is 0 (blanking time), the value of the control word sent on the clock signals shall be 1111100 or 1100000. The control information, such as HSYNC and VSYNC, is always sent unmodified. The value of the control word to send is determined by the running word disparity and the value of the control to be sent. If the running word disparity is positive and the value of the control to be sent is 0, the control word sent shall be 1110000. If the running word disparity is zero or negative and the control word to be sent is 0, the control word sent shall be 1111000. If the running word disparity is positive and the value of the control to be sent is 1, the control word sent shall be 1100000. If the running word disparity is zero or negative and the value of the control to be sent is 1, the control word sent shall be 1111100. The DC Balance bit shall be sent as 0 when sending control information during blanking time. See Figure 18. In backward compatible mode (BAL = low) control and data is sent as regular LVDS data. See Figure 16. Support of CNTLE, CNTLF: The 387/388 will also support the transmission of two additional user-defined control signals in 'dual pixel' output mode which are active during blanking while VSYNC is low. The additional control signals, referred to as CNTLE and CNTLF, should be multiplexed with data signals and provided to the transmitter inputs. Inputs B26 - CNTLF and B27 - CNTLE are designated for this purpose. When operating in 'nonbalanced' mode, controls (CNTLE, CNTLF) are transmitted on LVDS channel A6 during the blanking interval when
VSYNC is low. When operating in 'DC balanced' mode, controls (CNTLE, CNTLF) are transmitted on LVDS channels A4 and A5 during the blanking interval when VSYNC is low. Refer to Table (Control Signals Transmitted During Blanking) for details. These signals may be active only during blanking while VSYNC is low. Control signal levels are latched and held in the last valid state when VSYNC transitions from low to high. These control signals are available as TTL outputs of the receiver. 3. Deskew: The OpenLDI receiver (DS90CF388) is able to tolerate a minimum of 300ps skew between the signals arriving on a single differential pair (intra-pair) and a minimum of 1 LVDS data bit time skew between signals arriving on dependent differential pair (pair-to-pair). This is supported in the DC balance data transmission mode only. To complete the deskew operation, a minimum of four clock cycles is required during blanking time. This allows the chipset to support reduced blanking applications. Backwards Compatible Mode with FPD-Link The transmitter provides a second LVDS output clock. Both LVDS clocks will be identical in 'Dual pixel mode'. This feature supports backward compatibility with the previous generation of devices - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit 'notebook' receivers. Pre-emphasis feature is available for use in both the DC balanced and non-DC balanced (backwards compatible) modes. Transmitter Features: The transmitter is designed to reject cycle-to-cycle jitter which may be seen at the transmitter input clock. Very low cycle-to-cycle jitter is passed on to the transmitter outputs. This significantly reduces the impact of jitter provided by the input clock source, and improves the accuracy of data sampling. Data sampling is further enhanced by automatically calibrated data sampling strobes at the receiver inputs. Timing and control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent during blanking intervals to guarantee correct reception of these critical signals. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for rising edge strobe or falling edge strobe through a dedicated pin. A rising edge transmitter will inter-operate with a falling edge receiver without any translation logic.
CONFIGURATION TABLE
TABLE 7. Transmitter / Receiver configuration table Pin R_FB (Tx only) R_FDE (both Tx and Rx) BAL (both Tx and Rx) DUAL (Tx only) Condition R_FB = VCC R_FB = GND R_FDE = VCC R_FDE = GND BAL=VCC BAL=Gnd DUAL=VCC DUAL=1/2VCC DUAL=Gnd Rising Edge Data Strobe Falling Edge Data Strobe Active data DE = High Active data DE = Low DC Balanced enabled DC Balanced disabled (backward compatible to FPD-Link) 48-bit color (dual pixel) support Single-to-dual support 24-bit color (single pixel) support Configuration
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Pin Diagram
Transmitter-DS90C387
DS100073-6
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Pin Diagram
Receiver-DS90CF388
DS100073-7
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DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
Physical Dimensions
inches (millimeters) unless otherwise noted
Order Number DS90C387VJD and DS90CF388VJD NS Package Number VJD100A
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