View NSC04701_993702.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS90CR217/DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-75 MHz
February 1999
DS90CR217/DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz
General Description
The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR218 receiver converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75 MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75 MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec). This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
Features
n 20 to 75 MHz shift clock support n 50% duty cycle on receiver output clock n Best-in-Class Set & Hold Times on TxINPUTs and RxOUTPUTs n Low power consumption n Tx + Rx Power-down mode <400W (max) n 1V common mode range (around +1.2V) n Narrow bus reduces cable size and cost n Up to 1.575 Gbps throughput n Up to 197 Megabytes/sec bandwidth n 345 mV (typ) swing LVDS devices for low EMI n PLL requires no external components n Rising edge data strobe n Compatible with TIA/EIA-644 LVDS standard n Low profile 48-lead TSSOP package
Block Diagrams
DS90CR217 DS90CR218
DS100871-1
DS100871-27
Order Number DS90CR217MTD See NS Package Number MTD48
Order Number DS90CR218MTD See NS Package Number MTD48
TRI-STATE (R) is a registered trademark of National Semiconductor Corporation.
(c) 1999 National Semiconductor Corporation
DS100871
www.national.com
Pin Diagrams
DS100871-21
DS100871-22
DS90CR217
DS90CR218
Typical Application
DS100871-23
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) -0.3V to +4V CMOS/TTL Input Voltage -0.5V to (VCC + 0.3V) CMOS/TTL Output Voltage -0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage -0.3V to (VCC + 0.3V) LVDS Driver Output Voltage -0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150C Storage Temperature Range -65C to +150C Lead Temperature (Soldering, 4 sec.) +260C Maximum Package Power Dissipation @ +25C MTD48 (TSSOP) Package: DS90CR217 1.98 W
DS90CR218 Package Derating DS90CR217 DS90CR218 ESD Rating (HBM, 1.5k, 100pF) (EIAJ, 0, 200pF) Latch Up Tolerance @ 25C
1.89 W 16 mW/C above +25C 15 mW/C above +25C
> 7kV > 700V > 300mA
Recommended Operating Conditions
Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min 3.0 -10 0 Nom 3.3 +25 Max 3.6 +70 2.4 100 Units V C V mVPP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified Symbol VIH VIL VOH VOL VCL IIN IOS VOD VOD VOS VOS IOS IOZ Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Clamp Voltage Input Current Output Short Circuit Current Differential Output Voltage Change in V OD between Complimentary Output States Offset Voltage (Note 4) Change in V OSbetween Complimentary Output States Output Short Circuit Current Output TRI-STATE (R) Current V R V LVDS RECEIVER DC SPECIFICATIONS VTH VTL I IN Differential Input High Threshold Differential Input Low Threshold Input Current V V TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case (with Loads) RL = 100, CL = 5 pF, Worst Case Pattern (Figures 1, 2) f = 33 MHz f = 40 MHz f = 66 MHz f = 75 MHz 28 29 34 39 42 47 52 57 mA mA mA mA
IN IN OUT L
Conditions
Min 2.0 GND
Typ
Max VCC 0.8
Units V V V V V A A mA mV mV V mV mA A
CMOS/TTL DC SPECIFICATIONS
I I I
OH OL CL IN IN
= -0.4 mA = 2 mA = -18 mA = 0.4V, 2.5V or VCC = GND = 0V
2.7
3.3 0.06 -0.79 +1.8 0.3 -1.5 +10 -120 450 35
V V V R
-10
0 -60
OUT
LVDS DRIVER DC SPECIFICATIONS
L
= 100
250
290
1.125
1.25
1.375 35
= 0V,
-3.5
-5
= 100
PWR DWN = 0V,
OUT
1
10
= 0V or VCC +100 -100 mV mV A A
V
CM
= +1.2V
= +2.4V, VCC = 3.6V = 0V, VCC = 3.6V
10 10
3
www.national.com
Electrical Characteristics
Symbol ICCTZ Parameter Transmitter Supply Current Power Down
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified Conditions PWR DWN = Low Driver Outputs in TRI-STATE under Powerdown Mode CL = 8 pF, Worst Case Pattern (Figures 1, 3) f = 33 MHz f = 40 MHz f = 66 MHz f = 75 MHz Min Typ Max Units TRANSMITTER SUPPLY CURRENT 10 55 A
RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current Worst Case 49 53 78 90 15 60 65 95 105 55 mA mA mA mA A
ICCRZ
Receiver Supply Current Power Down
PWR DWN = Low Receiver Outputs Stay Low during Powerdown Mode
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and VOD). Note 4: VOS previously referred as VCM.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified Symbol LLHT LHLT TCIT TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TCIP TCIH TCIL TSTC THTC TCCD TPLLS TPDD Parameter LVDS Low-to-High Transition Time (Figure 2) LVDS High-to-Low Transition Time (Figure 2) TxCLK IN Transition Time (Figure 4) Transmitter Output Pulse Position for Bit0 (Figure 15) Transmitter Output Pulse Position for Bit1 Transmitter Output Pulse Position for Bit2 Transmitter Output Pulse Position for Bit3 Transmitter Output Pulse Position for Bit4 Transmitter Output Pulse Position for Bit5 Transmitter Output Pulse Position for Bit6 TxCLK IN Period (Figure 6) TxCLK IN High Time (Figure 6) TxCLK IN Low Time (Figure 6) TxIN Setup to TxCLK IN (Figure 6) TxIN Hold to TxCLK IN (Figure 6) TxCLK IN to TxCLK OUT Delay @ 25C,VCC=3.3V (Figure 8) Transmitter Phase Lock Loop Set (Figure 10) Transmitter Powerdown Delay (Figure 13) f = 75 MHz f = 75 MHz 1.0 -0.20 1.71 3.61 5.51 7.42 9.32 11.23 13.33 0.35T 0.35T 2.5 0 3.8 6.3 10 100 0 1.91 3.81 5.71 7.62 9.52 11.43 T 0.5T 0.5T Min Typ 0.75 0.75 Max 1.5 1.5 6.0 0.20 2.11 4.01 5.91 7.82 9.72 11.63 50 0.65T 0.65T Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
www.national.com
4
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified Symbol CLHT CHLT RSPos0 RSPos1 RSPos2 RSPos3 RSPos4 RSPos5 RSPos6 RSKM RCOP RCOH RCOL RSRC RHRC RCCD RPLLS RPDD Parameter CMOS/TTL Low-to-High Transition Time (Figure 3) CMOS/TTL High-to-Low Transition Time (Figure 3) Receiver Input Strobe Position for Bit 0 (Figure 16) Receiver Input Strobe Position for Bit 1 Receiver Input Strobe Position for Bit 2 Receiver Input Strobe Position for Bit 3 Receiver Input Strobe Position for Bit 4 Receiver Input Strobe Position for Bit 5 Receiver Input Strobe Position for Bit 6 RxIN Skew Margin (Note 5) (Figure 17) RxCLK OUT Period (Figure 7) RxCLK OUT High Time (Figure 7) RxCLK OUT Low Time (Figure 7) RxOUT Setup to RxCLK OUT (Figure 7) RxOUT Hold to RxCLK OUT (Figure 7) RxCLK IN to RxCLK OUT Delay @ 25C, VCC = 3.3V (Note 6)(Figure 9) Receiver Phase Lock Loop Set (Figure 11) Receiver Powerdown Delay (Figure 14) f = 75 MHz f = 75 MHz f = 75 MHz 0.58 2.49 4.39 6.30 8.20 10.11 12.01 380 13.33 3.6 3.6 3.5 3.5 3.4 5.0 7.3 10 1 T 5 5 50 6.0 6.0 Min Typ 2.0 1.8 0.95 2.86 4.76 6.67 8.57 10.48 12.38 Max 3.5 3.5 1.32 3.23 5.13 7.04 8.94 10.85 12.75 Units ns ns ns ns ns ns ns ns ns ps ns ns ns ns ns ns ms s
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and source clock jitter less than 250 ps. Note 6: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the 217/287 transmitter and 218/288 receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
AC Timing Diagrams
DS100871-2
FIGURE 1. "Worst Case" Test Pattern
DS100871-3 DS100871-4
FIGURE 2. DS90CR217 (Transmitter) LVDS Output Load and Transition Times
5
www.national.com
AC Timing Diagrams
(Continued)
DS100871-5 DS100871-6
FIGURE 3. DS90CR218 (Receiver) CMOS/TTL Output Load and Transition Times
DS100871-7
FIGURE 4. D590CR217 (Transmitter) Input Clock Transition Time
DS100871-8
Note 7: Measurements at VDIFF = 0V Note 8: TCCS measured between earliest and latest LVDS edges Note 9: TxCLK Differential LowHigh Edge
FIGURE 5. DS90CR217 (Transmitter) Channel-to-Channel Skew
DS100871-9
FIGURE 6. DS90CR217 (Transmitter) Setup/Hold and High/Low Times
www.national.com
6
AC Timing Diagrams
(Continued)
DS100871-10
FIGURE 7. DS90CR218 (Receiver) Setup/Hold and High/Low Times
DS100871-11
FIGURE 8. DS90CR217 (Transmitter) Clock In to Clock Out Delay
DS100871-12
FIGURE 9. DS90CR218 (Receiver) Clock In to Clock Out Delay
DS100871-13
FIGURE 10. DS90CR217 (Transmitter) Phase Lock Loop Set Time
7
www.national.com
AC Timing Diagrams
(Continued)
DS100871-14
FIGURE 11. DS9OCR218 (Receiver) Phase Lock Loop Set Time
DS100871-16
FIGURE 12. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR217)
DS100871-17
FIGURE 13. Transmitter Powerdown Delay
www.national.com
8
AC Timing Diagrams
(Continued)
DS100871-18
FIGURE 14. Receiver Powerdown Delay
DS100871-19
FIGURE 15. Transmitter LVDS Output Pulse Position Measurement
9
www.national.com
AC Timing Diagrams
(Continued)
DS100871-28
FIGURE 16. Receiver LVDS Input Strobe Position
www.national.com
10
AC Timing Diagrams
(Continued)
DS100871-20
C -- Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos -- Transmitter output pulse position (min and max) RSKM Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11) Cable Skew -- typicaIIy 10 ps-40 ps per foot, media dependent Note 10: Cycle-to-cycle jitter is less than 250 ps at 75MHz Note 11: ISI is dependent on interconnect length; may be zero
FIGURE 17. Receiver LVDS Input Skew Margin
Applications Information
The DS90CR217 and DS90CR218 are backward compatible with the existing 5V Channel Link transmitter/receiver pair (DS90CR213, DS90CR214). To upgrade from a 5V to a 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL V CC. 2. 3. Transmitter input and control inputs except 3.3V TTL/ CMOS levels. They are not 5V tolerant. The receiver powerdown feature when enabled wilI lock receiver output to a logic low. However, the 5V/66 MHz receiver maintain the outputs in the previous state when powerdown occurred.
DS90CR217 Pin Description -- Channel Link Transmitter
Pin Name TxIN TxOUT+ TxOUT- TxCLK IN TxCLK OUT+ TxCLK OUT- PWR DWN V CC GND PLL V CC PLL GND LVDS V CC LVDS GND I/O I O O I O O I I I I I I I No. 21 3 3 1 1 1 1 4 5 1 2 1 3 TTL level input. Positive LVDS differential data output. Negative LVDS differential data output. TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN. Positive LVDS differential clock output. Negative LVDS differential clock output. TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at power down. Power supply pins for TTL inputs. Ground pins for TTL inputs. Power supply pins for PLL. Ground pins for PLL. Power supply pin for LVDS outputs. Ground pins for LVDS outputs. Description
DS90CR218 Pin Description -- Channel Link Receiver
Pin Name RxIN+ RxIN- RxOUT RxCLK IN+ RxCLK IN- RxCLK OUT I/O I I O I I O No. 3 3 21 1 1 1 Description Positive LVDS differential data inputs. (Note 12) Negative LVDS differential data inputs. (Note 12) TTL level data outputs. Positive LVDS differential clock input. Negative LVDS differential clock input. TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
11 www.national.com
Applications Information
(Continued) (Continued)
DS90CR218 Pin Description -- Channel Link Receiver
Pin Name PWR DWN V CC GND PLL V CC PLL GND LVDS V CC LVDS GND I/O I I I I 1 I I No. 1 4 5 1 2 1 3 Power supply pins for TTL outputs. Ground pins for TTL outputs. Power supply for PLL. Ground pin for PLL. Power supply pin for LVDS inputs. Ground pins for LVDS inputs. Description
TTL level input. When asserted (low input) the receiver outputs are low.
Note 12: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the last valid state. A floating/terminated clock input will result in a LOW clock output.
The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending upon the application the interconnecting media may vary. For example, for lower data rate (clock rate) and shorter cable lengths (< 2m), the media electrical performance is less critical. For higher speed/long distance applications the media's performance becomes more critical. Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs). Twin-coax for example, has been demonstrated at distances as great as 5 meters and with the maximum data transfer of 1.58 Gbit/s. Additional applications information can be found in the following National Interface Application Notes: AN = #### AN-1041 AN-1035 AN-806 AN-905 AN-916 Topic Introduction to Channel Link PCB Design Guidelines for LVDS and Link Devices Transmission Line Theory Transmission Line Calculations and Differential Impedance Cable Information
CABLES: A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The 21bit CHANNEL LINK chipset (DS90CR217/218) requires four pairs of signal wires and the 28-bit CHANNEL LINK chipset (DS90CR287/288) requires five pairs of signal wires. The ideal cable/connector interface would have a constant 100 differential impedance throughout the path. It is also recommended that cable skew remain below 130ps ( 75 MHz clock rate) to maintain a sufficient data sampling window at the receiver. In addition to the four or five cable pairs that carry data and clock, it is recommended to provide at least one additional conductor (or pair) which connects ground between the transmitter and receiver. This low impedance ground provides a common mode return path for the two devices. Some of the more commonly used cable types for point-to-point applications include flat ribbon, flex, twisted pair and TwinCoax. All are available in a variety of configurations and options. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point applications while TwinCoax is good for short and long applications. When using ribbon cable, it is recommended to place a ground line between each differential pair to act as a barrier to noise coupling between adjacent pairs. For Twin-Coax cable applications, it is recommended to utilize a shield on each cable pair. All exwww.national.com 12
tended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless of the cable type. This overall shield results in improved transmission parameters such as faster attainable speeds, longer distances between transmitter and receiver and reduced problems associated with EMS or EMI. The high-speed transport of LVDS signals has been demonstrated on several types of cables with excellent results. However, the best overall performance has been seen when using Twin-Coax cable. Twin-Coax has very low cable skew and EMI due to its construction and double shielding. All of the design considerations discussed here and listed in the supplemental application notes provide the subsystem communications designer with many useful guidelines. It is recommended that the designer assess the tradeoffs of each application thoroughly to arrive at a reliable and economical cable solution. BOARD LAYOUT: To obtain the maximum benefit from the noise and EMI reductions of LVDS, attention should be paid to the layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise canceling of the differential signals. The board designer should also try to maintain equal length on signal traces for a given differential pair. As with any high speed design, the impedance discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on traces). Any discontinuities which do occur on one signal line should be mirrored in the other line of the differential pair. Care should be taken to ensure that the differential trace impedance match the differential impedance of the selected physical media (this impedance should also match the value of the termination resistor that is connected across the differential pair at the receiver's input). Finally, the location of the CHANNEL LINK TxOUT/ RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs. All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance and EMI. UNUSED INPUTS: All unused inputs at the TxIN inputs of the transmitter must be tied to ground. All unused outputs at the RxOUT outputs of the receiver must then be left floating. TERMINATION: Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL LINK chipset will normally require a single 100 resistor between the true and complement lines on each differential pair of the receiver input. The actual value of the termination resistor should be selected to match the differential mode
Applications Information
(Continued)
characteristic impedance (90 to 120 typical) of the cable. Figure 18 shows an example. No additional pull-up or pulldown resistors are necessary as with some other differential technologies such as PECL. Surface mount resistors are
recommended to avoid the additional inductance that accompanies leaded resistors. These resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively terminate the differential lines.
DS100871-24
FIGURE 18. LVDS Serialized Link Termination DECOUPLING CAPACITORS: Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface mount form factor) between each VCC and the ground plane(s) are recommended. The three capacitor values are 0.1 F, 0.01F and 0.001 F. An example is shown in Figure 19. The designer should employ wide traces for power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the number of bypass capacitors, the PLL VCC should receive the most filtering/bypassing. Next would be the LVDS VCC pins and finally the logic VCC pins. ferential pair), interconnect skew (t of one differential pair to another) and clock jitter will all reduce the available window for sampling the LVDS serial data streams. Care must be taken to ensure that the clock input to the transmitter be a clean low noise signal. Individual bypassing of each VCC to ground will minimize the noise passed on to the PLL, thus creating a low jitter LVDS clock. These measures provide more margin for channel-to-channel skew and interconnect skew as a part of the overall jitter/skew budget. COMMON MODE vs. DIFFERENTIAL MODE NOISE MARGIN: The typical signal swing for LVDS is 300 mV centered at +1.2V. The CHANNEL LINK receiver supports a 100 mV threshold therefore providing approximately 200 mV of differential noise margin. Common mode protection is of more importance to the system's operation due to the differential data transmission. LVDS supports an input voltage range of Ground to +2.4V. This allows for a 1.0V shifting of the center point due to ground potential differences and common mode noise. POWER SEQUENCING AND POWERDOWN MODE: Outputs of the CNANNEL LINK transmitter remain in TRI-STATE until the power supply reaches 2V. Clock and data outputs will begin to toggle 10 ms after VCC has reached 3V and the Powerdown pin is above 1.5V. Either device may be placed into a powerdown mode at any time by asserting the Powerdown pin (active low). Total power dissipation for each device will decrease to 5 W (typical). The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs (RxOUT) retain the states they were in when the clocks stopped. When the receiver board loses power, the receiver inputs are shorted to V CC through an internal diode. Current is limited (5 mA per input) by the fixed current mode drivers, thus avoiding the potential for latchup when powering the device.
DS100871-25
FIGURE 19. CHANNEL LINK Decoupling Configuration CLOCK JITTER: The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example, a 75 MHz clock has a period of 13.33 ns which results in a data bit width of 1.90 ns. Differential skew (t within one dif-
13
www.national.com
Applications Information
(Continued)
DS100871-26
FIGURE 20. Single-Ended and Differential Waveforms
www.national.com
14
15
DS90CR217/DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-75 MHz
Physical Dimensions
inches (millimeters) unless otherwise noted
Order Number DS90CR217MTD or DS90CR218MTD Dimentions in milimeters only NS Package Number MTD48
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

▲Up To Search▲

Price & Availability of NSC04701

	To Download NSC04701 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .