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MOTOROLA
Order Number: MC10EP016/D Rev. 0.1, 05/1999
Semiconductor Components
MC10EP016
8-BIT SYNCHRONOUS BINARY UP COUNTER
Product Preview
* * * * * * * * * * * * *
8-Bit Synchronous Binary Up Counter
1.3GHz Min Count Frequency PECL mode: 3.0V to 5.5V VCC with VEE = 0V ECL mode: 0V VCC with VEE = -3.0V to -5.5V 550ps CLK to Q, TC Internal TC Feedback (Gated) 8-Bit Fully Synchronous Counting and TC Generation Asynchronous Master Reset Q Output will default LOW with inputs open or at VEE 75k Pulldown Resistors ESD Protection: >4KV HBM, >200V MM Moisture Sensitivity Level 1, Indefinite Time Out of Drypack Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 * Transistor Count = TBD devices
FA SUFFIX LQFP PACKAGE CASE 873A
The MC10EP016 is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPSTM family. The counter features internal feedback to TC gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 1999
1
ECLinPS PlusTM
MC10EP016
PIN NAMES
PIN P0 - P7 Q0 - Q7 CE PE MR CLK TC TCLD FUNCTION Parallel Data (Preset) Inputs Data Outputs Count Enable Control Input Parallel Load Enable Control Input Master Reset Clock Terminal Count Output TC-Load Control Input
FUNCTION TABLES
CE X L L H X X PE L H H H X X TCLD MR X L H X X X L L L L L H CLK Z Z Z Z ZZ X FUNCTION Load Parallel (Pn to Qn) Continuous Count Count; Load Parallel on TC = LOW Hold Masters Respond, Slaves Hold Reset (Qn : = LOW, TC : = HIGH)
ZZ = Clock Pulse (High-to-Low) Z = Clock Pulse (Low-to-High)
FUNCTION TABLE
Function Load Count PE L H H H H L H H H H H H H H X CE X L L L L X H H L L L L L L X MR L L L L L L L L L L L L L L H TCLD X L L L L X X X H H H H H H X CLK Z Z Z Z Z Z Z Z Z Z Z Z Z Z X P7-P4 H X X X X H X X H H H H H H X P3 H X X X X H X X L L L L L L X P2 H X X X X H X X H H H H H H X P1 L X X X X L X X H H H H H H X P0 L X X X X L X X L L L L L L X Q7-Q4 H H H H L H H H H H H H H H L Q3 H H H H L H H H H H H L L H L Q2 H H H H L H H H H H H H H L L Q1 L L H H L L L L L H H H H L L Q0 L H L H L L L L H L H L H L L TC H H H L H H H H H H L H H H H
Load Hold
Load on Terminal Count
Reset
2
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MC10EP016 ECLinPS PlusTM
24 23 22 21 20 19 18 17
25 26 27 28 29 30 31 32 MC10EP016 (Pinout to be Determined)
16 15 14 13 12 11 10 9
1
2
3
4
5
6
7
8
MAXIMUM RATINGS*
Symbol VEE VCC VI VI Iout TA Tstg JA JC Tsol Parameter Power Supply (VCC = 0V) Power Supply (VEE = 0V) Input Voltage (VCC = 0V, VI not more negative than VEE) Input Voltage (VEE = 0V, VI not more positive than VCC) Output Current Operating Temperature Range Storage Temperature Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Solder Temperature (<2 to 3 Seconds: 245C desired) Still Air 500lfpm Continuous Surge Value -6.0 to 0 6.0 to 0 -6.0 to 0 6.0 to 0 50 100 -40 to +85 -65 to +150 130 TBD TBD 265 Unit VDC VDC VDC VDC mA C C C/W C/W C
* Maximum Ratings are those values beyond which damage to the device may occur.
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3
ECLinPS PlusTM
MC10EP016
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = -5.5V to -3.0V) (Note 3.)
-40C Symbol IEE VOH VOL VIH VIL IIH Characteristic Power Supply Current (Note 1.) Output HIGH Voltage (Note 2.) Output LOW Voltage (Note 2.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Input HIGH Current -1135 -1935 -1210 -1935 -1060 -1810 -885 -1685 -885 -1610 150 -1070 -1870 -1145 -1870 -945 -1745 -820 -1620 -820 -1545 150 -1010 -1810 -1085 -1810 -885 -1685 Min Typ Max Min 25C Typ Max Min 85C Typ Max 150 -760 -1560 -760 -1485 150 Unit mA mV mV mV mV A
IIL Input LOW Current 0.5 0.5 0.5 A NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 1. VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating. 2. All loading with 50 ohms to VCC-2.0 volts. 3. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, LVPECL (VCC = 3.3V 0.3V, VEE = 0V) (Note 6.)
-40C Symbol IEE VOH VOL VIH VIL IIH Characteristic Power Supply Current (Note 4.) Output HIGH Voltage (Note 5.) Output LOW Voltage (Note 5.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Input HIGH Current 2165 1365 2090 1365 2240 1490 2415 1615 2415 1690 150 2230 1430 2155 1430 2355 1555 2480 1680 2480 1755 150 2290 1490 2215 1490 2415 1615 Min Typ Max Min 25C Typ Max Min 85C Typ Max 150 2540 1740 2540 1815 150 Unit mA mV mV mV mV A
IIL Input LOW Current 0.5 0.5 0.5 A NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 4. VCC = 3.3V, VEE = 0V, all other pins floating. 5. All loading with 50 ohms to VCC-2.0 volts. 6. Input and output parameters vary 1:1 with VCC.
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MC10EP016 ECLinPS PlusTM
DC CHARACTERISTICS, PECL (VCC = 5.0V 0.5V, VEE = 0V) (Note 9.)
-40C Symbol IEE VOH VOL VIH VIL IIH Characteristic Power Supply Current (Note 7.) Output HIGH Voltage (Note 8.) Output LOW Voltage (Note 8.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Input HIGH Current 3865 3065 3790 3065 3940 3190 4115 3315 4115 3390 150 3930 3130 3855 3130 4055 3255 4180 3380 4180 3455 150 3990 3190 3915 3190 4115 3315 Min Typ Max Min 25C Typ Max Min 85C Typ Max 150 4240 3440 4240 3515 150 Unit mA mV mV mV mV A
IIL Input LOW Current 0.5 0.5 0.5 A NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 7. VCC = 5.0V, VEE = 0V, all other pins floating. 8. All loading with 50 ohms to VCC-2.0 volts. 9. Input and output parameters vary 1:1 with VCC.
AC CHARACTERISTICS (VEE = -3.6V to -3.0; VCC = GND)
-40C Symbol
fCOUNT tPLH tPHL
0C Max Min Typ
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
25C Max Min Typ
1.3 500 550 550 550 TBD TBD TBD TBD TBD TBD TBD TBD TBD 300
85C Max Min Typ
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Characteristic
Maximum Count Frequency (Note 10.) Propagation Delay CLK -> Q MR -> Q CLK -> TCb MR -> TCb Setup Time Pn CEb PEb TCLD Pn CEb PEb TCLD
Min
Typ
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Max
Unit
GHz ps
tS
ps
tH
Hold Time
ps
tRR tPW tr tf
Reset Recovery Time Minimum Pulse Width CLK, MR Output Rise/ Fall Times (20% - 80%)
ps ps ps
TBD
TBD
165
TBD
10. fmax specified to 1.3GHz with reduced output swing.
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5
ECLinPS PlusTM
MC10EP016
8-BIT BINARY COUNTER LOGIC DIAGRAM
Q0 Q1 Q7
PE
TCLD
Q0M MASTER BIT 0 PO P1 SLAVE CE BIT 1
CE
Q0M
Q0
CE Q Q1 0 Q2 Q3 Q4 Q5 Q6 P7
BIT 7
MR
CLK
BITS 2-6 5
TC
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
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MC10EP016 ECLinPS PlusTM
Applications Information
Cascading Multiple EP016 Devices
For applications which call for larger than 8-bit counters multiple EP016s can be tied together to achieve very wide bit width counters. The active low terminal count (TC) output and count enable input (CE) greatly facilitate the cascading of EP016 devices. Two EP016s can be cascaded without the need for external gating, however for counters wider than 16 bits external OR gates are necessary for cascade implementations. Figure 1 below pictorially illustrates the cascading of 4 EP016s to build a 32-bit high frequency counter. Note the EP01 gates used to OR the terminal count outputs of the lower order EP016s to control the counting operation of the higher order bits. When the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state) the more significant EP016 is set in its count mode and will count one binary digit upon the next positive clock transition. In addition, the preceding devices will also count one bit thus sending their terminal count outputs back to a high state disabling the count operation of the more significant counters and placing them back into hold modes. Therefore, for an EP016 in the chain to count, all of the lower order terminal count outputs must be in the low state. The bit width of the counter can be increased or decreased by simply adding or subtracting EP016 devices from Figure 1 and maintaining the logic pattern illustrated in the same figure. The maximum frequency of operation for the cascaded counter chain is set by the propagation delay of the TC output and the necessary setup time of the CE input and the propagation delay through the OR gate controlling it (for 16-bit counters the limitation is only the TC propagation delay and the CE setup time). Figure 1 shows EP01 gates used to control the count enable inputs, however, if the frequency of operation is lower a slower, LVECL OR gate can be used. Using the worst case guarantees for these parameters from the ECLinPS data book, the maximum count frequency for a greater than 16-bit counter is TBD and that for a 16-bit counter is TBD.
LOAD Q0 -> Q7 Q0 -> Q7 Q0 -> Q7 Q0 -> Q7
LO
CE EP016 LSB
PE
CE EP016
PE
CE EP016
PE
CE EP016 MSB
PE
CLK
TC
CLK
TC EP01
CLK
TC EP01
CLK
TC
P0 -> P7
P0 -> P7
P0 -> P7
P0 -> P7
CLOCK
Figure 1. 32-Bit Cascaded E016 Counter
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7
ECLinPS PlusTM
MC10EP016
Applications Information (continued)
Note that this assumes the trace delay between the TC outputs and the CE inputs are negligible. If this is not the case estimates of these delays need to be added to the calculations. where: P0 = LSB and P7 = MSB Forcing this input condition as per the setup in Figure 2 will result in the waveforms of Figure 3. Note that the TC output is used as the divide output and the pulse duration is equal to a Table 1. Preset Values for Various Divide Ratios
Divide Ratio 2 3 4 5 * * 112 113 114 * * 254 255 256 P7 H H H H * * H H H * * L L L P6 H H H H * * L L L * * L L L Preset Data Inputs P5 H H H H * * L L L * * L L L P4 H H H H * * H L L * * L L L P3 H H H H * * L H H * * L L L P2 H H H L * * L H H * * L L L P1 H L L H * * L H H * * H L L P0 L H L H * * L H L * * L H L
Programmable Divider
The EP016 has been designed with a control pin which makes it ideal for use as an 8-bit programmable divider. The TCLD pin (load on terminal count) when asserted reloads the data present at the parallel input pin (Pn's) upon reaching terminal count (an all 1s state on the outputs). Because this feedback is built internal to the chip, the programmable division operation will run at very nearly the same frequency as the maximum counting frequency of the device. Figure 2 below illustrates the input conditions necessary for utilizing the EP016 as a programmable divider set up to divide by 113.
H P7 H L H PE CE TCLD TC CLK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 L P6 L P5 L P4 H P3 H P2 H P1 H P0
Figure 2. Mod 2 to 256 Programmable Divider To determine what value to load into the device to accomplish the desired division, the designer simply subtracts the binary equivalent of the desired divide ratio from the binary value for 256. As an example for a divide ratio of 113: Pn's = 256 - 113 = 8F16 = 1000 1111
full clock period. For even divide ratios, twice the desired divide ratio can be loaded into the EP016 and the TC output can feed the clock input of a toggle flip flop to create a signal divided as desired with a 50% duty cycle. A single EP016 can be used to divide by any ratio from 2 to 256 inclusive. If divide ratios of greater than 256 are needed multiple EP016s can be cascaded in a manner similar to that already discussed. When EP016s are cascaded to build larger dividers the TCLD pin will no longer provide a means for loading on terminal count. Because one does not want to reload the counters until all of the devices in the chain have reached terminal count, external gating of the TC pins must be used for multiple EP016 divider chains.
Load Clock
1001 0000
1001 0001 *** ***
1111 1100
1111 1101
1111 1110
1111 1111
Load
PE *** TC DIVIDE BY 113
Figure 3. Divide by 113 EP016 Programmable Divider Waveforms
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MC10EP016 ECLinPS PlusTM
Applications Information (continued)
EP01
Q0 -> Q7 LO CE EP016 LSB PE
Q0 -> Q7 CE EP016 PE
Q0 -> Q7 CE EP016 PE
Q0 -> Q7 CE EP016 MSB PE
CLK
TC
CLK
TC EP01
CLK
TC EP01
CLK
TC
PO -> P7 CLOCK
PO -> P7
PO -> P7
PO -> P7
Figure 4. 32-Bit Cascaded EP016 Programmable Divider Figure 4 shows a typical block diagram of a 32-bit divider chain. Once again to maximize the frequency of operation EP01 OR gates were used. For lower frequency applications a slower OR gate could replace the EP01. Note that for a 16-bit divider the OR function feeding the PE (program enable) input CANNOT be replaced by a wire OR tie as the TC output of the least significant EP016 must also feed the CE input of the most significant EP016. If the two TC outputs were OR tied the cascaded count operation would not operate properly. Because in the cascaded form the PE feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device.
Maximizing EP016 Count Frequency
The EP016 device produces 9 fast transitioning single ended outputs, thus VCC noise can become significant in situations where all of the outputs switch simultaneously in the same direction. This VCC noise can negatively impact the maximum frequency of operation of the device. Since the device does not need to have the Q outputs terminated to count properly, it is recommended that if the outputs are not going to be used in the rest of the system they should be left unterminated. In addition, if only a subset of the Q outputs are used in the system only those outputs should be terminated. Not terminating the unused outputs will not only cut down the VCC noise generated but will also save in total system power dissipation. Following these guidelines will allow designers to either be more aggressive in their designs or provide them with an extra margin to the published data book specifications.
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9
ECLinPS PlusTM
MC10EP016 OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
D
8X
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
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GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z-
EE EE EE
MC10EP016 ECLinPS PlusTM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. - http://sps.motorola.com/mfax/ 852-26629298 HOME PAGE: http://motorola.com/sps/ JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
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MC10EP016/D
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