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| MC74VHCT50A Product Preview Noninverting Buffer / CMOS Logic Level Shifter with LSTTL-Compatible Inputs The MC74VHCT50A is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL-type input thresholds and the output has a full 5V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while operating at the high-voltage power supply. The MC74VHCT50A input structure provides protection when voltages up to 7V are applied, regardless of the supply voltage. This allows the MC74VHCT50A to be used to interface 5V circuits to 3V circuits. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. * High Speed: tPD = TBDns (Typ) at VCC = 5V * Low Power Dissipation: ICC = 2A (Max) at TA = 25C * TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V * CMOS-Compatible Outputs: VOH > 0.8VCC; VOL < 0.1VCC @Load * Power Down Protection Provided on Inputs and Outputs * Balanced Propagation Delays * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300mA * ESD Performance: HBM > 2000V; MM > 200V, CDM > 1500V LOGIC DIAGRAM A1 1 2 Y1 A1 A2 3 4 Y2 A2 A3 5 6 Y3 Y=A A4 9 8 Y4 A4 A5 Y5 A6 A6 13 12 Y6 1 Y6 A3 1 1 1 1 1 Y1 MC74VHCT50AD Y2 Y3 Y4 Y5 MC74VHCT50ADT MC74VHCT50AM SOIC TSSOP SOIC EIAJ 55 Units/Rail 96 Units/Rail 50 Units/Rail http://onsemi.com 14-LEAD SOIC D SUFFIX CASE 751A 14-LEAD TSSOP DT SUFFIX CASE 948G 14-LEAD SOIC EIAJ M SUFFIX CASE 965 PIN CONNECTION AND MARKING DIAGRAM (Top View) VCC 14 A6 13 Y6 12 A5 11 Y5 10 A4 9 Y4 8 1 A1 2 Y1 3 A2 4 Y2 5 A3 6 Y3 7 GND For detailed package marking information, see the Marking Diagram section on page 4 of this data sheet. LOGIC SYMBOL ORDERING INFORMATION Device Package Shipping A5 11 10 FUNCTION TABLE A Input L H Y Output L H This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. (c) Semiconductor Components Industries, LLC, 1999 1 October, 1999 - Rev. 0.0 Publication Order Number: MC74VHCT50A/D MC74VHCT50A MAXIMUM RATINGS* Characteristics DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Power Dissipation in Still Air, SOIC Packages TSSOP Package Lead temperature, 1 mm from case for 10 s (VOUT < GND; VOUT > VCC) VCC = 0 High or Low State Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TL Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -20 +20 +25 +50 500 450 260 Unit V V V mA mA mA mA mW C Storage temperature Tstg -65 to +150 C * Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Characteristics DC Supply Voltage DC Input Voltage DC Output Voltage VCC = 0 High or Low State Symbol VCC VIN VOUT TA tr , tf Min 4.5 0.0 0.0 0.0 -55 0 0 Max 5.5 5.5 5.5 VCC +85 100 20 Unit V V V C ns/V Operating Temperature Range Input Rise and Fall Time VCC = 3.3V 0.3V VCC = 5.0V 0.5V http://onsemi.com 2 MC74VHCT50A DC ELECTRICAL CHARACTERISTICS VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOH = -50A VIN = VIH or VIL IOH = -4mA IOH = -8mA VIN = VIH or VIL IOL = 50A VIN = VIH or VIL IOL = 4mA IOL = 8mA VIN = 5.5V or GND VIN = VCC or GND Input: VIN = 3.4V VOUT = 5.5V Test Conditions (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 0 to 5.5 5.5 5.5 0.0 2.9 4.4 2.58 3.94 0.0 0.0 0.1 0.1 0.36 0.36 0.1 2.0 1.35 0.5 3.0 4.5 Min 1.2 2.0 2.0 0.53 0.8 0.8 2.9 4.4 2.48 3.80 0.1 0.1 0.44 0.44 1.0 20 1.50 5.0 TA = 25C Typ Max TA 85C Min 1.2 2.0 2.0 0.53 0.8 0.8 2.9 4.4 2.34 3.66 0.1 0.1 0.52 0.52 1.0 40 1.65 10 A A mA A V V Max TA 125C Min 1.2 2.0 2.0 0.53 0.8 0.8 Max Unit V VIL V VOH V V VOL Maximum Low-Level Output Voltage VIN = VIH or VIL IIN ICC ICCT IOPD Maximum Input Leakage Current Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current II I I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIII IIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II I I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr = tf = 3.0ns) Symbol Parameter Test Conditions Min TA = 25C Typ 7.0 9.5 4.7 5.5 5 TA 85C TA 125C Max Min Max Min Max Unit ns tPLH, tPHL Maximum Propogation Delay, Input A to Y VCC = 3.0 0.3V VCC = 5.0 0.5V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 10.0 13.5 6.7 7.7 10 11.0 15.0 7.5 8.5 10 13.0 17.5 8.5 9.5 10 CIN Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0V 24 CPD Power Dissipation Capacitance (Note 1.) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V) TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.4 -0.4 Max 0.8 -0.8 3.5 1.5 Unit V V V V http://onsemi.com 3 MC74VHCT50A TEST POINT 3.0V A 50% GND tPLH tPHL VOH Y 50% VCC VOL *Includes all probe and jig capacitance OUTPUT DEVICE UNDER TEST CL* Figure 1. Switching Waveforms Figure 2. Test Circuit MARKING DIAGRAMS (Top View) 14 13 12 11 10 9 8 14 13 12 11 10 9 8 VHCT50A AWLYWW* 1 2 3 4 5 6 7 1 2 3 VHCT 50A ALYW* 4 5 6 7 14-LEAD SOIC D SUFFIX CASE 751A 14 13 12 11 10 9 8 14-LEAD TSSOP DT SUFFIX CASE 948G VHCT50A AWLYWW* 1 2 3 4 5 6 7 14-LEAD SOIC EIAJ M SUFFIX CASE 965 *See Applications Note #AND8004/D for date code and traceability information. http://onsemi.com 4 MC74VHCT50A PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 F SEATING PLANE D 14 PL 0.25 (0.010) M K T B S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.228 0.244 0.010 0.019 http://onsemi.com 5 MC74VHCT50A PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U S A -V- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E http://onsemi.com 6 CCC EE CCC EE SECTION N-N -W- MC74VHCT50A PACKAGE DIMENSIONS M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 965-01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P c b 0.13 (0.005) M A1 0.10 (0.004) http://onsemi.com 7 MC74VHCT50A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION USA/EUROPE Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line*: 303-675-2167 800-344-3810 Toll Free USA/Canada *To receive a Fax of our publications ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5487-8345 Email: r14153@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. America Technical Support: 800-282-9855 Toll Free USA/Canada http://onsemi.com 8 MC74VHCT50A/D |
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