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| QuickRAM Family Data Sheet * * * * * * Up to 90,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights High Performance & High Density * Up to 90,000 usable PLD gates with up to 316 I/Os * 300 MHz 16-bit counters, 400 MHz datapaths, 160+ MHz FIFOs * 0.35 m four-layer metal non-volatile CMOS process Up to 316 I/O Pins * Up to 308 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades * Eight high-drive input/distributed network pins Eight Low-Skew Distributed Networks * Two array clock/control networks are available to the logic cell flip-flop; clock, set, and reset inputs -- each can be driven by an input-only pin * Six global clock/control networks available to the logic cell; F1, clock, set, and reset inputs and the data input, I/O register clock, reset, and enable inputs as well as the output enable control--each can be driven by an input-only, I/O pin, any logic cell output, or I/O cell feedback High Speed Embedded SRAM * Up to 22 dual-port RAM modules, organized in user-configurable 1,152 bit blocks * 5 ns access times, each port independently accessible * Fast and efficient for FIFO, RAM, and ROM functions High Performance Silicon * Input + logic cell + output total delays under 6 ns * Data path speeds over 400 MHz * Counter speeds over 300 MHz * FIFO speeds over 160+ MHz Figure 1: QuickRAM Block Diagram Easy to Use/Fast Development Cycles * 100% routable with 100% utilization and complete pin-out stability * Variable-grain logic cells provide high performance and 100% utilization * Comprehensive design tools include high quality Verilog/VHDL synthesis Advanced I/O Capabilities * Interfaces with 3.3 V and 5.0 V devices * PCI compliant with 3.3 V and 5.0 V busses for -1/-2/-3/-4 speed grades * Full JTAG boundary scan * I/O cells with individually controlled registered input path and output enables (c) 2005 QuickLogic Corporation www.quicklogic.com * * 22 RAM Blocks 1,584 Hi gh Speed Logic Cells Interface * * * * 1 QuickRAM Family Data Sheet Rev. I Table 1: QuickRAM Product Family Members QL4009 Max Gates Logic Array Logic Cells Max Flip-Flops Max I/O RAM Modules RAM Bits PLCC TQFP Packages PQFP PBGA CQFP 47,052 16 x 16 160 242 74 8 9,216 68/84 100 QL4016 63,840 20 x 16 320 438 110 10 11,520 84 100/144 100 QL4036 97,128 28 x 24 672 876 196 14 16,128 144 208 256 QL4058 61,820 36 x 28 1,008 1,260 244 18 20,736 208/240 456 QL4090 44,964 44 x 36 1,584 1,900 308 22 25,334 208/240 456 208 Table 2: Max I/O per Device/Package Combination Device QL4009 QL4016 QL4036 QL4058 QL4090 68 PLCC 46 84 PLCC 60 60 100 TQFP 74 74 144 TQFP 110 110 208 PQFP 166 166 166 240 PQFP 194 194 256 PBGA 196 456 PBGA 244 308 100 CQFP 74 208 CQFP 166 2 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I Architecture Overview The QuickRAMTM family of Embedded Standard Products (ESP) offer FPGA logic in combination with DualPort SRAM modules. The QuickRAM family of ESPs have up to 90,000 usable PLD gates. QuickRAM ESPs are fabricated on a 0.35 m four-layer metal process using QuickLogic's patented ViaLinkTM technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QuickRAM family contains a range of 160 to 1,584 logic cells and 8 to 22 dual port RAM Modules (see Figure 1). Each RAM Module has 1,152 RAM bits, for a total ranging from 9,216 to 25,344 bits (see Table 1). RAM Modules are dual port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 (see Figure 2). With a maximum of 308 I/Os, the QuickRAM family of ESPs are available in many device/package combinations (see Table 2). Figure 2: QuickRAM Module [8:0] [17:0] WA WD WE WCLK RE RCLK RA RD ASYNCRD [8:0] [17:0] [1:0] MODE Designers can cascade multiple RAM Modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see Figure 3). This approach allows up to 512-deep configurations as large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device. Figure 3: QuickRAM Module Bits WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM Module (1,152 bits) WDATA RDATA (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 3 QuickRAM Family Data Sheet Rev. I Software support for the complete QuickRAM family is available through two basic packages. The turnkey QuickWorksTM package provides the most complete ESP software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM packages provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for design entry, synthesis, or simulation. The QuickLogic variable grain logic cell features up to 16 simultaneous inputs and 5 outputs within a cell that can be fragmented into 5 independent cells. Each cell has a fan-in of 29 including register and control lines (see Figure 4). Figure 4: QuickRAM Logic Cell QS A1 A2 A3 A4 A5 A6 QS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 QC QR AZ OZ QZ NZ FZ 4 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I Electrical Specifications AC Characteristics at VCC = 3.3 V, TA = 25 C (K = 1.00) To calculate delays, multiply the appropriate K factor from Table 12 by the numbers provided in Table 3 through Table 10. Table 3: Logic Cell Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delaya Setup Timea Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width Propagation Delays (ns) Fanout 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 2 1.7 1.7 0.0 1.0 1.2 1.2 1.3 1.1 1.9 1.8 3 1.9 1.7 0.0 1.2 1.2 1.2 1.5 1.3 1.9 1.8 4 2.2 1.7 0.0 1.5 1.2 1.2 1.8 1.6 1.9 1.8 5 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. Table 4: RAM Cell Synchronous Write Timing Symbol tSWA tHWA tSWD tHWD tSWE tHWE tWCRD Parameter WA Setup Time to WCLK WA Hold Time to WCLK WD Setup Time to WCLK WD Hold Time to WCLK WE Setup Time to WCLK WE Hold Time to WCLK WCLK to RD (WA=RA)a Propagation Delays (ns) Fanout 1 1.0 0.0 1.0 0.0 1.0 0.0 5.0 2 1.0 0.0 1.0 0.0 1.0 0.0 5.3 3 1.0 0.0 1.0 0.0 1.0 0.0 5.6 4 1.0 0.0 1.0 0.0 1.0 0.0 5.9 5 1.0 0.0 1.0 0.0 1.0 0.0 7.1 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 5 QuickRAM Family Data Sheet Rev. I Table 5: RAM Cell Synchronous Read Timing Symbol tSRA tHRA tSRE tHRE tRCRD Parameter RA Setup Time to RCLK RA Hold Time to RCLK RE Setup Time to RCLK RE Hold Time to RCLK RCLK to RD a Propagation Delays (ns) Fanout 1 1.0 0.0 1.0 0.0 4.0 2 1.0 0.0 1.0 0.0 4.3 3 1.0 0.0 1.0 0.0 4.6 4 1.0 0.0 1.0 0.0 4.9 5 1.0 0.0 1.0 0.0 6.1 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. Table 6: RAM Cell Asynchronous Read Timing Symbol RPDRD Parameter RA to RD a Propagation Delays (ns) Fanout 1 3.0 2 3.3 3 3.6 4 3.9 5 5.1 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. Table 7: Input-Only/Clock Cells Symbol tIN tINI tISU tIH tICLK tIRST tIESU tIEH Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time Propagation Delays (ns) Fanouta 1 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 2 1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0 3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0 4 1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0 8 2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0 12 2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in Table 12. 6 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I Table 8: Clock Cells Symbol tACK tGCKP tGCKB Parameter Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay Propagation Delays (ns) Fanouta 1 1.2 0.7 0.8 2 1.2 0.7 0.8 3 1.3 0.7 0.9 4 1.3 0.7 0.9 8 1.5 0.7 1.1 10 1.6 0.7 1.2 11 1.7 0.7 1.3 a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column. Table 9: I/O Cell Input Delays Symbol tI/O tISU tIH tIOCLK tIORST tIESU tIEH Parameter Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock to Q Input Register Reset Delay Input Register Clock Enable Set-Up Time Input Register Clock Enable Hold Time Propagation Delays (ns) Fanouta 1 1.3 3.1 0.0 0.7 0.6 2.3 0.0 2 1.6 3.1 0.0 1.0 0.9 2.3 0.0 3 1.8 3.1 0.0 1.2 1.1 2.3 0.0 4 2.1 3.1 0.0 1.5 1.4 2.3 0.0 8 3.1 3.1 0.0 2.5 2.4 2.3 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. Table 10: I/O Cell Output Delays Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter 3 Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-statea Output Delay High to Tri-state a Propagation Delays (ns) Output Load Capacitance (pF) 50 2.5 2.6 1.7 2.0 75 3.1 3.2 2.2 2.6 100 3.6 3.7 2.8 3.1 150 4.7 4.8 3.9 4.2 2.1 2.2 1.2 1.6 2.0 1.2 a. The loads presented in Figure 5 are used for tPXZ: Figure 5: Loads used for tPXZ t 1K PHZ 5 pF 1K t PLZ 5 pF (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 7 QuickRAM Family Data Sheet Rev. I DC Characteristics The DC specifications are provided in Table 11 through Table 13. Table 11: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity Value -0.5 to 4.6 V -0.5 to 7.0 V -0.5 V to VCCIO +0.5 V 200 mA Parameter DC Input Current ESD Pad Protection Storage Temperature Lead Temperature Value 20 mA 2000 V -65 C to +150 C 300 C Table 12: Operating Range Symbol VCC VCCIO TA TC Parameter Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade -1 Speed Grade K Delay Factor -2 Speed Grade -3 Speed Grade -4 Speed Grade Military Min. 3.0 3.0 -55 0.42 0.42 0.42 Max. 3.6 5.5 125 2.03 1.64 1.37 Industrial Min. 3.0 3.0 -40 0.43 0.43 0.43 0.43 0.43 Max. 3.6 5.5 85 1.90 1.54 1.28 0.90 0.82 Commercial Min. 3.0 3.0 0 0.46 0.46 0.46 0.46 0.46 Max. 3.6 5.25 70 1.85 1.50 1.25 0.88 0.80 Unit V V C C n/a n/a n/a n/a n/a Table 13: DC Characteristics Symbol VIH VIL VOH VOL II IOZ CI IOS ICC ICCIO Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance b Conditions Min. 0.5 VCC -0.5 Max. VCCIO + 0.5 0.3 VCC VCC VCC 0.45 0.1 VCC Units V V V V V V A A pF mA mA mA A IOH = -12 mA IOH = -500 A IOL = 16 mA a 2.4 0.9 VCC IOL = 1.5 mA VI = VCCIO or GND VI = VCCIO or GND VO = GND VO = VCC VI, VIO = VCCIO or GND -10 -10 -15 40 0.50 (typ) 0 10 10 10 -180 210 2 100 Output Short Circuit Currentc D.C. Supply Currentd D.C. Supply Current on VCCIO a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. b. Capacitance is sample tested only. Clock pins are 12 pF maximum. c. Only one output at a time. Duration should not exceed 30 seconds. d. For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices. and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer applications group. 8 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I Kv and Kt Graphs Figure 6: Voltage Factor vs. Supply Voltage Voltage Factor vs. Supply Voltage 1.1000 1.0800 1.0600 1.0400 Kv 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage (V) Figure 7: Temperature Factor vs. Operating Temperature Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80 Kt Junction Temperature C (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 9 QuickRAM Family Data Sheet Rev. I Power-Up Sequencing Figure 8: Power-Up Requirements VCCIO Voltage VCC (VCCIO -VCC)MAX VCC 400 us Time When powering up a device, the VCC/VCCIO rails must take 400 s or longer to reach the maximum value (refer to Figure 7). NOTE: Ramping VCC/VCCIO to the maximum voltage faster than 400 s can cause the device to behave improperly. For users with a limited power budget, keep (VCCIO -VCC)MAX 500 mV when ramping up the power supply. 10 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I JTAG Figure 9: JTAG Block Diagram TCK TMS TRSTB TAP Controller State Machine (16 States) Instruction Decode and Control Logic Instruction Register RDI Mux Boundary-Scan Register (Data Register) Mux TDO Bypass Register Internal Register I/O Registers User Defined Data Register Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. The 1149.1 standard requires the following three tests: * Extest Instruction. The Extest Instruction performs a Printed Circuit Board (PCB) interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 11 QuickRAM Family Data Sheet Rev. I * Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. Pin Descriptions Table 14: Pin Descriptions Pin TDI/RSI Function Test Data In for JTAG /RAM init. Serial Data In Active low Reset for JTAG /RAM init. reset out Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG /RAM init. clock out Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-drive input Input/Output pin Power supply pin Input voltage tolerance pin Ground pin Ground/Thermal pin Description Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused. Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization. Must be grounded during normal operation. Can be configured as either or both. Can be configured as either or both. Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3 V supply. Connect to 5.0 V supply if 5 V input tolerance is required, otherwise connect to 3.3 V supply. Connect to ground. Available on 456-PBGA only. Connect to ground plane on PCB if heat sinking desired. Otherwise may be left unconnected. TRSTB/RRO TMS TCK TDO/RCO STM I/ACLK I/GCLK I I/O VCC VCCIO GND GND/THERM 12 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I QL4009 - 68 PLCC Pinout Diagram Figure 10: QL4009 - 68 Pin PLCC (Top View) 987 65 43 2 1 68 67 66 65 64 63 62 61 TDO IO IO IO IO VCCIO IO IO GND IO IO IO IO IO IO STM TCK QL4009 - 68 PLCC Pinout Table Table 15: QL4009 - 68 PLCC Pinout Table 68 PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function GND I/O I/O VCCIO I/O I/O I/O I/O TDO I/O I/O I/O I/O GND I/O GCLK/I ACLK/I 68 PLCC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function VCC GCLK/I GCLK/I I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O 68 PLCC 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function GND I/O I/O I/O VCCIO I/O I/O TRSTB TMS I/O I/O I/O I/O GND I/O GCLK/I ACLK/I 68 PLCC 52 53 54 55 56 57 58 58 60 61 62 63 64 65 66 67 68 Function VCC GCLK/I GCLK/I I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O I/O I/O TDI IO IO IO IO IO IO IO GND IO IO IO VCCIO IO IO TRSTB TMS 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 IO IO IO IO GND IO GCLK/I ACLK/I VCC GCLK/I GCLK/I IO IO IO IO IO IO QuickRAM QL4009-1PL68C IO IO IO IO IO IO GCLK/I GCLK/I VCC ACLK/I GCLK/I IO GND IO IO IO IO 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 13 QuickRAM Family Data Sheet Rev. I QL4009 - 84 PLCC Pinout Diagram Figure 11: QL4009 - 84 Pin PLCC (Top View) 11 10 9 87 65 43 2 1 84 83 82 81 80 79 78 77 76 75 TDO IO IO IO IO IO IO VCCIO IO IO IO IO IO GND IO IO VCC IO IO STM TCK 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 QL4009 - 84 PLCC Pinout Table Table 16: QL4009 - 84 PLCC Pinout Table 84 PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK/I 84 PLCC 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Function ACLK/I GCLK/I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O VCC I/O I/O I/O GND I/O I/O 84 PLCC 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Function I/O I/O I/O VCCIO I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK/I 84 PLCC 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Function ACLK/I GCLK/I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O VCC I/O I/O GND I/O I/O 14 * www.quicklogic.com * * * * * TDI IO IO VCC IO IO IO GND IO IO IO IO IO VCCIO IO IO IO IO IO TRSTB TMS IO IO IO IO IO IO IO GND IO GCLK/I ACLK/I GCLK/I GCLK/I VCC IO IO IO IO IO IO IO QuickRAM QL4009-1PL84C IO IO IO IO IO IO IO VCC GCLK/I GCLK/I ACLK/I GCLK/I IO GND IO IO IO IO IO IO IO 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I QL4009 - 100 TQFP Pinout Diagram Figure 12: QL4009 - 100 Pin TQFP (Top View) Pin 1 Pin 76 QuickRAM QL4009-1PF100C Pin 26 Pin 51 QL4009 - 100 TQFP Pinout Table Table 17: QL4009 - 100 TQFP Pinout Table 100TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK/I VCC I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O 100TQFP 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Function TDI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O TRSTB TMS 100TQFP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK/I VCC I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O 100TQFP 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function TCK STM I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O TDO (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 15 QuickRAM Family Data Sheet Rev. I QL4016 - 84 PLCC Pinout Diagram Figure 13: QL4016 - 84 Pin PLCC (Top View) 11 10 9 87 65 43 2 1 84 83 82 81 80 79 78 77 76 75 TDO IO IO IO IO IO IO VCCIO IO IO IO IO IO GND IO IO VCC IO IO STM TCK 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 QL4016 - 84 PLCC Pinout Table Table 18: QL4016 - 84 PLCC Pinout Table 84 PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O GND I/O I 84 PLCC 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Function ACLK/I I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O VCC I/O I/O I/O GND I/O I/O 84 PLCC 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Function I/O I/O I/O VCCIO I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O GND I/O I 84 PLCC 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Function ACLK/I I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O VCC I/O I/O GND I/O I/O 16 * www.quicklogic.com * * * * * TDI IO IO VCC IO IO IO GND IO IO IO IO IO VCCIO IO IO IO IO IO TRSTB TMS IO IO IO IO IO IO IO GND IO I ACLK/I I GCLK/I VCC IO IO IO IO IO IO IO QuickRAM QL4016-1PL84C IO IO IO IO IO IO IO VCC GCLK/I I ACLK/I I IO GND IO IO IO IO IO IO IO 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I QL4016 - 100 TQFP/CQFP Pinout Diagram Figure 14: QL4016 - 100 Pin TQFP/CQFP (Top View) Pin 1 Pin 76 QuickRAM QL4016-1PF100C Pin 26 Pin 51 QL4016 - 144 TQFP Pinout Diagram Figure 15: QL4016 - 144 Pin TQFP (Top View) Pin 1 Pin 109 QuickRAM QL4016-1PF144C Pin 37 Pin 73 (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 17 QuickRAM Family Data Sheet Rev. I QL4016 - 144 TQFP and 100 TQFP/CQFP Pinout Table Table 19: QL4016 - 144 TQFP and 100 TQFP/CQFP Pinout Table 144TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 100TQFP 2 3 NC 4 NC 5 NC 6 NC 7 NC NC 8 NC 9 10 11 12 13 14 15 16 17 18 NC 19 NC 20 21 NC NC 22 23 NC NC 24 25 Function I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK/I VCC I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O 144TQFP 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 100TQFP 26 27 28 29 NC 30 31 NC 32 33 NC 34 35 36 NC 37 38 39 40 41 42 NC 43 44 45 NC NC 46 NC NC NC 47 48 49 50 51 52 Function TDI I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TRSTB TMS I/O I/O 144TQFP 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NC 97 98 99 100 101 102 103 104 105 106 107 108 109 110 100TQFP 53 54 55 NC NC NC 56 NC 57 NC 58 NC 59 60 61 62 63 64 65 66 67 NC 68 NC 69 NC 70 71 NC NC 72 NC 73 74 75 76 77 Function I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK/I VCC I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O TCK STM 144TQFP 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 NC 137 138 139 140 141 142 143 144 100TQFP 78 79 80 NC 81 82 83 NC 84 NC NC 85 NC 86 87 88 89 90 91 92 NC 93 NC 94 NC NC 95 NC NC 96 97 98 99 100 1 Function I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TDO I/O 18 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I QL4036 - 144 TQFP Pinout Diagram Figure 16: QL4036 - 144 Pin TQFP (Top View) Pin 1 Pin 109 QuickRAM QL4036-1PF144C Pin 37 Pin 73 QL4036 - 208 PQFP Pinout Diagram Figure 17: QL4036 - 208 Pin PQFP (Top View) Pin 1 Pin 157 QuickRAM QL4036-1PQ208C Pin 53 Pin 105 (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 19 QuickRAM Family Data Sheet Rev. I QL4036 - 144 TQFP and 208 PQFP Pinout Table Table 20: QL4036 - 144 TQFP and 208 PQFP Pinout Table 208 PQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 144 TQFP NC 1 2 3 NC 4 5 NC 6 7 NC NC 8 NC 9 NC 10 11 12 13 NC 14 15 16 17 18 19 20 21 22 23 NC 24 NC 25 NC 26 27 28 NC NC 29 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK/I ACLK/I VCC GCLK/I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O 208 PQFP 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 144 TQFP 30 31 NC 32 NC 33 NC 34 35 36 37 38 39 NC 40 NC NC 41 42 43 NC 44 45 NC 46 47 48 NC 49 NC 50 51 52 NC 53 54 55 56 NC 57 58 59 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O 208 PQFP 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 144 TQFP 60 61 NC 62 63 NC NC 64 NC 65 66 67 NC NC 68 69 NC 70 71 72 NC 73 NC 74 75 76 77 NC 78 79 80 NC 81 82 NC 83 NC 84 85 NC 86 NC Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 208 PQFP 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 144 TQFP 87 88 89 90 91 92 93 94 95 NC 96 NC 97 98 NC 99 NC 100 NC 101 102 103 104 NC 105 106 NC 107 NC 108 109 110 111 NC 112 113 NC NC 114 115 116 NC Function GND I/O GCLK/I ACLK/I VCC GCLK/I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O GND I/O VCC I/O I/O I/O 208 PQFP 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 144 TQFP 117 118 119 120 NC NC 121 NC 122 123 124 NC 125 126 127 128 129 NC 130 131 132 NC 133 134 NC 135 136 NC 137 NC 138 139 NC 140 NC 141 142 NC 143 144 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO I/O 20 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I QL4036 - 256 PBGA Pinout Diagram Figure 18: QL4036 - 256 PBGA Pinout Diagram TOP View QuickRAM QL4036-1PB256C BOTTOM View 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIN A1 CORNER (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 21 QuickRAM Family Data Sheet Rev. I QL4036 - 256 PBGA Pinout Table Table 21: QL4036 - 256 PBGA Pinout Table 256 PBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 Function VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC STM NC I/O I/O I/O I/O 256 PBGA C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 Function I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VSS I/O VCC I/O VSS I/O I/O VCC I/O VSS I/O VCC I/O VSS I/O I/O I/O NC I/O I/O I/O I/O I/O 256 PBGA E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1 Function I/O I/O I/O I/O I/O VCC VCC NC I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O VSS VSS I/O I/O I/O I/O I/O NC I/O NC I/O I/O GCLK/I I/O I/O I/O VCC GCLK/I ACLK/I GCLK/I NC GCLK/I 256 PBGA L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 Function ACLK/I GCLK/I GCLK/I VCC I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O VSS VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O I/O VCC VCC I/O I/O I/O NC I/O I/O NC 256 PBGA T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 Function I/O I/O NC I/O I/O I/O I/O VSS I/O VCC I/O VSS I/O VCC I/O I/O VSS I/O VCC I/O VSS I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O TMS 256 PBGA V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Function I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC 22 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I QL4058 - 208 and 240 PQFP Pinout Diagrams Figure 19: QL4058 - 208 Pin PQFP (Top View) Pin 1 Pin 157 QuickRAM QL4058-1PQ208C Pin 53 Pin 105 Figure 20: QL4058 - 240 Pin PQFP (Top View) Pin 1 Pin 181 QuickRAM QL4058-1PQ240C Pin 61 Pin 121 (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 23 QuickRAM Family Data Sheet Rev. I QL4058 - 208 and 240 PQFP Pinout Table Table 22: QL4058 - 208/240 PQFP Pinout Table 240 PQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 208 PQFP 208 1 2 3 4 5 NC 6 7 8 9 10 11 12 13 14 NC 15 16 17 18 19 20 NC 21 22 23 24 25 26 27 28 29 30 31 32 NC 33 NC 34 35 36 NC 37 38 39 NC 40 41 42 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK/I ACLK/I VCC GCLK/I GCLK/I VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O 240 PQFP 51 52 53 54 55 56 57 58 59 60 NC NC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC 84 85 86 87 88 89 90 91 92 93 94 95 96 97 208 PQFP 43 44 45 46 47 48 NC 49 50 51 52 53 54 NC NC 55 56 NC 57 58 59 60 61 62 63 64 NC 65 66 67 NC 68 69 70 NC 71 NC 72 73 74 NC 75 76 77 78 79 80 81 82 83 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O GND I/O I/O I/O I/O VCCIO 240 PQFP 98 99 100 101 102 103 104 105 106 107 108 109 110 NC 111 NC NC 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 208 PQFP 84 85 86 87 88 89 90 91 92 NC 93 94 95 96 97 98 99 100 NC 101 NC 102 NC NC 103 104 105 NC 106 107 108 109 NC 110 111 112 113 114 115 116 117 NC 118 119 120 121 NC 122 123 124 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 240 PQFP 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 NC 181 182 183 184 185 186 187 188 189 190 191 192 193 208 PQFP 125 126 127 128 NC 129 130 131 132 133 134 135 136 NC 137 NC 138 139 140 141 142 NC 143 144 145 NC 146 147 148 149 150 151 152 153 154 155 156 157 158 NC 159 160 161 162 163 164 165 166 NC 167 Function I/O I/O GND I/O I/O GLCK/I ACLK/I VCC GLCK/I GLCK/I VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O 240 PQFP 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 208 PQFP 168 169 NC 170 171 172 173 174 175 NC 176 177 178 179 NC 180 181 182 NC 183 184 185 186 187 188 NC 189 190 191 192 193 194 NC 195 196 197 198 NC 199 200 201 202 203 204 205 206 207 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO 24 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I QL4058 - 456 PBGA Pinout Diagram Figure 21: QL4058 - 456 PBGA Pinout Diagram TOP View QuickRAM QL4058-1PB456C BOTTOM View 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF PIN A1 CORNER (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 25 QuickRAM Family Data Sheet Rev. I QL4058 - 456 PBGA Pinout Table Table 23: QL4058 - 456 PBGA Pinout Table 456 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 Function I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O VCCIO I/O I/O NC I/O NC I/O I/O I/O NC I/O NC I/O I/O I/O I/O NC I/O NC NC NC NC NC I/O NC NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O STM 456 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 Function I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O TCK NC I/O I/O I/O GND NC NC I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O GND I/O NC NC I/O GND I/O I/O I/O 456 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 Function I/O I/O I/O I/O GND VCC GND NC GND I/O GND GND VCC GND GND GND NC GND NC GND VCC GND I/O I/O I/O I/O I/O I/O NC NC VCC VCC NC I/O I/O I/O I/O I/O I/O I/O NC GND NC I/O I/O I/O NC I/O NC I/O NC NC 456 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 Function NC I/O NC I/O I/O I/O I/O NC GND NC NC I/O I/O I/O NC NC I/O I/O VCC GND I/O I/O NC I/O I/O I/O I/O I/O NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC I/O I/O NC I/O ACLK/I GCLK/I I/O NC GND GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC 456 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 Function NC I/O I/O I/O GCLK/I I/O I/O GCLK/I VCC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND I/O I/O NC I/O I/O I/O NC I/O NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC GCLK/I GCLK/I NC ACLK/I NC I/O I/O NC NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM VCC NC NC I/O GCLK/I 26 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I Table 23: QL4058 - 456 PBGA Pinout Table (Continued) 456 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 Function I/O I/O I/O I/O VCC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND I/O I/O NC I/O NC I/O I/O I/O GND NC I/O I/O I/O I/O I/O I/O NC NC NC GND NC I/O NC I/O I/O I/O I/O I/O 456 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 Function NC NC I/O I/O I/O NC NC I/O NC I/O I/O GND I/O NC I/O I/O I/O I/O NC NC VCC VCC NC I/O I/O I/O NC I/O I/O I/O GND VCC NC NC NC VCC GND NC I/O GND 456 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 Function VCC I/O NC VCC GND NC VCC GND I/O NC I/O I/O I/O I/O NC GND NC NC NC NC NC NC I/O NC I/O VCCIO NC NC NC NC I/O I/O I/O NC GND NC I/O I/O I/O NC 456 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 Function I/O I/O I/O I/O I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O TRSTB NC I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 456 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Function I/O I/O I/O I/O I/O NC NC TMS I/O I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O NC I/O I/O NC NC I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 27 QuickRAM Family Data Sheet Rev. I QL4090 - 208 PQFP/CQFP and 240 PQFP Pinout Diagrams Figure 22: QL4090 - 208 Pin PQFP/CQFP (Top View) Pin 1 Pin 157 QuickRAM QL4090-1PQ208C Pin 53 Figure 23: QL4090 - 240 Pin PQFP (Top View) Pin 1 Pin 105 Pin 181 QuickRAM QL4090-1PQ240C Pin 61 Pin 121 28 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I QL4090 - 208 PQFP/CQFP and 240 PQFP Pinout Table Table 24: QL4090 - 208 PQFP/CQFP and 240 PQFP Pinout Table 240 PQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 208 PQFP 208 1 2 3 4 5 NC 6 7 8 9 10 11 12 13 14 NC 15 16 17 18 19 20 NC 21 22 23 24 25 26 27 28 29 30 31 32 NC 33 NC 34 35 36 NC 37 38 39 NC 40 41 42 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK/I ACLK/I VCC GCLK/I GCLK/I VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O 240 PQFP 51 52 53 54 55 56 57 58 59 60 NC NC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC 84 85 86 87 88 89 90 91 92 93 94 95 96 97 208 PQFP 43 44 45 46 47 48 NC 49 50 51 52 53 54 NC NC 55 56 NC 57 58 59 60 61 62 63 64 NC 65 66 67 NC 68 69 70 NC 71 NC 72 73 74 NC 75 76 77 78 79 80 81 82 83 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O GND I/O I/O I/O I/O VCCIO 240 PQFP 98 99 100 101 102 103 104 105 106 107 108 109 110 NC 111 NC NC 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 208 PQFP 84 85 86 87 88 89 90 91 92 NC 93 94 95 96 97 98 99 100 NC 101 NC 102 NC NC 103 104 105 NC 106 107 108 109 NC 110 111 112 113 114 115 116 117 NC 118 119 120 121 NC 122 123 124 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 240 PQFP 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 NC 181 182 183 184 185 186 187 188 189 190 191 192 193 208 PQFP 125 126 127 128 NC 129 130 131 132 133 134 135 136 NC 137 NC 138 139 140 141 142 NC 143 144 145 NC 146 147 148 149 150 151 152 153 154 155 156 157 158 NC 159 160 161 162 163 164 165 166 NC 167 Function I/O I/O GND I/O I/O GLCK/I ACLK/I VCC GLCK/I GLCK/I VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O 240 PQFP 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 208 PQFP 168 169 NC 170 171 172 173 174 175 NC 176 177 178 179 NC 180 181 182 NC 183 184 185 186 187 188 NC 189 190 191 192 193 194 NC 195 196 197 198 NC 199 200 201 202 203 204 205 206 207 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 29 QuickRAM Family Data Sheet Rev. I QL4090 - 456 PBGA Pinout Diagram Figure 24: QL4090 - 456 PBGA Pinout Diagram TOP View QuickRAM QL4090-1PB456C BOTTOM View 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF PIN A1 CORNER 30 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I QL4090 - 456 PBGA Pinout Table Table 25: QL4090 - 456 PBGA Pinout Table 456 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O STM 456 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 Function I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK I/O I/O I/O I/O GND I/O NC I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O NC I/O GND I/O I/O I/O 456 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 Function I/O I/O I/O I/O GND VCC GND NC GND I/O GND GND VCC GND GND GND NC GND NC GND VCC GND I/O I/O I/O I/O I/O I/O I/O NC VCC VCC NC I/O I/O I/O I/O I/O I/O I/O NC GND I/O I/O I/O I/O I/O I/O I/O I/O NC NC 456 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 Function I/O I/O I/O I/O I/O I/O I/O NC GND NC NC I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC I/O I/O I/O I/O ACLK/I GCLK/I I/O NC GND GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC 456 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 p26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 Function NC I/O I/O I/O GCLK/I I/O I/O GCLK/I VCC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND I/O I/O I/O I/O I/O I/O I/O I/O NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC GCLK/I GCLK/I I/O ACLK/I I/O I/O I/O NC NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM VCC NC I/O I/O GCLK/I (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 31 QuickRAM Family Data Sheet Rev. I Table 25: QL4090 - 456 PBGA Pinout Table (Continued) 456 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 Function I/O I/O I/O I/O VCC GND/THERMAL GND/THERMAL GND/THERMAL GND/THERMAL GND/THERMAL GND/THERMAL GND I/O I/O I/O I/O I/O I/O I/O I/O GND NC I/O I/O I/O I/O I/O I/O I/O NC NC GND NC I/O I/O I/O I/O I/O I/O I/O 456 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 Function NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O NC NC VCC VCC NC I/O I/O I/O I/O I/O I/O I/O GND VCC NC NC NC VCC GND NC I/O GND 456 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 Function VCC I/O NC VCC GND NC VCC GND I/O I/O I/O I/O I/O I/O NC GND I/O NC I/O I/O NC I/O I/O NC I/O VCCIO NC I/O I/O NC I/O I/O I/O NC GND I/O I/O I/O I/O NC 456 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 456 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Function I/O I/O I/O I/O I/O I/O NC TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 32 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I Package Mechanical Drawings 68 PLCC Mechanical Drawing (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 33 QuickRAM Family Data Sheet Rev. I 84 PLCC Mechanical Drawing 34 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I 100 CQFP Mechanical Drawing (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 35 QuickRAM Family Data Sheet Rev. I 100 TQFP Mechanical Drawing 36 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I 144 TQFP Mechanical Drawing (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 37 QuickRAM Family Data Sheet Rev. I 208 CQFP Mechanical Drawing 38 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I 208 PQFP Mechanical Drawing (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 39 QuickRAM Family Data Sheet Rev. I 240 PQFP Mechanical Drawing 40 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I 256 PBGA Mechanical Drawing (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 41 QuickRAM Family Data Sheet Rev. I 456 PBGA Mechanical Drawing 42 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QuickRAM Family Data Sheet Rev. I Packaging Information The QuickRAM product family packaging information is presented in Table 26. NOTE: Military temperature range plastic packages will be added as follow on products to the commercial and industrial products. Table 26: Packaging Options Device Device Information Pin 68 PLCC Package Definitionsa 84 PLCC 100 TQFP QL4009 Pitch 0.05 in. 0.05 in. 0.5 mm Pin 84 PLCC 100 TQFP 144 TQFP 100 CQFP QL4016 Pitch 0.05 in. 0.5 mm 0.5 mm 0.025 in. Pin 144 TQFP 208 PQFP 256 PBGA QL4036 Pitch 0.5 mm 0.5 mm 1.27 mm Pin 208 PQFP 240 PQFP 456 PBGA QL4058 Pitch 0.5 mm 0.5 mm 1.27 mm Pin 208 PQFP 240 PQFP 456 PBGA 208 CQFP QL4090 Pin 0.5 mm 0.5 mm 1.27 mm 0.5 mm a. PLCC PQFP PBGA TQFP CQFP = = = = = Plastic Leaded Chip Carrier Plastic Quad Flat Pack Plastic Ball Grid Array Thin Quad Flat Pack Ceramic Quad Flat Pack Ordering Information QL QuickLogic Device Part Number: 4009, 4016, 4036, 4058, 4090 Operating Range: C = Commercial I = Industrial M = Military 4090 -1 PQ208 C Speed Grade: 0 - Quick 1 - Fast Package Code: 2 - Faster PL68 = 68-pin PLCC 3 - Faster PF84 = 84-pin PLCC 4 - Wow** PF100 (PFN100)* = 100-pin TQFP PF144 (PFN144)* = 144-pin TQFP PQ208 = 208-pin PQFP PQ240 = 240-pin PQFP PB256 = 256-ball PBGA PB456 = 456-ball PBGA CF100 = 100-pin CQFP CF208 = 208-pin CQFP * Lead-free packaging is available, contact QuickLogic regarding availability (see Contact Information). ** Contact QuickLogic regarding availability (see Contact Information) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 43 QuickRAM Family Data Sheet Rev. I Contact Information Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932 57 9011 (Europe - except Germany/Benelux) +(49) 89 930 86 170 (Germany/Benelux) +(86) 21 6867 0273 (Asia - except Japan) +(81) 45 470 5525 (Japan) E-mail: Sales: info@quicklogic.com www.quicklogic.com/sales Support: www.quicklogic.com/support Internet: www.quicklogic.com Revision History Revision A through G H I Date Not available March 2002 March 2005 Originator and Comments Not available Brian Faith and Andreea Rotaru Mehul Kochar and Kathleen Murchek Copyright and Trademark Information Copyright (c) 2005 QuickLogic Corporation. All Rights Reserved. The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, ViaLink, QuickRAM, and QuickWorks are registered trademarks of QuickLogic Corporation; QuickTools and SpDE are trademarks of QuickLogic Corporation. Verilog is a registered trademark of Cadence Design Systems, Inc. 44 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation |
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