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| SN74LVC652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS303A - JANUARY 1993 - REVISED JULY 1995 D D D D D EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages DB, DW, OR PW PACKAGE (TOP VIEW) description This octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation. CLKAB SAB OEAB A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC CLKBA SBA OEBA B1 B2 B3 B4 B5 B6 B7 B8 The SN74LVC652 consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVC652. Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The SN74LVC652 is characterized for operation from - 40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1995, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74LVC652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS303A - JANUARY 1993 - REVISED JULY 1995 FUNCTION TABLE INPUTS OEAB L L X H L L L L H H H OEBA H H H H X L L L H H L CLKAB H or L H or L X X X H or L H or L CLKBA H or L H or L X H or L X X H or L SAB X X X X X X X X L H H SBA X X X X X X L H X X H Input Input Input Input Unspecified Output Output Output Input Input Output DATA I/O A1 THRU A8 B1 THRU B8 Input Input Unspecified Output Input Input Input Input Output Output Output OPERATION OR FUNCTION Isolation Store A and B data Store A, hold B Store A in both registers Hold A, store B Store B in both registers Real-time B data to A bus Stored B data to A bus Real-time A data to B bus Stored A data to B bus Stored A data to B bus and stored B data to A bus The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs. Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered in order to load both registers. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74LVC652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS303A - JANUARY 1993 - REVISED JULY 1995 BUS B 3 21 OEAB OEBA L L 1 23 2 CLKAB CLKBA SAB X X X 22 SBA L 3 21 OEAB OEBA H H 1 CLKAB X 23 CLKBA X 2 SAB L BUS B 22 SBA X REAL-TIME TRANSFER BUS A TO BUS B 1 CLKAB H or L 23 CLKBA H or L 2 SAB H BUS B 22 SBA H TRANSFER STORED DATA TO A AND/OR B BUS A REAL-TIME TRANSFER BUS B TO BUS A BUS B BUS A 3 OEAB X L L 21 OEBA H X H 1 23 2 CLKAB CLKBA SAB X X X X X 22 SBA X X X 3 OEAB H 21 OEBA L STORAGE FROM A, B, OR A AND B Figure 1. Bus-Management Functions POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 BUS A BUS A 3 SN74LVC652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS303A - JANUARY 1993 - REVISED JULY 1995 logic symbol OEBA OEAB CLKBA SBA CLKAB SAB 21 3 23 22 1 2 EN1 [BA] EN2 [AB] C4 G5 C6 G7 1 1 6D 1 A2 A3 A4 A5 A6 A7 A8 5 6 7 8 9 10 11 7 7 19 18 17 16 15 14 13 B2 B3 B4 B5 B6 B7 B8 5 51 1 2 4D 20 B1 A1 4 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74LVC652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS303A - JANUARY 1993 - REVISED JULY 1995 logic diagram (positive logic) OEBA 21 OEAB CLKBA SBA CLKAB SAB 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 1D C1 B1 To Seven Other Channels POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN74LVC652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS303A - JANUARY 1993 - REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . 1.7 W PW package . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) MIN VCC VIH VIL VI VO IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level High level output current Low-level Low level output current Input transition rise or fall rate VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V 0 - 40 Operating Data retention only VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V Control inputs Data inputs 2 1.5 2 0.8 0 0 0 5.5 VCC VCC - 12 - 24 12 24 10 85 MAX 3.6 UNIT V V V V V mA mA ns / V C TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74LVC652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS303A - JANUARY 1993 - REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = - 100 A VOH IOH = - 12 mA IOH = - 24 mA IOL = 100 A VOL II IOZ ICC Ci IOL = 12 mA IOL = 24 mA VI = 5.5 V or GND VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC MIN to MAX 2.7 V 3V 3V MIN to MAX 2.7 V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 4.6 7.2 MIN TYP MAX UNIT VCC - 0.2 2.2 2.4 2 0.2 0.4 0.55 5 10 20 500 A A A A pF pF V V nICC Control inputs VI = VCC or GND 3.3 V Cio A or B ports VO = VCC or GND 3.3 V For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. All typical values are measured at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. timing characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) VCC = 3.3 V 0.3 V MIN fclock tw tsu th Clock frequency Pulse duration Setup time, data before CLK Hold time, data after CLK 0 5 5 1 MAX 100 VCC = 2.7 V MIN 0 5 5 1 MAX 80 MHz ns ns ns UNIT switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER fmax A or B tpd ten tdis ten tdis CLK SAB or SBA OE OE OE OE B or A A or B A or B A or B A or B A or B A or B FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN 100 1.5 1.5 1.5 1.5 1.5 1.5 1.5 8 9 9 8.5 8.5 9 9 MAX VCC = 2.7 V MIN 80 9.2 11 11 9.5 9.5 10 10 ns ns ns ns ns MAX MHz UNIT POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN74LVC652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS303A - JANUARY 1993 - REVISED JULY 1995 operating characteristics, VCC = 3.3 V, TA = 25C PARAMETER Cpd d Power dissipation capacitance per transceiver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF f = 10 MHz pF, TYP 38 4.2 UNIT pF PARAMETER MEASUREMENT INFORMATION 6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND LOAD CIRCUIT FOR OUTPUTS 2.7 V Timing Input 1.5 V 0V tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Data Input tsu 1.5 V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V tPZL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 3V VOL + 0.3 V VOL 1.5 V 0V 2.7 V Input tPLH Output 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Control 1.5 V [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated |
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