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SN74LVC823 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS305A - MARCH 1993 - REVISED AUGUST 1995
D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages
DB, DW, OR PW PACKAGE (TOP VIEW)
description
This 9-bit bus-interface flip-flop is designed for 2.7-V to 3.6-V VCC operation.
OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLKEN CLK
The SN74LVC823 is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, latching the outputs. The SN74LVC823 has noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low independently of the clock. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The output-enable (OE) input does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVC823 is characterized for operation from - 40C to 85C.
FUNCTION TABLE (each flip-flop) INPUTS OE L L L L H CLR L H H H X CLKEN X L L H X CLK X X X D X H L X X OUTPUT Q L H L Q0 Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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* DALLAS, TEXAS 75265
1
SN74LVC823 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS305A - MARCH 1993 - REVISED AUGUST 1995
logic symbol
OE CLR CLKEN CLK 1 11 14 13 EN R G1 1C2 23 22 21 20 19 18 17 16 15
1D 2D 3D 4D 5D 6D 7D 8D 9D
2 3 4 5 6 7 8 9 10
2D
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE CLR CLKEN 1 11 14
CLK
13
R C1 1D 2 1D 23 1Q
To Eight Other Channels
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC823 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS305A - MARCH 1993 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . 1.7 W PW package . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
MIN VCC VIH VIL VI VO IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level High level output current Low-level Low level output current Input transition rise or fall rate VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V 0 - 40 VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2.7 2 0.8 0 0 5.5 VCC - 12 - 24 12 24 10 85 MAX 3.6 UNIT V V V V V mA mA ns / V C
TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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SN74LVC823 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS305A - MARCH 1993 - REVISED AUGUST 1995
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = - 100 A VOH IOH = - 12 mA IOH = - 24 mA IOL = 100 A VOL II IOZ ICC Ci Co IOL = 12 mA IOL = 24 mA VI = 5.5 V or GND VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, VI = VCC or GND VO = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC MIN to MAX 2.7 V 3V 3V MIN to MAX 2.7 V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 3.3 V 3.3 V 9 10 MIN TYP MAX UNIT VCC - 0.2 2.2 2.4 2 0.2 0.4 0.55 5 10 20 500 A A A A pF pF V
V
nICC
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. All typical values are at VCC = 3.3 V, TA = 25C.
timing characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 1)
VCC = 3.3 V 0.3 V MIN fclock tw Clock frequency Pulse duration CLR low CLK high or low CLR inactive tsu Setup time, data before CLK Data CLKEN low th Hold time, data after CLK time Data CLKEN low 0 5 4 1 2 3.5 2 0.5 MAX 100 VCC = 2.7 V MIN 0 5 4 1 3 4.5 2 0.5 ns ns MAX 80 MHz ns UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd d ten tdis CLK CLR OE OE Q Q Q Q FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN 100 2 1.5 1.5 1.5 8 8 8.5 8 MAX VCC = 2.7 V MIN 80 2 1.5 1.5 1.5 9 9 9.5 9 MAX MHz ns ns ns UNIT
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC823 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS305A - MARCH 1993 - REVISED AUGUST 1995
operating characteristics, VCC = 3.3 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per flip-flop flip flop Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 10 MHz TYP 22 12 UNIT pF
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT FOR OUTPUTS Timing Input tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Data Input tsu 1.5 V
2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V tPZL VOH Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 3V VOL + 0.3 V VOL 1.5 V 0V
2.7 V Input tPLH Output 1.5 V 1.5 V 1.5 V 0V tPHL 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
Output Control
1.5 V
[0V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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