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SN74LVC544A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS346E - MARCH 1994 - REVISED JUNE 1998
D D D D D D
EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Power Off Disables Outputs, Permitting Live Insertion Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages
DB, DW, OR PW PACKAGE (TOP VIEW)
LEBA OEBA A1 A2 A3 A4 A5 A6 A7 A8 CEAB GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC CEBA B1 B2 B3 B4 B5 B6 B7 B8 LEAB OEAB
description
The SN74LVC544A contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB places the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the inverted data present at the output of the A latches. Data flow from B to A is similar to A to B, but requires using the CEBA, LEBA, and OEBA. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN74LVC544A is characterized for operation from -40C to 85C.
FUNCTION TABLE INPUTS CEAB H L L L L LEAB X X H L L OEAB X H L L L A X X X L H OUTPUT B Z Z B0 H
L A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 1998, Texas Instruments Incorporated
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* DALLAS, TEXAS 75265
1
PRODUCT PREVIEW
This octal registered transceiver is designed for 1.65-V to 3.6-V VCC operation.
SN74LVC544A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS346E - MARCH 1994 - REVISED JUNE 1998
logic symbol
2 OEBA 23 CEBA 1 LEBA 13 OEAB 11 CEAB 14 LEAB A1 3 3 4 5 6 7 8 9 10 6D 1EN3 G1 1C5 2EN4 G2 2C6 5D 4 22 B1
A2 A3 A4 A5 A6
21 20 19 18 17 16 15
B2 B3 B4 B5 B6 B7 B8
PRODUCT PREVIEW
A7 A8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OEBA CEBA LEBA OEAB CEAB LEAB A1 2 23 1 13 11 14 3 C1 1D 22 B1
C1 1D
To Seven Other Channels
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SN74LVC544A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS346E - MARCH 1994 - REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI: (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 High or low state 3 state VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 0 0 1.65 1.5 0.65 x VCC 1.7 2 0.35 x VCC 0.7 0.8 5.5 VCC 5.5 -4 -8 -12 -24 4 8 12 24 10 ns/V mA mA V V V V MAX 3.6 UNIT V
VIH
High-level input voltage
VIL VI VO
Low-level input voltage Input voltage Output voltage
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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PRODUCT PREVIEW
SN74LVC544A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS346E - MARCH 1994 - REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 A IOH = -4 mA VOH IOH = -8 mA IOH = -12 mA 12 IOH = -24 mA IOL = 100 A VOL IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA II Ioff Control inputs VI = 0 to 5.5 V VI or VO = 5.5 V VO = 0 to 5.5 V VI = VCC or GND 3.6 V VI 5.5 V Control inputs VI = VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3.6 V 0 3.6 V IO = 0 3.6 36V 2.7 V to 3.6 V 3.3 V 3.3 V MIN VCC-0.2 1.2 1.7 2.2 2.4 2.2 0.2 0.45 0.7 0.4 0.55 5 10 10 10 10 500 A A A A A pF pF V V TYP MAX UNIT
PRODUCT PREVIEW
IOZ ICC ICC Ci
One input at VCC - 0.6 V, Other inputs at VCC or GND
Cio A or B ports VO = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. This applies in the disabled state only.
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
VCC = 1.8 V 0.15 V MIN tw Pulse duration, LEAB or LEBA low Data before LEAB or LEBA tsu Setup time Data before CEAB or CEBA Hold time Data after LEAB or LEBA Data after CEAB or CEBA High Low High Low MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V 0.3 V MIN MAX ns ns ns ns UNIT
th
4
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SN74LVC544A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS346E - MARCH 1994 - REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER FROM (INPUT) A or B LEBA or LEAB OEBA or OEAB OEBA or OEAB CEBA or CEAB CEBA or CEAB TO (OUTPUT) B or A A or B A or B A or B A or B A or B VCC = 1.8 V 0.15 V MIN MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V 0.3 V MIN MAX ns ns ns ns ns UNIT
tpd d ten tdis ten tdis
operating characteristics, TA = 25C
PARAMETER Outputs enabled Outputs disabled f = 10 MHz pF TEST CONDITIONS VCC = 1.8 V 0.15 V TYP VCC = 2.5 V 0.2 V TYP VCC = 3.3 V 0.3 V TYP UNIT
Cpd
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PRODUCT PREVIEW
Power dissipation capacitance per transceiver
SN74LVC544A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS346E - MARCH 1994 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1k S1 Open GND 1k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC Open
LOAD CIRCUIT tw Timing Input tsu VCC VCC/2 0V th VCC VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at Open (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
PRODUCT PREVIEW
Data Input
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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POST OFFICE BOX 655303
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SN74LVC544A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS346E - MARCH 1994 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC/2
VCC/2 0V tPLZ VCC
VCC/2
VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V
VCC/2
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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PRODUCT PREVIEW
VCC
SN74LVC544A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS346E - MARCH 1994 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT
tw 2.7 V
Timing Input tsu
2.7 V 1.5 V 0V th 2.7 V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 0V
Input
1.5 V
1.5 V 0V
VOLTAGE WAVEFORMS PULSE DURATION
PRODUCT PREVIEW
Data Input
Output Control (low-level enabling) tPZL
2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL
2.7 V Input tPLH 1.5 V 1.5 V 0V tPHL VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL
Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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