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CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
SCAS502C - APRIL 1995 - REVISED MAY 1996
D D D D D D D D
Generates Programmable CPU Clock Output (50 MHz, 60 MHz, or 66 MHz) Generates 33-MHz Clock for Asynchronous PCI One 14.318-MHz Reference Clock Output All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input LVTTL-Compatible Inputs and Outputs Internal Loop Filters for Phase-Lock Loops Eliminate the Need for External Components Operates at 3.3-V VCC Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages
DB OR DW PACKAGE (TOP VIEW)
X1 X2 AGND VCC 1Y1 1Y2 1Y3 1Y4 GND 1A CPUCLK SEL0
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
AVCC REFCLK OE VCC 2Y1 2Y2 2Y3 2Y4 GND 2A PCICLK SEL1
description
The CDC913 is a high-performance clock generator with integrated dual 1-to-4 buffers, which simplifies clock system design for PC motherboards. The CDC913 consists of a crystal oscillator, two phase-locked loops (PLL), and two 1-to-4 buffers. The CDC913 generates all frequencies using a single 14.318-MHz crystal. The CPUCLK output is programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 inputs. PCICLK outputs a 33-MHz clock, independent of the CPUCLK frequency. REFCLK provides a buffered copy of the 14.318-MHz reference. The oscillator and PLLs in the CDC913 are bypassed when in the TEST mode, i.e., SEL1 = SEL0 = H. When in the TEST mode, a test clock can be driven over the X1 input and buffered out from the PCICLK, CPUCLK, and REFCLK outputs. Outputs 1Yn and 2Yn are 3-state outputs and are enabled via OE. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are enabled. Since the CDC913 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, and following any changes to the SELn inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1996, Texas Instruments Incorporated
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CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
SCAS502C - APRIL 1995 - REVISED MAY 1996
Function Tables
SEL0 L H L SEL1 L L H X1 14.318 MHz 14.318 MHz 14.318 MHz TCLK CPUCLK 50 MHz 60 MHz 66 MHz TCLK PCICLK 33 MHz 33 MHz 33 MHz TCLK REFCLK 14.318 MHz 14.318 MHz 14.318 MHz TCLK
H H Test clock (TCLK) is driven over X1 when the CDC913 is in the TEST mode; i.e., SEL1 = SEL0 = H. OE H L L L L 1A X L L H H 2A X L H L H 1Yn Hi-Z L L H H 2Yn Hi-Z L H L H
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CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
SCAS502C - APRIL 1995 - REVISED MAY 1996
functional block diagram
X1
1 OSC
23
REFCLK
X2
2
14 33-MHz PLL
PCICLK
11 CPU-CLK PLL SEL0 12 Select Logic
CPUCLK
SEL1
13
OE
22
5
1Y1
6 1A 10 7
1Y2
1Y3
8
1Y4
20
2Y1
19 2A 15 18
2Y2
2Y3
17
2Y4
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3
CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
SCAS502C - APRIL 1995 - REVISED MAY 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . -0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 IOHmax Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Maximum power dissipation at TA = 55C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . 1.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL VI Supply voltage High-level input voltage Low-level input voltage Input voltage REFCLK PCICLK IOH High-level output current CPUCLK 1Yn 2Yn REFCLK PCICLK IOL Low-level output current CPUCLK 1Yn 2Yn TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. 0 0 3.135 2 0.8 VCC -12 -6 -6 -12 -12 12 6 6 12 12 70 C mA mA MAX 3.6 UNIT V V V V
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POST OFFICE BOX 655303
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CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
SCAS502C - APRIL 1995 - REVISED MAY 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VCC = 3.135 V, TEST CONDITIONS II = -18 mA IOH = -12 mA IOH = - 6 mA IOH = - 6 mA IOH = -12 mA IOH = -12 mA 12 IOL = 12 mA IOL = 6 mA VOL VCC = 3.135 V IOL = 6 mA IOL = 12 mA IOL = 12 mA II IOZ ICC Ci VCC = 3.6 V, VCC = 3.6 V, VCC = 3.6 V, 36V VI = VCC or GND VI = 3.135 V or 0 VI = 3.135 V or 0 VI = VCC or GND VO = 3 V or 0 Outputs high IO = 0 0, Outputs low Outputs disabled 6 6 MIN REFCLK PCICLK CPUCLK 1Yn 2Yn REFCLK PCICLK CPUCLK 1Yn 2Yn 2.5 2.5 2.5 2.5 25 2.5 0.4 0.4 0.4 0.4 04 0.4 1 1 TA = 25C TYP MAX -1.2 2.4 2.4 2.4 2.4 24 2.4 0.5 0.5 0.5 0.5 05 0.5 1 1 1 1 1 pF pF mA A A V V MIN TYP MAX -1.2 UNIT V
VOH
VCC = 3.135 V
Co All typical values are at VCC = 3.3 V, TA = 25_C.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
MIN Stabilization time After SEL1, SEL0 After power up MAX 5 5 UNIT ms
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable.
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5
CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
SCAS502C - APRIL 1995 - REVISED MAY 1996
switching characteristics (see Figures 1 and 2)
PARAMETER FROM (INPUT) 1A 2A 1A 2A OE OE OE OE TO (OUTPUT) 1Yn 2Yn 1Yn 2Yn 1Yn 2Yn 1Yn 2Yn 1Yn 2Yn 1Yn 2Yn 1Yn tsk(o) () tsk(p) Jitter(pk pk) (pk-pk) 2Yn Any Y 1Yn and 2Yn CPUCLK PCICLK PCICLK SEL0 = L, SEL1 = L tc(period) CPUCLK SEL0 = H, SEL1 = L SEL0 = L, SEL1 = H Duty cycle D t c cle tr tf Specifications are applicable only after the PLL stabilization time has elapsed. Rise and fall times are characterized using the load circuits shown in Figure 1. CPUCLK PCICLK 30 20 ns 16.7 15 45% 45% 55% 55% 2 2 ns ns VCC = 3.3 V, TA = 25C MIN 1.5 1.5 1.5 1.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 TYP MAX 3.5 3.5 3.5 3.5 7 7 7 7 7 7 7 7 350 350 500 1 VCC = 3.135 V to 3.6 V, TA = 0C to 70C MIN 1.2 1.2 1.2 1.2 2 2 2 2 2 2 2 2 MAX 3.8 3.8 3.8 3.8 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 350 350 500 1 250 350 ns ps s ps ns UNIT
tPLH tPHL tPZH tPZL tPHZ tPLZ
ns
ns ns ns ns
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CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
SCAS502C - APRIL 1995 - REVISED MAY 1996
PARAMETER MEASUREMENT INFORMATION
VCC From Output Under Test CL = 15 pF (see Note A) 500 S1 Open GND 500 TEST tPLH /tPHL tPLZ /tPZL tPHZ /tPZH S1 Open 2X VCC GND
LOAD CIRCUIT 3V Output Control (low-level enabling) tPZL Input 1.5 V 1.5 V 0V tPLZ 2.4 V Output Waveform 1 S1 at VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH VCC 1.5 V tPHZ VOH 0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. VOL + 0.3 V VOL Output 0.4 V tr 1.5 V 2.4 V 0.4 V tPLH 1.5 V 1.5 V 0V tPHL VOH VOL 3V
tf VOLTAGE WAVEFORMS
1.5 V
VOH - 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
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CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
SCAS502C - APRIL 1995 - REVISED MAY 1996
PARAMETER MEASUREMENT INFORMATION
1A, 2A
1Y1 tPLH1 tPHL1
1Y2 tPLH2 tPHL2
1Y3 tPLH3 tPHL3
1Y4 tPLH4 tPHL4
2Y1 tPLH5 tPHL5
2Y2 tPLH6 tPHL6
2Y3 tPLH7 tPHL7
2Y4 tPLH8 NOTE A: Output skew, tsk(o), is calculated as the greater of: The difference between the fastest and slowest of tPLHn (n = 1, 2, . . . , 8). The difference between the fastest and slowest of tPHLn (n = 1, 2, . . . , 8). Pulse skew, tsk(p), is calculated as the greater of | tPLHn - tPLHn | (n = 1, 2, . . . , 8). tPHL8
Figure 2. Waveforms for Calculation of tsk(o) and tsk(p)
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Copyright (c) 1998, Texas Instruments Incorporated

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