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| CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B - DECEMBER 1995 - REVISED OCTOBER 1996 D D D D D D D D Two Integrated PLLs Provide All Digital Video Disk (DVD) System Frequencies Two 27-MHz Reference Clock Outputs One 18.432-MHz Reference Clock Output One 33.875-MHz Reference Clock Output Output Clock Frequencies Derived From an 18.432-MHz Crystal Input 3.3-V CMOS Outputs Separate Analog Core and Output Supply Voltage Internal Loop Filters for Phase-Lock Loops Eliminate the Need for External Components DB PACKAGE (TOP VIEW) GND 1X1 1X2 VCC GND PWRDN GND VCC VCC GND GND GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FCLK1 TEST FCLK2 VCC GND NC GND FCLK3 VCC AGND AVCC FCLK4 NC - No internal connection description The CDC9171 is a high-performance clock synthesizer that generates the required clock signals needed for a DVD system. The CDC9171 generates all output frequencies from an 18.432-MHz crystal. The 18.432-MHz (FCLK1) reference clock output is buffered from the integrated oscillators. Two integrated phase-lock loops (PLL) synthesize the 27-MHz (FCLK2, FCLK3) and the 33.868-MHz (FCLK4) reference clock outputs from the 18.4320-MHz crystal. The oscillator and PLLs can be bypassed in the TEST mode. When TEST is high, input 1X1 is buffered to all outputs. All clock outputs provide low-jitter clock signals for reliable clock operation. PWRDN is used to disable the PLLs and output buffers. When low, PWRDN disables the integrated PLLs and forces all outputs to a logic-low state. Because the CDC9171 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the 1X1 input and upon activation, following the transition of PWRDN to a logic-high state. FUNCTION TABLE INPUTS PWRDN L H H H TEST X L H H 1X1 X 18.432 MHz L H FCLK1 L 18.432 MHz L H OUTPUTS FCLK(2-3) L 27 MHz L H FLCK4 L 33.868 MHz L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright (c) 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B - DECEMBER 1995 - REVISED OCTOBER 1996 functional block diagram TEST 23 24 2 3 FCLK1 (18.432 MHz) 1X1 1X2 (18.432 MHz) 6 PWRDN absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high state or power-off state, VO) . . . . . . . . -0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Maximum power dissipation at TA = 55C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. 2 AAAAA AAAAA AAAAA AAAAA 27-MHz PLL AAAAA AAAAA AAAAA AAAAA AAA AAA AAA OSC 22 FCLK2 (27 MHz) 17 FCLK3 (27 MHz) 13 33.868-MHz PLL FCLK4 (33.868 MHz) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B - DECEMBER 1995 - REVISED OCTOBER 1996 recommended operating conditions (see Note 3) MIN VCC VI VIH VIL IOH IOL Supply voltage Input voltage (PWRDN only) High-level input voltage Low-level input voltage High-level output current Low-level output current 0 3 0 2 0.8 -8 8 70 MAX 3.6 5.5 UNIT V V V V mA mA C TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II VCC = 3 V, VCC = 3 V, VCC = 3 V, VCC = 3.6 V, , VCC = 3.6 V, VI = VCC or GND VI = 3 V or 0 VO = 3 V or 0 TEST CONDITIONS II = -18 mA IOH = -8 mA IOL = 8 mA VI = VCC or GND IO = 0 Outputs active (PWRDN = H) Outputs low (PWRDN = L) 20 5 7 8 MIN 2.4 0.4 1 35 10 TA = 25C TYP MAX -1.2 2.4 0.4 1 35 mA 10 pF pF MIN MAX -1.2 UNIT V V V A ICC Ci Co Except for crystal input (1X1) timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN Stabilization time After PWRDN After power up MAX 5 5 UNIT ms Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at 1X1. switching characteristics over recommended free-air temperature range for 3-V outputs (see Figure 1) PARAMETER FCLK1 All other outputs Any output Any output (CL = 20 pF) 45% VCC = 3.3 V, TA = 25C MIN Jitter Duty cycle tr MAX VCC = 3 V to 3.6 V, TA = 0C to 70C MIN MAX 200 250 55% 2.5 2.5 ns ns ps UNIT tf Any output (CL = 20 pF) Specifications are applicable only after the PLL stabilization time has elapsed. Rise and fall times are characterized using the test circuit shown in Figure 1. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B - DECEMBER 1995 - REVISED OCTOBER 1996 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 20 pF (see Note A) LOAD CIRCUIT Duty Cycle 2.4 V 1.5 V 0.4 V tr tf NOTES: A. CL inlcudes probe and jig capacitance. B. The outputs are measured one at a time with one transition per measurement. Figure 1. Voltage Waveform and Load Circuit 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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