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SN74SSTL16837 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCBS675F - SEPTEMBER 1996 - REVISED MAY 1998
D D D D D D
Member of the Texas Instruments WidebusTM Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class II Specifications Latch-Up Performance Exceeds 250 mA Per JESD 17 Packaged in Plastic Thin Shrink Small-Outline Package
DGG PACKAGE (TOP VIEW)
description
This 20-bit universal bus driver is designed for 3-V to 3.6-V VCC operation and SSTL_3 or LVTTL I/O levels. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when latch enable (LE) is high. The A data is latched if LE is low and clock (CLK) is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74SSTL16837 is characterized operation from 0C to 70C. for
Y1 Y2 GND Y3 Y4 VDDQ Y5 Y6 GND Y7 Y8 VDDQ Y9 Y10 GND OE VREF GND Y11 Y12 VDDQ Y13 Y14 GND Y15 Y16 VDDQ Y17 Y18 GND Y19 Y20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
A1 A2 GND A3 A4 VCC A5 A6 GND A7 A8 VCC A9 A10 GND CLK LE GND A11 A12 VCC A13 A14 GND A15 A16 VCC A17 A18 GND A19 A20
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1998, Texas Instruments Incorporated
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1
SN74SSTL16837 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCBS675F - SEPTEMBER 1996 - REVISED MAY 1998
FUNCTION TABLE INPUTS OE L L L L L L LE H H L L L L CLK X X H L A H L H L X X OUTPUT Y H L H L Y0 Y0
H X X X Z Output level before the indicated steady-state input conditions were established, provided that CLK was high before LE went low Output level before the indicated steady-state input conditions were established
logic diagram (positive logic)
16 OE 49 CLK 48 LE 64
LE C1 1 Y1
A1
1D
To 19 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51.
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POST OFFICE BOX 655303
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SN74SSTL16837 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCBS675F - SEPTEMBER 1996 - REVISED MAY 1998
recommended operating conditions (see Note 4)
MIN VCC VDDQ VREF VTT VI VIH VIL VIH VIL IOH IOL TA Supply voltage Output supply voltage Reference voltage (VREF = 0.45 x VDDQ) Termination voltage Input voltage AC high-level input voltage AC low-level input voltage DC high-level input voltage DC low-level input voltage High-level output current Low-level output current Operating free-air temperature 0 All inputs All inputs All inputs All inputs VREF+200mV VREF-200mV - 20 20 70 VDDQ 3 1.3 VREF-50mV 0 VREF+400mV VREF-400mV 1.5 VREF NOM MAX 3.6 3.6 1.7 VREF+50mV VCC UNIT V V V V V V V V V mA
_C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH II = -18 mA IOH = -100 A IOH = -16 mA IOH = -20 mA IOL = 100 A IOL = 16 mA IOL = 20 mA VI = 2.1 V or 0.9 V VI = 3.6 V or 0 VI = 2.1 V or 0.9 V VI = 3.6 V or 0 VI = 2.1 V or 0.9 V VI = 3.6 V or 0 VREF = 1.3 V or 1.7 V VO = 0.9 V or 2.1 V VO = 0 or 3.6 V VI = 2.1 V or 0.9 V VI = 3.6 V or 0 Control inputs A port VI = 2 1 V or 0 9 V 2.1 0.9 IO = 0 TEST CONDITIONS VCC 3V 3 V to 3.6 V 3V 3 V to 3.6 V 3V VREF = 1 3 V or 1 7 V 1.3 1.7 VREF = 1 3 V or 1 7 V 1.3 1.7 VREF = 1 3 V or 1 7 V 1.3 1.7 3.6 36V 36V 3.6 3.6 36V 3.6 V 36V 3.6 3.6 36V 3.3 33V 3.3 V 2.5 2 3 MIN TYP MAX -1.2 VCC-0.2 2.2 2.1 0.2 0.5 0.55 40 1.2 5 5 150 4 150 10 10 90 90 mA A A mA pF pF A A mA V UNIT V V
VOL
LE
II
Data inp ts OE inputs, CLK VREF
IOZ ICC Ci
Co Y port VO = 2.1 V or 0.9 V All typical values are at VCC = 3.3 V, TA = 25C.
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3
SN74SSTL16837 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCBS675F - SEPTEMBER 1996 - REVISED MAY 1998
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V 0.3 V MIN fclock tw Clock frequency Pulse duration LE high CLK high or low A before CLK tsu Setup time A before LE A after CLK A after LE LE low CLK high CLK low LE low 2.5 2.5 1.5 1.5 2 1 1 ns ns MAX 200 MHz ns UNIT
th
Hold time
switching characteristics over recommended operating free-air temperature range, Class I, VREF = VTT = VDDQ X 0.45 and CL = 10 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax A tpd ten tdis LE CLK OE OE Y Y Y FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN 200 1.1 1.5 1 1.8 1.8 4 4.1 3 5.5 6 ns ns ns MAX MHz UNIT
switching characteristics over recommended operating free-air temperature range, Class II, VREF = VTT = VDDQ X 0.45 and CL = 30 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax A tpd ten tdis LE CLK OE OE Y Y Y FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN 200 1.1 1.5 1 1.8 1.8 4.2 4.3 3.2 5.5 6 ns ns ns MAX MHz UNIT
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74SSTL16837 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCBS675F - SEPTEMBER 1996 - REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
VTT Test Point 25 = SSTL_3 Class II 50 = SSTL_3 Class I
25
CL = 10 pF or 30 pF (see Note A)
LOAD CIRCUIT
Timing Input tsu Data Input VREF
VREF
VIH VIL
tw VIH Input VREF VREF VIL
th VIH VREF VIL Output Control tPZL VIH VIL VOLTAGE WAVEFORMS PULSE DURATION
VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
VREF
VREF
VIH VIL
Input tPLH
VREF
VREF tPHL VREF
Output Waveform 1 (see Note B) tPZH
tPLZ VIL VIL tPHZ
VTT VOL
Output
VOH VREF VOL
Output Waveform 2 (see Note B)
VIH
VIH
VOH VTT
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VREF = 0.45 VDDQ VIH = VREF+400mV (AC voltage levels) VIL = VREF-400mV (AC voltage levels)
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 1.25 ns/V, tf 1.25 ns/V. D. The outputs are measured one at a time with one transition per measurement. E. VTT = VREF = VDDQ X 0.45 F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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