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| SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004J - NOVEMBER 1992 - REVISED MAY 2000 D D D D Functionally Equivalent to QS3384 and QS3L384 5- Switch Connection Between Two Ports TTL-Compatible Input Levels Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB, DBQ), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) description The SN74CBT3384A provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. 1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE The device is organized as two 5-bit switches with separate output-enable (OE) inputs. When OE is low, the switch is on, and port A is connected to port B. When OE is high, the switch is open, and a high-impedance state exists between the two ports. The SN74CBT3384A is characterized for operation from -40C to 85C. FUNCTION TABLE (each 5-bit bus switch) INPUTS 1OE L L H H 2OE L H L H INPUTS/OUTPUTS 1B1-1B5 1A1-1A5 1A1-1A5 Z Z 2B1-2B5 2A1-2A5 Z 2A1-2A5 Z logic diagram (positive logic) 1A1 3 2 1B1 1A5 1OE 11 1 10 1B5 2A1 14 15 2B1 2A5 2OE 22 13 23 2B5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004J - NOVEMBER 1992 - REVISED MAY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63C/W DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature -40 4 2 0.8 85 MAX 5.5 UNIT V V V C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II ICC ICC Ci Cio(OFF) Control inputs Control inputs VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V ron VCC = 4.5 V TEST CONDITIONS II = -18 mA VI = 5.5 V or GND IO = 0, One input at 3.4 V, OE = VCC VI = 2.4 V, VI = 0 II = 15 mA II = 64 mA II = 30 mA VI = VCC or GND Other inputs at VCC or GND 4 4.5 14 5 5 20 7 7 MIN TYP MAX -1.2 1 3 2.5 UNIT V A A mA pF pF VI = 2.4 V, II = 15 mA 10 15 All typical values are at VCC = 5 V (unless otherwise noted), TA = 25C. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004J - NOVEMBER 1992 - REVISED MAY 2000 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tdis FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B VCC = 4 V MIN MAX 0.35 6.2 5.5 1.9 2.1 VCC = 5 V 0.5 V MIN MAX 0.25 5.7 5.2 ns ns ns UNIT The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL Output Waveform 1 S1 at 7 V (see Note B) tPZH TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open 3V 1.5 V 1.5 V 0V tPLZ 3.5 V 1.5 V tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL LOAD CIRCUIT 3V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) 1.5 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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