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SN54CBTD3384, SN74CBTD3384 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING
SCDS025L - MAY 1995 - REVISED MAY 2000
D D D D
5- Switch Connection Between Two Ports TTL-Compatible Input Levels Designed to Be Used in Level-Shifting Applications Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB, DBQ), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Package, Ceramic DIPs (JT), and Ceramic Chip Carriers (FK)
SN54CBTD3384 . . . JT OR W PACKAGE SN74CBTD3384 . . . DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW)
description
The 'CBTD3384 devices provide ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switches allows connections to be made without adding propagation delay. A diode to VCC is integrated on the die to allow for level shifting between 5-V inputs and 3.3-V outputs. These devices are organized as two 5-bit switches with separate output-enable (OE) inputs. When OE is low, the switch is on, and port A is connected to port B. When OE is high, the switch is open, and a high-impedance state exists between the two ports. The SN54CBTD3384 is characterized for operation over the full military temperature range from -55C to 125C. The SN74CBTD3384 is characterized for operation from -40C to 85C.
1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE
SN54CBTD3384 . . . FK PACKAGE (TOP VIEW)
1A1 1B1 1OE NC V CC 1A2 1B2 1B3 NC 1A3 1A4 1B4
4
5 6 7 8 9
3 2 1 28 27 26
2B5 2A5
25 24 23 22 21 20
10
11 19 12 13 14 15 16 17 18
2A4 2B4 2B3 NC 2A3 2A2 2B2
NC - No internal connection FUNCTION TABLE (each 5-bit bus switch) INPUTS 1OE L L H H 2OE L H L H INPUTS/OUTPUTS 1B1-1B5 1A1-1A5 1A1-1A5 Z Z 2B1-2B5 2A1-2A5 Z 2A1-2A5 Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1B5 1A5 GND NC 2OE 2A1 2B1
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SN54CBTD3384, SN74CBTD3384 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING
SCDS025L - MAY 1995 - REVISED MAY 2000
logic diagram (positive logic)
1A1 3 2 1B1
11 1A5 1OE 1
10
1B5
2A1
14
15
2B1
22 2A5 2OE 13
23
2B5
Pin numbers shown are for the DB, DBQ, DGV, DW, JT, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63C/W DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54CBTD3384 MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature -55 4.5 2 0.8 125 -40 MAX 5.5 SN74CBTD3384 MIN 4.5 2 0.8 85 MAX 5.5 UNIT V V V C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54CBTD3384, SN74CBTD3384 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING
SCDS025L - MAY 1995 - REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH II ICC ICC Ci Control inputs Control inputs VCC = 4.5 V, See Figure 2 VCC = 5.5 V, VCC = 5.5 V, TEST CONDITIONS II = -18 mA VI = 5.5 V or GND IO = 0, VI = VCC or GND MIN SN54CBTD3384 TYP MAX -1.2 1 1.5 2.5 3 OE = VCC VI = 0 II = 64 mA II = 30 mA 3.5 5 5 3 3.5 5 5 7 7 MIN SN74CBTD3384 TYP MAX -1.2 1 1.5 2.5 UNIT V A mA mA pF pF
VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0, VCC = 4.5 V
Cio(OFF) ron
VI = 2.4 V, II = 15 mA 35 35 50 Typical values are at VCC = 5 V, TA = 25C. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B 2.2 1.5 SN54CBTD3384 MIN MAX 0.25 9.7 8.6 2.3 1.7 SN74CBTD3384 MIN MAX 0.25 7 5.3 UNIT ns ns ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54CBTD3384, SN74CBTD3384 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING
SCDS025L - MAY 1995 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL 3V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) Output Waveform 1 S1 at 7 V (see Note B) tPZH 1.5 V TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
3V 1.5 V 1.5 V 0V tPLZ 3.5 V 1.5 V VOL + 0.3 V tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54CBTD3384, SN74CBTD3384 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING
SCDS025L - MAY 1995 - REVISED MAY 2000
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
4 TA = 85C 3.75 VOH - Output Voltage High - V 3.5 3.25 3 2.75 2.5 2.25 2 1.75 1.5 4.5 100 A VOH - Output Voltage High - V 6 mA 12 mA 24 mA 4 3.75 3.5 3.25 3 2.75 2.5 2.25 2 1.75 4.75 5 5.25 5.5 5.75 1.5 4.5 4.75 5 5.25 5.5 5.75 100 A 6 mA 12 mA 24 mA
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
TA = 25C
VCC - Supply Voltage - V
VCC - Supply Voltage - V
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
4 3.75 VOH - Output Voltage High - V 3.5 3.25 3 2.75 2.5 2.25 2 1.75 1.5 4.5 TA = 0C
100 A 6 mA 12 mA 24 mA
4.75 5 5.25 5.5 VCC - Supply Voltage - V
5.75
Figure 2. VOH Values
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
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Copyright (c) 2000, Texas Instruments Incorporated

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