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SN74CBTLV16210 LOW-VOLTAGE 20-BIT FET BUS SWITCH
SCDS042F - DECEMBER 1997 - REVISED MAY 2000
D D D
5- Switch Connection Between Two Ports Isolation Under Power-Off Conditions Package Options Include Plastic Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV), and Shrink Small-Outline (DL) Packages
For tape and reel order entry: The DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.
DGG, DGV, OR DL PACKAGE (TOP VIEW)
NOTE:
description
The SN74CBTLV16210 provides 20 bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as dual 10-bit bus switches with separate output-enable (OE) inputs. It can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE is low, the associated 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74CBTLV16210 is characterized for operation from -40C to 85C.
FUNCTION TABLE (each 10-bit bus switch) INPUT OE L H FUNCTION A port = B port Disconnect
NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10
NC - No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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1
SN74CBTLV16210 LOW-VOLTAGE 20-BIT FET BUS SWITCH
SCDS042F - DECEMBER 1997 - REVISED MAY 2000
logic diagram (positive logic)
2 1A1 SW 46 1B1
12 1A10 SW
36 1B10
48 1OE
13 2A1 SW
35
2B1
24 2A10 SW
25 2B10
47 2OE
simplified schematic, each FET switch
A
B
(OE)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
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POST OFFICE BOX 655303
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SN74CBTLV16210 LOW-VOLTAGE 20-BIT FET BUS SWITCH
SCDS042F - DECEMBER 1997 - REVISED MAY 2000
recommended operating conditions (see Note 3)
MIN VCC VIH VIL Supply voltage High level control input voltage High-level Low-level Low level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2.3 1.7 2 0.7 0.8 MAX 3.6 UNIT V V V
TA Operating free-air temperature -40 85 C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II Ioff ICC ICC Ci Cio(OFF) Control inputs Control inputs VCC = 3 V, VCC = 3.6 V, VCC = 0, VCC = 3.6 V, VCC = 3.6 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 2 3 V 2.3 V, TYP at VCC = 2.5 V ron VCC = 3 V TEST CONDITIONS II = -18 mA VI = VCC or GND VI or VO= 0 to 3.6 V IO = 0, VI = VCC or GND One input at 3 V, Other inputs at VCC or GND 4.5 OE = VCC VI = 0 VI = 1.7 V, VI = 0 II = 64 mA II = 24 mA II = 15 mA II = 64 mA II = 24 mA 6.5 5 5 27 5 5 8 8 40 7 7 MIN TYP MAX -1.2 1 10 10 300 UNIT V A A A A pF pF
VI = 2.4 V, II = 15 mA 10 15 All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25C. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 2)
PARAMETER tpd ten FROM (INPUT) A or B OE TO (OUTPUT) B or A A or B 1 VCC = 2.5 V 0.2 V MIN MAX 0.15 6.8 1 VCC = 3.3 V 0.3 V MIN MAX 0.25 6 ns ns UNIT
tdis OE A or B 1 7.3 1 7.4 ns The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
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3
SN74CBTLV16210 LOW-VOLTAGE 20-BIT FET BUS SWITCH
SCDS042F - DECEMBER 1997 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
LOAD CIRCUIT
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74CBTLV16210 LOW-VOLTAGE 20-BIT FET BUS SWITCH
SCDS042F - DECEMBER 1997 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL 3V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL Output Waveform 1 S1 at 6 V (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B) 1.5 V TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
3V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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5
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Copyright (c) 2000, Texas Instruments Incorporated

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