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| SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044F - DECEMBER 1997 - REVISED MAY 2000 D D D D D D 4- Switch Connection Between Two Ports Isolation Under Power-Off Conditions Break-Before-Make Feature ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV), and Shrink Small-Outline (DL) Packages For tape and reel order entry: The DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR. DGG, DGV, OR DL PACKAGE (TOP VIEW) NOTE: description The SN74CBTLV16212 provides 24 bits of high-speed bus switching or exchanging. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device operates as a 24-bit bus switch or a 12-bit bus exchanger, which provides data exchanging between the four signal ports via the data-select (S0, S1, S2) terminals. The SN74CBTLV16212 is specified by the break-before-make feature to have no through current when switching between B ports. The SN74CBTLV16212 is characterized for operation from -40C to 85C. S0 1A1 1A2 2A1 2A2 3A1 3A2 GND 4A1 4A2 5A1 5A2 6A1 6A2 7A1 7A2 VCC 8A1 GND 8A2 9A1 9A2 10A1 10A2 11A1 11A2 12A1 12A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 S1 S2 1B1 1B2 2B1 2B2 3B1 GND 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 GND 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044F - DECEMBER 1997 - REVISED MAY 2000 FUNCTION TABLE INPUTS S2 L L L L H H H H S1 L L H H L L H H S0 L H L H L H L H INPUTS/OUTPUTS A1 Z B1 B2 Z Z Z B1 B2 A2 Z Z Z B1 B2 Z B2 B1 FUNCTION Disconnect A1 port = B1 port A1 port = B2 port A2 port = B1 port A2 port = B2 port Disconnect A1 port = B1 port A2 port = B2 port A1 port = B2 port A2 port = B1 port 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044F - DECEMBER 1997 - REVISED MAY 2000 logic diagram (positive logic) 1A1 2 SW 54 1B1 SW SW 3 1A2 SW 53 1B2 12A1 27 SW 30 12B1 SW SW 28 12A2 SW 29 12B2 1 S0 56 S1 55 S2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044F - DECEMBER 1997 - REVISED MAY 2000 simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) MIN VCC VIH VIL Supply voltage High level control input voltage High-level Low-level Low level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2.3 1.7 2 0.7 0.8 MAX 3.6 UNIT V V V TA Operating free-air temperature -40 85 C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044F - DECEMBER 1997 - REVISED MAY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II Ioff ICC ICC Ci Control inputs Control inputs VCC = 3 V, VCC = 3.6 V, VCC = 0, VCC = 3.6 V, VCC = 3.6 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 2.3 V, 23V TYP at VCC = 2.5 V ron VCC = 3 V TEST CONDITIONS II = -18 mA VI = VCC or GND VI or VO= 0 to 3.6 V IO = 0, One input at 3 V, VI = VCC or GND Other inputs at VCC or GND 5 OE = VCC VI = 0 VI = 1.7 V, VI = 0 II = 64 mA II = 24 mA II = 15 mA II = 64 mA II = 24 mA 8 5 5 27 5 5 8 8 40 7 7 MIN TYP MAX -1.2 1 10 10 300 UNIT V A A A A pF pF Cio(OFF) VI = 2.4 V, II = 15 mA 10 15 All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25C. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 2) PARAMETER tpd tpd ten FROM (INPUT) A or B S S TO (OUTPUT) B or A B or A A or B 3 3 VCC = 2.5 V 0.2 V MIN MAX 0.15 11.1 10.9 3 3 VCC = 3.3 V 0.3 V MIN MAX 0.25 8.8 8.6 ns ns ns UNIT tdis S A or B 1 8.7 2 8.8 ns The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044F - DECEMBER 1997 - REVISED MAY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V 2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND LOAD CIRCUIT Output Control tPZL VCC Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VOH Output Waveform 2 S1 at GND (see Note B) VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Input VCC/2 tPLH VCC/2 0V tPHL Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL VCC/2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044F - DECEMBER 1997 - REVISED MAY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V 6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND 3V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL LOAD CIRCUIT 3V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL 1.5 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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