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SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
D D D D D D D D D D D
16 17 18 19 20 21 22 23 24 25 26 27 28
41 40 39 38 37 36 35 34 33 32 31 30 29
description
The 'ALVTH16543 devices are 16-bit registered transceivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA), output-enable (OEAB or OEBA), and chip-enable (CEAB or CEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but uses the CEBA, LEBA, and OEBA inputs. When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 1999, Texas Instruments Incorporated
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PRODUCT PREVIEW
State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus TM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C High-Drive (-24/24 mA at 2.5-V and -32/64 mA at 3.3-V VCC) Power Off Disables Outputs, Permitting Live Insertion High-Impedance State During Power Up and Power Down Prevents Driver Conflict Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16543 . . . WD PACKAGE SN74ALVTH16543 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW)
1OEAB 1LEAB 1CEAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2CEAB 2LEAB 2OEAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
1OEBA 1LEBA 1CEBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2CEBA 2LEBA 2OEBA
SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH16543 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ALVTH16543 is characterized for operation from -40C to 85C.
FUNCTION TABLE (each 8-bit section) INPUTS CEAB H X L L L LEAB X X H L L OEAB X H L L L A X X X L H OUTPUT B Z Z B0 L
PRODUCT PREVIEW
H A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established
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SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
logic diagram (positive logic)
1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 1A1 56 54 55 1 3 2 5 C1 1D 52 1B1
C1 1D
To Seven Other Channels 29 31 30 28 26 27 15 C1 1D 42 2B1
2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 2A1
C1 1D
To Seven Other Channels
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PRODUCT PREVIEW
SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO (see Note 1) . . . . . . . . . -0.5 V to 7 V Output current in the low state, IO: SN54ALVTH16543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH16543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH16543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -48 mA SN74ALVTH16543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
PRODUCT PREVIEW
recommended operating conditions, VCC = 2.5 V 0.2 V (see Note 3)
SN54ALVTH16543 MIN VCC VIH VIL VI IOH IOL t/v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1 kHz Input transition rise or fall rate Power-up ramp rate Operating free-air temperature Outputs enabled 200 -55 125 0 VCC 2.3 1.7 0.7 5.5 -6 6 18 10 200 -40 85 0 VCC TYP MAX 2.7 SN74ALVTH16543 MIN 2.3 1.7 0.7 5.5 -8 8 24 10 TYP MAX 2.7 UNIT V V V V mA mA ns/V s/V C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
recommended operating conditions, VCC = 3.3 V 0.3 V (see Note 3)
SN54ALVTH16543 MIN VCC VIH VIL VI IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1 kHz Input transition rise or fall rate Outputs enabled 0 VCC 3 2 0.8 5.5 -24 24 48 10 0 VCC TYP MAX 3.6 SN74ALVTH16543 MIN 3 2 0.8 5.5 -32 32 64 10 TYP MAX 3.6 UNIT V V V V mA mA ns/V
t/VCC Power-up ramp rate 200 200 s/V TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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PRODUCT PREVIEW
SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted)
PARAMETER VIK VOH TEST CONDITIONS VCC = 2.3 V, VCC = 2.3 V to 2.7 V, VCC = 2 3 V 2.3 VCC = 2.3 V to 2.7 V, VOL II = -18 mA IOH = -100 A IOH = -6 mA IOH = -8 mA IOL = 100 A IOL = 6 mA IOL = 8 mA IOL = 18 mA IOL = 24 mA IO = 1 mA, VI = VCC or GND VI = VCC or GND VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.7 V VI = 1.7 V VI = 0 to VCC VI = 0 to VCC 300 -300 125 100 0.04 2.6 0.04 0.1 4.5 0.1 0.04 2.6 0.04 115 -10 300 -300 125 100 0.1 4.5 0.1 pF mA SN54ALVTH16543 MIN TYP MAX -1.2 VCC-0.2 1.8 0.2 0.4 0.4 0.5 0.5 0.55 1 10 10 1 -5 115 -10 0.55 1 10 10 1 -5 100 A A A A A A A A V V VCC-0.2 V 1.8 0.2 SN74ALVTH16543 MIN TYP MAX -1.2 UNIT V
VCC = 2 3 V 2.3
VRST Control inputs
VCC = 2.7 V VCC = 2.7 V, VCC = 0 or 2.7 V, VCC = 2.7 V VCC = 0, VCC = 2.3 V, VCC = 2.3 V, VCC = 2.7 V, VCC = 2.7 V, VCC = 2.3 V,
PRODUCT PREVIEW
II A or B ports Ioff IBHL IBHH IBHLO# IBHHO|| IEXk IOZ(PU/PD)h
VO = 5.5 V VCC 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don't care VCC = 2.7 V, IO = 0, VI = VCC or GND VCC = 2.5 V, VCC = 2.5 V, Outputs high Outputs low Outputs disabled VI = 2.5 V or 0 VO = 2.5 V or 0
ICC Ci Cio
pF All typical values are at VCC = 2.5 V, TA = 25C. Data must not be loaded into the flip-flops/latches after applying power. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. # An external driver must source at least IBHLO to switch this node from low to high. || An external driver must sink at least IBHHO to switch this node from high to low. kCurrent into an output in the high state when VO > VCC hHigh-impedance state during power up or power down
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SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted)
PARAMETER VIK VOH TEST CONDITIONS VCC = 3 V, VCC = 3 V to 3.6 V, VCC = 3 V VCC = 3 V to 3.6 V, II = -18 mA IOH = -100 A IOH = -24 mA IOH = -32 mA IOL = 100 A IOL = 16 mA IOL = 24 mA IOL = 32 mA IOL = 48 mA IOL = 64 mA VRST Control inputs II A or B ports Ioff IBHL IBHH IBHLO# IBHHO|| IEXk IOZ(PU/PD)h VCC = 3.6 V VCC = 0, VCC = 3 V, VCC = 3 V, VCC = 3.6 V, VCC = 3.6 V, VCC = 3 V, VCC = 3.6 V VCC = 3.6 V, VCC = 0 or 3.6 V, IO = 1 mA, VI = VCC or GND VI = VCC or GND VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to VCC VI = 0 to VCC 75 -75 500 -500 125 100 0.07 3.6 0.07 0.1 5 0.1 0.4 0.07 3.6 0.07 SN54ALVTH16543 MIN TYP MAX -1.2 VCC-0.2 2 0.2 0.5 0.5 0.55 0.55 0.55 1 10 10 1 -5 75 -75 500 -500 125 100 0.1 5 0.1 0.4 mA pF mA 0.55 1 10 10 1 -5 100 A A A A A A A A V VCC-0.2 V 2 0.2 0.4 V SN74ALVTH16543 MIN TYP MAX -1.2 UNIT V
VOL
VCC = 3 V
VO = 5.5 V VCC 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don't care VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high Outputs low Outputs disabled
ICC
ICC Ci
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VCC = 3.3 V, VCC = 3.3 V, VI = 3.3 V or 0 VO = 3.3 V or 0
Cio pF All typical values are at VCC = 3.3 V, TA = 25C. Data must not be loaded into the flip-flops/latches after applying power. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. # An external driver must source at least IBHLO to switch this node from low to high. || An external driver must sink at least IBHHO to switch this node from high to low. kCurrent into an output in the high state when VO > VCC hHigh-impedance state during power up or power down This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
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PRODUCT PREVIEW
SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted)
SN54ALVTH16543 MIN tw Pulse duration, LEAB or LEBA low Data high A or B before LEAB or LEBA tsu Setup time A or B before CEAB or CEBA A or B after LEAB or LEBA th Hold time A or B after CEAB or CEBA Data low Data high Data low Data high Data low Data high Data low ns ns MAX SN74ALVTH16543 MIN MAX UNIT ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted)
PRODUCT PREVIEW
SN54ALVTH16543 MIN tw Pulse duration, LEAB or LEBA low Data high A or B before LEAB or LEBA tsu Setup time A or B before CEAB or CEBA A or B after LEAB or LEBA th Hold time A or B after CEAB or CEBA Data low Data high Data low Data high Data low Data high Data low MAX
SN74ALVTH16543 MIN MAX
UNIT ns
ns
ns
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SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
switching characteristics over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B TO (OUTPUT) B or A A or B A or B A or B A or B A or B SN54ALVTH16543 MIN MAX SN74ALVTH16543 MIN MAX UNIT ns ns ns ns ns ns
LE OE OE CE CE
switching characteristics over recommended operating free-air temperature range, CL = 50 pF, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B TO (OUTPUT) B or A A or B A or B A or B A or B A or B SN54ALVTH16543 MIN MAX SN74ALVTH16543 MIN MAX UNIT ns ns ns ns ns ns
LE OE OE CE CE
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PRODUCT PREVIEW
SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu VCC VCC/2 0V th VCC VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
PRODUCT PREVIEW
Data Input
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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SN54ALVTH16543, SN74ALVTH16543 2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES073C - JUNE 1996 - REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT tw 3V Timing Input tsu Data Input 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Waveform 1 S1 at 6 V (see Note B) tPZH VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) 3V 1.5 V 0V th 3V 1.5 V 0V Output Control 1.5 V 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH Output tPHL tPLZ 3V 1.5 V VOL + 0.3 V tPHZ VOH VOH - 0.3 V 0V VOL 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION
1.5 V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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PRODUCT PREVIEW
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