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SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
SCES085F - AUGUST 1996 - REVISED JUNE 1999
D D D D D D
Member of the Texas Instruments Widebus TM Family EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DGG), Thin Shrink Small-Outline (DL), and Thin Very Small-Outline (DGV) Packages
DGG, DGV, OR DL PACKAGE (TOP VIEW)
NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.
description
This 1-bit to 4-bit address driver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH162344 is used in applications in which four separate memory locations must be addressed by a single address. The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, the output enable (OE) inputs should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE1 1B1 1B2 GND 1B3 1B4 VCC 1A 2B1 2B2 GND 2B3 2B4 2A 3A 3B1 3B2 GND 3B3 3B4 4A VCC 4B1 4B2 GND 4B3 4B4 OE2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
OE4 8B1 8B2 GND 8B3 8B4 VCC 8A 7B1 7B2 GND 7B3 7B4 7A 6A 6B1 6B2 GND 6B3 6B4 5A VCC 5B1 5B2 GND 5B3 5B4 OE3
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162344 is characterized for operation from -40C to 85C.
A-TO-B FUNCTION TABLE INPUTS OE L L H A H L X OUTPUT Bn H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
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1
SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
SCES085F - AUGUST 1996 - REVISED JUNE 1999
logic diagram (positive logic)
OE4 OE3 OE2 OE1 56 29 28 1
2
1B1
34
5B1
3 1A 8 5
1B2 5A 1B3 36
33
5B2
31
5B3
6
1B4
30
5B4
9
2B1
41
6B1
10 2A 14 12
2B2 6A 2B3 42
40
6B2
38
6B3
13
2B4
37
6B4
16
3B1
48
7B1
17 3A 15 19
3B2 7A 3B3 43
47
7B2
45
7B3
20
3B4
44
7B4
23
4B1
55
8B1
24 4A 21 26
4B2 8A 4B3 49
54
8B2
52
8B3
27
4B4
51
8B4
2
POST OFFICE BOX 655303
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SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
SCES085F - AUGUST 1996 - REVISED JUNE 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN VCC VIH Supply voltage High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO Low-level input voltage Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 1.65 0.65 x VCC 1.7 2 0.35 x VCC 0.7 0.8 VCC VCC -2 -6 -8 -12 2 6 8 12 10 ns/V mA mA V V V V MAX 3.6 UNIT V
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
SCES085F - AUGUST 1996 - REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 A IOH = -2 mA IOH = -4 mA VOH IOH = -6 mA 6 IOH = -8 mA IOH = -12 mA IOL = 100 A IOL = 2 mA IOL = 4 mA VOL IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.58 V VI = 1.07 V VI = 0.7 V II(hold) ( ) VI = 1.7 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V IOZ ICC ICC Ci Control inputs Data inputs VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, VI = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 3V 2.7 V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 3V 2.7 V 3V 3.6 V 1.65 V 1.65 V 2.3 V 2.3 V 3V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 33V 3.3 2.5 3.5 25 -25 45 -45 75 -75 500 10 40 750 A A A pF A MIN TYP MAX UNIT VCC-0.2 1.2 1.9 1.7 2.4 2 2 0.2 0.45 0.4 0.55 0.55 0.6 0.8 5 A V V
Co Outputs VO = VCC or GND 3.3 V 4 pF All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER tpd ten tdis tsk(o) tsk(o)# This information was not available at the time of publication. Skew between outputs of the same bank and same package (same transition) # Skew between outputs of all banks of same package (A1-A8 tied together) FROM (INPUT) A OE OE TO (OUTPUT) B B B VCC = 1.8 V TYP VCC = 2.5 V 0.2 V MIN 1 1 1 MAX 4.9 6.4 5.4 VCC = 2.7 V MIN MAX 5.1 6.6 4.7 VCC = 3.3 V 0.3 V MIN 1.4 1.2 1.2 MAX 4.4 5.7 4.5 0.35 0.5 ns ns ns ns ns UNIT
4
POST OFFICE BOX 655303
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SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
SCES085F - AUGUST 1996 - REVISED JUNE 1999
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 0 0, f = 10 MHz VCC = 1.8 V TYP VCC = 2.5 V TYP 68 12 VCC = 3.3 V TYP 82 14 UNIT pF
This information was not available at the time of publication.
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k S1 Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
SCES085F - AUGUST 1996 - REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
SCES085F - AUGUST 1996 - REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
tw LOAD CIRCUIT 2.7 V Timing Input tsu Data Input 1.5 V 2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL Output Waveform 1 S1 at 6 V (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B) 2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V tPHZ VOH 1.5 V VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL VOLTAGE WAVEFORMS PULSE DURATION Input 1.5 V 1.5 V 0V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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Copyright (c) 1999, Texas Instruments Incorporated

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