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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
D D D D
Member of the Texas Instruments Widebus TM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process DOCTM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of 24 mA at 2.5-V VCC
D D D D
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.
3.2 2.8 VOL - Output Voltage - V 2.4 2.0 1.6 VCC = 2.5 V 1.2 VCC = 1.8 V 0.8 0.4 0 17 34 51 68 85 102 119 IOL - Output Current - mA 136 153 170 VCC = 3.3 V TA = 25C Process = Nominal - Output Voltage - V TA = 25C Process = Nominal
2.8 2.4 2.0 1.6 1.2 0.8
V
OH
VCC = 3.3 V 0.4
VCC = 2.5 V VCC = 1.8 V -32 -16 0
-160 -144 -128 -112 -96 -80 -64 -48 IOH - Output Current - mA
Figure 1. Output Voltage vs Output Current This 12-bit to 24-bit registered bus exchanger is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high-speed microprocessors.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DOC, EPIC, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
description (continued)
Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the period during which the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active-low output enables (OEA, OEB1, OEB2). To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16269 is characterized for operation from -40C to 85C.
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
terminal assignments
DGG OR DGV PACKAGE (TOP VIEW)
OEA OEB1 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 NC SEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
OEB2 CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK
NC - No internal connection
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
Function Tables
OUTPUT ENABLE INPUTS CLK OEA H H L L OEB H L H L OUTPUTS A Z Z Active Active 1B, 2B Z Active Z Active
A-TO-B STORAGE (OEB = L) INPUTS CLKENA1 H L L X X CLKENA2 H X X L L CLK X A X L H L H OUTPUTS 1B 1B0 L H X 2B 2B0 X X L H
X Output level before the indicated steady-state input conditions were established B-TO-A STORAGE (OEA = L) INPUTS CLK X X SEL H L H H L 1B X X L H X 2B X X X X L OUTPUT A A0 A0 L H L
L X H H Output level before the indicated steady-state input conditions were established
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
logic diagram (positive logic)
CLK OEB1 29 2 C1 1D C1 OEB2 CLKENA1 CLKENA2 SEL 56 30 55 C1 28 1 1D 1D
OEA
1D 1 of 12 Channels
C1
G1 A1 8 C1 1 1D 1 23 1B1
CE C1 1D 6 2B1
CE C1 1D
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any input/output when the output is in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any input/output when the output is in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51.
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
recommended operating conditions (see Note 4)
MIN VCC Supply voltage Operating Data retention only VCC = 1.2 V VCC = 1.4 V to 1.6 V VIH High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 1.2 V VCC = 1.4 V to 1.6 V VIL Low-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 Active state 3-state VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 0 1.4 1.2 VCC 0.65 x VCC 0.65 x VCC 1.7 2 GND 0.35 x VCC 0.35 x VCC 0.7 0.8 3.6 VCC 3.6 -2 -4 -8 -12 2 4 8 12 mA mA V V V V MAX 3.6 UNIT V
VI VO
Input voltage Output voltage
IOHS
Static high-level output current high level
IOLS
Static low-level output current low level
Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V TA Operating free-air temperature -40 85 C Dynamic drive capability is equivalent to standard outputs with IOH and IOL of 24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC TM) Circuitry Technology and Applications, literature number SCEA009. NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
t/v
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOHS = -100 A IOHS = -2 mA, VOH IOHS = -4 mA, IOHS = -8 mA, IOHS = -12 mA, IOLS = 100 A VOL IOLS = 2 mA, IOLS = 4 mA, IOLS = 8 mA, IOLS = 12 mA, II Ioff IOZ ICC Ci Cio Control inputs A or B ports orts Control inputs VI = VCC or GND VI or VO = 3.6 V VO = VCC or GND VI = VCC or GND, VI = VCC or GND VO = VCC or GND IO = 0 TEST CONDITIONS VCC 1.4 V to 3.6 V 1.4 V 1.65 V 2.3 V 3V 1.4 V to 3.6 V VIL = 0.49 V VIL = 0.57 V VIL = 0.7 V VIL = 0.8 V 1.4 V 1.65 V 2.3 V 3V 3.6 V 0 3.6 V 3.6 V 2.5 V 3.3 V 2.5 V 3.3 V 3.5 3.5 8.5 8.5 MIN TYP MAX UNIT VCC-0.2 1.05 1.2 1.75 2.3 0.2 0.4 0.45 0.55 0.7 2.5 10 12.5 40 A A A A pF pF F V V
VIH = 0.91 V VIH = 1.07 V VIH = 1.7 V VIH = 2 V
Typical values are measured at TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5)
VCC = 1.2V TYP fclock Clock frequency tw Pulse duration, CLK high or low A data before CLK B data before CLK tsu Setup time SEL before CLK CLKENA1 or CLKENA2 before CLK OE before CLK A data after CLK B data after CLK th Hold time SEL after CLK CLKENA1 or CLKENA2 after CLK OE after CLK 4.7 6.2 4.5 0.9 5.4 1.9 0.4 1 2.6 0.4 3.9 4.3 3.4 0.9 5.3 2 1.3 1 2.2 0.4 VCC = 1.5 V 0.1 V MIN MAX VCC = 1.8 V 0.15 V MIN 5.8 2.6 3 2.2 1 2 1.2 0.5 0.4 1.4 0.4 MAX 75 5 2.1 2.1 1.6 1.1 1.6 1.1 0.6 0.3 1.1 0.5 VCC = 2.5 V 0.2 V MIN MAX 125 3.5 1.9 1.9 1.3 1.1 1.1 1 0.7 0.4 1 0.3 ns ns VCC = 3.3 V 0.3 V MIN MAX 175 MHz ns UNIT
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5)
PARAMETER fmax tpd d ten tdis di CLK B A B CLK CLK A B A 13.5 11.6 16 14.2 16 11.9 3 2.6 3.5 3.2 4.9 3 9.5 7.4 12 9.3 12.3 8.7 FROM (INPUT) TO (OUTPUT) VCC = 1.2 V TYP VCC = 1.5 V 0.1 V MIN MAX VCC = 1.8 V 0.15 V MIN 75 2.5 2.2 2.4 2 3.3 2.1 6.7 5.8 8.5 6.7 8.5 6.7 MAX VCC = 2.5 V 0.2 V MIN 125 1.6 1.5 2.1 2 1.9 1.8 4 3.5 4.8 4.4 4.8 3.6 MAX VCC = 3.3 V 0.3 V MIN 175 1.1 1 1.5 1.4 1.3 1.7 3 2.7 3.8 3.4 3.7 3.4 MAX MHz ns ns ns UNIT
switching characteristics, TA = 0C to 85C, CL = 0 pF
PARAMETER FROM (INPUT) TO (OUTPUT) B A VCC = 3.3 V 0.15 V MIN 1.4 1.2 MAX 2.4 2.1 ns UNIT
tpd d Texas Instruments SPICE simulation data
CLK
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 0 0, f = 10 MHz VCC = 1.8 V TYP 133 102 VCC = 2.5 V TYP 145 109 VCC = 3.3 V TYP 168 124 UNIT pF
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V 0.1 V
2 x VCC From Output Under Test CL = 15 pF (see Note A) 2 k S1 Open GND 2 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.1 V VOL tPHZ VOH VOH - 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k S1 Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
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SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SCES152G - DECEMBER 1998 - REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V
500 S1 2 x VCC Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
From Output Under Test CL = 30 pF (see Note A)
LOAD CIRCUIT
tw VCC
Timing Input tsu Data Input VCC/2
VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
VCC/2
VCC/2 0V
VOLTAGE WAVEFORMS PULSE DURATION
Output Control (low-level enabling) tPZL
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.3 V VOL tPHZ VCC/2 VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC Input VCC/2 VCC/2 0V tPLH tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B)
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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