View SCES156G_1000649.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN74AVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCES156G - DECEMBER 1998 - REVISED JUNE 2000
D D D D D
Member of the Texas Instruments Widebus TM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process DOCTM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of 24 mA at 2.5-V VCC Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
D D D D
Ioff Supports Partial-Power-Down Mode Operation ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.
3.2 2.8 VOL - Output Voltage - V 2.4 2.0 1.6 VCC = 2.5 V 1.2 VCC = 1.8 V 0.8 0.4 0 17 34 51 68 85 102 119 IOL - Output Current - mA 136 153 170 VCC = 3.3 V TA = 25C Process = Nominal - Output Voltage - V TA = 25C Process = Nominal
2.8 2.4 2.0 1.6 1.2 0.8
V
OH
VCC = 3.3 V 0.4
VCC = 2.5 V VCC = 1.8 V -32 -16 0
-160 -144 -128 -112 -96 -80 -64 -48 IOH - Output Current - mA
Figure 1. Output Voltage vs Output Current This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DOC, EPIC, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
SN74AVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCES156G - DECEMBER 1998 - REVISED JUNE 2000
description (continued)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16373 is characterized for operation from -40C to 85C.
terminal assignments
DGG OR DGV PACKAGE (TOP VIEW)
1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74AVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCES156G - DECEMBER 1998 - REVISED JUNE 2000
FUNCTION TABLE (each 8-bit latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
logic symbol
1OE 1LE 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 4D 2 1EN C3 2EN C4 3D 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE 1LE 1 48 C1 1D 2 1Q1 2OE 2LE 24 25 C1 2D1 36 1D 13
1D1
47
2Q1
To Seven Other Channels
To Seven Other Channels
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN74AVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCES156G - DECEMBER 1998 - REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74AVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCES156G - DECEMBER 1998 - REVISED JUNE 2000
recommended operating conditions (see Note 4)
MIN VCC Supply voltage Operating Data retention only VCC = 1.2 V VCC = 1.4 V to 1.6 V VIH High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 1.2 V VCC = 1.4 V to 1.6 V VIL Low-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 Active state 3-state VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 0 1.4 1.2 VCC 0.65 x VCC 0.65 x VCC 1.7 2 GND 0.35 x VCC 0.35 x VCC 0.7 0.8 3.6 VCC 3.6 -2 -4 -8 -12 2 4 8 12 mA mA V V V V MAX 3.6 UNIT V
VI VO
Input voltage Output voltage
IOHS
Static high-level output current high level
IOLS
Static low-level output current low level
Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V TA Operating free-air temperature -40 85 C Dynamic drive capability is equivalent to standard outputs with IOH and IOL of 24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009. NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
t/v
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN74AVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCES156G - DECEMBER 1998 - REVISED JUNE 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOHS = -100 A IOHS = -2 mA, VOH IOHS = -4 mA, IOHS = -8 mA, IOHS = -12 mA, IOLS = 100 A VOL IOLS = 2 mA, IOLS = 4 mA, IOLS = 8 mA, IOLS = 12 mA, II Ioff IOZ ICC Control inputs Ci Data inputs Co Out uts Outputs VI = VCC or GND VO = VCC or GND VI = VCC or GND VI or VO = 3.6 V VO = VCC or GND VI = VCC or GND, VI = VCC or GND IO = 0 VCC 1.4 V to 3.6 V 1.4 V 1.65 V 2.3 V 3V 1.4 V to 3.6 V VIL = 0.49 V VIL = 0.57 V VIL = 0.7 V VIL = 0.8 V 1.4 V 1.65 V 2.3 V 3V 3.6 V 0 3.6 V 3.6 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 3 3 2.5 2.5 6.5 6.5 pF F pF MIN TYP MAX UNIT VCC-0.2 1.05 1.2 1.75 2.3 0.2 0.4 0.45 0.55 0.7 2.5 10 10 40 A A A A V V
VIH = 0.91 V VIH = 1.07 V VIH = 1.7 V VIH = 2 V
Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25C.
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5)
VCC = 1.2 V MIN tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after LE 1.7 2 1.2 1.1 MAX VCC = 1.5 V 0.1 V MIN MAX VCC = 1.8 V 0.15 V MIN 2.2 1.1 1.1 MAX VCC = 2.5 V 0.2 V MIN 2 0.9 1.1 MAX VCC = 3.3 V 0.3 V MIN 1.8 0.8 1 MAX ns ns ns UNIT
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5)
PARAMETER FROM (INPUT) D LE OE OE TO (OUTPUT) VCC = 1.2 V TYP 5.8 7.2 7.4 8.4 VCC = 1.5 V 0.1 V MIN 1.2 1.4 1.6 2.5 MAX 6.8 8.3 8.8 9.4 VCC = 1.8 V 0.15 V MIN 1 1.1 1.6 2.3 MAX 5.7 6.6 6.7 7.8 VCC = 2.5 V 0.2 V MIN 0.8 0.8 1.4 1.3 MAX 3.3 4 4.3 4.2 VCC = 3.3 V 0.3 V MIN 0.7 0.7 0.7 1.2 MAX 2.8 3.2 3.4 3.9 ns ns ns UNIT
tpd d ten tdis
Q Q Q
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74AVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCES156G - DECEMBER 1998 - REVISED JUNE 2000
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 0 0, f = 10 MHz VCC = 1.8 V TYP 40 20 VCC = 2.5 V TYP 43 22 VCC = 3.3 V TYP 47 24 UNIT pF
PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V 0.1 V
2 x VCC From Output Under Test CL = 15 pF (see Note A) 2 k S1 Open GND 2 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.1 V VOL tPHZ VOH VOH - 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
SN74AVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCES156G - DECEMBER 1998 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k S1 Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74AVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCES156G - DECEMBER 1998 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
500 S1 2 x VCC Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
From Output Under Test CL = 30 pF (see Note A)
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 VCC/2 0V tPLH tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
9
SN74AVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCES156G - DECEMBER 1998 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT
tw VCC
Timing Input tsu Data Input VCC/2
VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
VCC/2
VCC/2 0V
VOLTAGE WAVEFORMS PULSE DURATION
Output Control (low-level enabling) tPZL
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 tPZH VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC Input VCC/2 VCC/2 0V tPLH tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B)
Output Waveform 2 S1 at GND (see Note B)
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SCES156G

	To Download SCES156G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .