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SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
D D D D
Member of the Texas Instruments Widebus TM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process DOCTM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of 24 mA at 2.5-V VCC
D D D D
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation Ideal for Use in PC133 Registered DIMM Applications Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.
3.2 2.8 VOL - Output Voltage - V 2.4 2.0 1.6 VCC = 2.5 V 1.2 VCC = 1.8 V 0.8 0.4 0 17 34 51 68 85 102 119 IOL - Output Current - mA 136 153 170 VCC = 3.3 V TA = 25C Process = Nominal - Output Voltage - V TA = 25C Process = Nominal
2.8 2.4 2.0 1.6 1.2 0.8
VCC = 3.3 V 0.4
VCC = 2.5 V VCC = 1.8 V -32 -16 0
-160 -144 -128 -112 -96 -80 -64 -48 IOH - Output Current - mA
Figure 1. Output Voltage vs Output Current This 20-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 2000, Texas Instruments Incorporated
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PRODUCT PREVIEW
V
OH
SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
description (continued)
The SN74AVC16836 is characterized for operation from -40C to 85C.
terminal assignments
DGG OR DGV PACKAGE (TOP VIEW)
OE Y1 Y2 GND Y3 Y4 VCC Y5 Y6 Y7 GND Y8 Y9 Y10 Y11 Y12 Y13 GND Y14 Y15 Y16 VCC Y17 Y18 GND Y19 Y20 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CLK A1 A2 GND A3 A4 VCC A5 A6 A7 GND A8 A9 A10 A11 A12 A13 GND A14 A15 A16 VCC A17 A18 GND A19 A20 LE
PRODUCT PREVIEW
NC - No internal connection FUNCTION TABLE (each universal bus driver) INPUTS OE H L L L L L LE X L L H H H CLK X X X L or H A X L H L H X OUTPUT Y Z L H L H
Y0 Output level before the indicated steady-state input conditions were established
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SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
logic symbol
OE CLK LE 1 56 29 EN1 2C3 C3 G2 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 1 1 1 3D 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
A1 A2 A3 A4 A5 A6 A7 A8
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1 OE 56 CLK LE 29
55 A1
1D C1 CLK 2 Y1
To 19 Other Channels
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PRODUCT PREVIEW
A9
SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51.
PRODUCT PREVIEW
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SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
MIN VCC Supply voltage Operating Data retention only VCC = 1.2 V VCC = 1.4 V to 1.6 V VIH High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 1.2 V VCC = 1.4 V to 1.6 V VIL Low-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 Active state 3-state VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 0 1.4 1.2 VCC 0.65 x VCC 0.65 x VCC 1.7 2 GND 0.35 x VCC 0.35 x VCC 0.7 0.8 3.6 VCC 3.6 -2 -4 -8 -12 2 4 8 12 mA mA V V V V MAX 3.6 UNIT V
VI VO
Input voltage Output voltage
IOHS
Static high-level output current high level
IOLS
Static low-level output current low level
Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V TA Operating free-air temperature -40 85 C Dynamic drive capability is equivalent to standard outputs with IOH and IOL of 24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC TM) Circuitry Technology and Applications, literature number SCEA009. NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
t/v
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PRODUCT PREVIEW
SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOHS = -100 A IOHS = -2 mA, VOH IOHS = -4 mA, IOHS = -8 mA, IOHS = -12 mA, IOLS = 100 A VOL IOLS = 2 mA, IOLS = 4 mA, IOLS = 8 mA, IOLS = 12 mA, II Ioff IOZ ICC Control inputs Ci Data inputs Co Out uts Outputs VO = VCC or GND VI = VCC or GND Control inputs VI = VCC or GND VI or VO = 3.6 V VO = VCC or GND VI = VCC or GND, IO = 0 VCC 1.4 V to 3.6 V 1.4 V 1.65 V 2.3 V 3V 1.4 V to 3.6 V VIL = 0.49 V VIL = 0.57 V VIL = 0.7 V VIL = 0.8 V 1.4 V 1.65 V 2.3 V 3V 3.6 V 0 3.6 V 3.6 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V pF F pF MIN TYP MAX UNIT VCC-0.2 1.05 1.2 1.75 2.3 0.2 0.4 0.45 0.55 0.7 2.5 10 10 40 A A A A V V
VIH = 0.91 V VIH = 1.07 V VIH = 1.7 V VIH = 2 V
PRODUCT PREVIEW
Typical values are measured at TA = 25C.
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5)
VCC = 1.2 V MIN fclock tw Clock frequency Pulse duration Setup St time LE low CLK high or low Data before CLK tsu Data before LE CLK high CLK low CLK high or low ns ns MAX VCC = 1.5 V 0.1 V MIN MAX VCC = 1.8 V 0.15 V MIN MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 3.3 V 0.3 V MIN MAX MHz ns UNIT
th
Hold time
Data after CLK Data after LE
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SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5)
PARAMETER fmax A tpd ten tdis LE CLK OE OE Y Y ns ns Y ns FROM (INPUT) TO (OUTPUT) VCC = 1.2 V TYP VCC = 1.5 V 0.1 V MIN MAX VCC = 1.8 V 0.15 V MIN MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 3.3 V 0.3 V MIN MAX MHz UNIT
switching characteristics, TA = 0C to 85C, CL = 0 pF
PARAMETER FROM (INPUT) A CLK TO (OUTPUT) VCC = 3.3 V 0.15 V MIN MAX UNIT
Texas Instruments SPICE simulation data
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 0 0, f = 10 MHz VCC = 1.8 V TYP VCC = 2.5 V TYP VCC = 3.3 V TYP UNIT pF
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PRODUCT PREVIEW
tpd d
Y
ns
SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V 0.1 V
2 x VCC From Output Under Test CL = 15 pF (see Note A) 2 k S1 Open GND 2 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu VCC VCC/2 0V th VCC VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
PRODUCT PREVIEW
Data Input
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.1 V VOL tPHZ VOH VOH - 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V
1 k S1 2 x VCC Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
From Output Under Test CL = 30 pF (see Note A)
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC/2
VCC/2 0V tPLZ VCC
VCC/2
VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V
VCC/2
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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VCC
SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu VCC VCC/2 0V th VCC VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
PRODUCT PREVIEW
Data Input
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
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SN74AVC16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES170F - DECEMBER 1998 - REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT
tw VCC
Timing Input tsu Data Input VCC/2
VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
VCC/2
VCC/2 0V
VOLTAGE WAVEFORMS PULSE DURATION
Output Control (low-level enabling) tPZL
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 tPZH VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B)
Output
VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
Output Waveform 2 S1 at GND (see Note B)
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
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PRODUCT PREVIEW
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