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SN74LVCZ16245A 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES278A - JUNE 1999 - REVISED JUNE 1999
D D D D D D D D
Member of the Texas Instruments Widebus TM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Ioff and Power-Up 3-State Support Hot Insertion Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
DGG OR DL PACKAGE (TOP VIEW)
description
This 16-bit (dual-octal) noninverting bus transceiver is designed for 2.3-V to 3.6-V VCC operation. The SN74LVCZ16245A is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. When VCC is between 0 and 1.25 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.25 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN74LVCZ16245A is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
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SN74LVCZ16245A 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES278A - JUNE 1999 - REVISED JUNE 1999
FUNCTION TABLE (each 8-bit section) INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation
logic symbol
48 1OE 1DIR 1 25 2OE 2DIR 24 G3 3 EN1 [BA] 3 EN2 [AB] G6 6 EN4 [BA] 6 EN5 [AB] 1A1 47 1 2 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 46 44 43 41 40 38 37 36 4 5 3 5 6 8 9 11 12 13 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2 1B1
2A2 2A3 2A4 2A5 2A6 2A7 2A8
35 33 32 30 29 27 26
14 16 17 19 20 22 23
2B2 2B3 2B4 2B5 2B6 2B7 2B8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74LVCZ16245A 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES278A - JUNE 1999 - REVISED JUNE 1999
logic diagram (positive logic)
1DIR 1 2DIR 48 24
1OE
25
2OE
1A1
47
2A1
36
2
1B1
13
2B1
To Seven Other Channels
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI: (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51.
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SN74LVCZ16245A 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES278A - JUNE 1999 - REVISED JUNE 1999
recommended operating conditions (see Note 4)
MIN VCC VIH VIL VI VO Supply voltage High level input voltage High-level Low-level Low level input voltage Input voltage Output voltage High or low state 3-state VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 2.3 V IOL t/v t/VCC TA Low-level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature 150 -40 85 VCC = 2.7 V VCC = 3 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 0 2.3 1.7 2 0.7 0.8 5.5 VCC 5.5 -8 -12 -24 8 12 24 5 ns/V s/V C mA mA MAX 3.6 UNIT V V V V V
IOH
High-level output current
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74LVCZ16245A 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES278A - JUNE 1999 - REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 A IOH = -8 mA VOH IOH = -12 mA 12 IOH = -24 mA IOL = 100 A VOL IOL = 8 mA IOL = 12 mA Control inputs IOL = 24 mA VI = 0 to 5.5 V VI or VO = 5.5 V VO = 0 to 5.5 V VO = 0.5 V to 2.5 V, VO = 0.5 V to 2.5 V, VI = VCC or GND 3.6 V VI 5.5 V One input at VCC - 0.6 V, Control inputs VI = VCC or GND VO = VCC or GND OE = don't care OE = don't care IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 2.3 V to 3.6 V 2.3 V 2.7 V 3V 3V 2.3 V to 3.6 V 2.3 V 2.7 V 3V 3.6 V 0 3.6 V 0 to 1.25 V 1.25 V to 0 3.6 36V 2.7 V to 3.6 V 3.3 V 3.3 V 5 7.5 MIN VCC-0.2 1.7 2.2 2.4 2.2 0.2 0.7 0.4 0.55 5 10 10 10 10 60 60 500 A A A A A A A pF pF V V TYP MAX UNIT
II Ioff IOZ IOZPU IOZPD ICC ICC Ci
Cio A or B ports All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. This applies in the disabled state only.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 2)
PARAMETER tpd ten tdis FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B VCC = 2.5 V 0.2 V MIN 1.3 1.8 1.8 MAX 5.7 7.7 8.1 VCC = 2.7 V MIN MAX 4.7 6.7 7.1 VCC = 3.3 V 0.3 V MIN 1 1.5 1.5 MAX 4 5.5 6.6 ns ns ns UNIT
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation capacitance per transceiver Outputs enabled Outputs disabled TEST CONDITIONS f = 10 MHz VCC = 2.5 V TYP 35 4 VCC = 3.3 V TYP 42 2 UNIT pF
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SN74LVCZ16245A 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES278A - JUNE 1999 - REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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POST OFFICE BOX 655303
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SN74LVCZ16245A 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES278A - JUNE 1999 - REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT
tw 2.7 V
Timing Input
2.7 V 1.5 V 0V tsu th 2.7 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
1.5 V
1.5 V 0V
VOLTAGE WAVEFORMS PULSE DURATION
Data Input
Output Control (low-level enabling) tPZL
2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
2.7 V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL
Output Waveform 1 S1 at 6 V (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B)
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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Copyright (c) 1999, Texas Instruments Incorporated

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