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SN54ALVTH32245, SN74ALVTH32245 2.5-V/3.3-V 32-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES333 - APRIL 2000
D D D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus TM Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C High Drive (-24/24 mA at 2.5-V and -32/64 mA at 3.3-V VCC) Ioff and Power-Up 3-State Support Hot Insertion
D D D D D
Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pins Minimize High-Speed Switching Noise Packaged in Plastic Fine-Pitch Ball Grid Array Package
NOTE: For tape and reel order entry: The GKER package is abbreviated to KR.
description
These devices can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the devices so that the buses are effectively isolated. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. When VCC is between 0 and 1.2 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH32245 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ALVTH32245 is characterized for operation from -40C to 85C.
FUNCTION TABLE (each 8-bit section) INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 2000, Texas Instruments Incorporated
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PRODUCT PREVIEW
The 'ALVTH32245 devices are 32-bit (dual-octal) noninverting 3-state transceivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
SN54ALVTH32245, SN74ALVTH32245 2.5-V/3.3-V 32-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES333 - APRIL 2000
GKE PACKAGE (TOP VIEW) 1 A B C D E F G H J K 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K L M N P R T 1B2 1B4 1B6 1B8 2B2 2B4 2B6 2B7 3B2 3B4 3B6 3B8 4B2 4B4 4B6 4B7 2 1B1 1B3 1B5 1B7 2B1 2B3 2B5 2B8 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B8 3 1DIR GND 1VCC GND GND 1VCC GND 2DIR 3DIR GND 2VCC GND GND 2VCC GND 4DIR 4 1OE GND 1VCC GND GND 1VCC GND 2OE 3OE GND 2VCC GND GND 2VCC GND 4OE 5 1A1 1A3 1A5 1A7 2A1 2A3 2A5 2A8 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A8 6 1A2 1A4 1A6 1A8 2A2 2A4 2A6 2A7 3A2 3A4 3A6 3A8 4A2 4A4 4A6 4A7
PRODUCT PREVIEW
L M N P R T
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SN54ALVTH32245, SN74ALVTH32245 2.5-V/3.3-V 32-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES333 - APRIL 2000
logic diagram (positive logic)
1DIR A3 2DIR A4 H3
1OE
H4
2OE
1A1
A5
2A1
E5
A2
1B1
E2
2B1
To Seven Other Channels NOTE A: 1VCC is associated with these channels.
To Seven Other Channels
3DIR
J3
4DIR J4
T3
3OE
T4
4OE
3A1
J5
4A1
N5
J2
3B1
N2
4B1
To Seven Other Channels NOTE B: 2VCC is associated with these channels.
To Seven Other Channels
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PRODUCT PREVIEW
SN54ALVTH32245, SN74ALVTH32245 2.5-V/3.3-V 32-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES333 - APRIL 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output current in the low state, IO: SN54ALVTH32245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH32245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH32245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -48 mA SN74ALVTH32245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -64 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
PRODUCT PREVIEW
recommended operating conditions, VCC = 2.5 V 0.2 V (see Note 3)
SN54ALVTH32245 MIN VCC VIH VIL VI IOH IOL t/v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1 kHz Input transition rise or fall rate Power-up ramp rate Operating free-air temperature Outputs enabled 200 -55 125 0 VCC 2.3 1.7 0.7 5.5 -6 6 18 10 200 -40 85 0 VCC TYP MAX 2.7 SN74ALVTH32245 MIN 2.3 1.7 0.7 5.5 -8 8 24 10 TYP MAX 2.7 UNIT V V V V mA mA ns/V s/V C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN54ALVTH32245, SN74ALVTH32245 2.5-V/3.3-V 32-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES333 - APRIL 2000
recommended operating conditions, VCC = 3.3 V 0.3 V (see Note 3)
SN54ALVTH32245 MIN VCC VIH VIL VI IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1 kHz Input transition rise or fall rate Outputs enabled 0 VCC 3 2 0.8 5.5 -24 24 48 10 0 VCC TYP MAX 3.6 SN74ALVTH32245 MIN 3 2 0.8 5.5 -32 32 64 10 TYP MAX 3.6 UNIT V V V V mA mA ns/V
t/VCC Power-up ramp rate 200 200 s/V TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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PRODUCT PREVIEW
SN54ALVTH32245, SN74ALVTH32245 2.5-V/3.3-V 32-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES333 - APRIL 2000
electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted)
PARAMETER VIK VOH TEST CONDITIONS VCC = 2.3 V, VCC = 2.3 V to 2.7 V, VCC = 2 3 V 2.3 VCC = 2.3 V to 2.7 V, VOL II = -18 mA IOH = -100 A IOH = -6 mA IOH = -8 mA IOL = 100 A IOL = 6 mA IOL = 8 mA IOL = 18 mA IOL = 24 mA VI = VCC or GND VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.7 V VI = 1.7 V VI = 0 to VCC VI = 0 to VCC VO = 5.5 V 300 -300 125 100 0.04 2.3 0.04 0.1 4.5 0.1 0.04 2.3 0.04 115 -10 300 -300 125 100 0.1 4.5 0.1 pF mA SN54ALVTH32245 MIN TYP MAX -1.2 VCC-0.2 1.8 0.2 0.4 0.4 0.5 0.5 1 10 10 1 -5 115 -10 1 10 10 1 -5 100 A A A A A A A A V VCC-0.2 V 1.8 0.2 SN74ALVTH32245 MIN TYP MAX -1.2 UNIT V
VCC = 2 3 V 2.3
Control inputs II A or B ports
VCC = 2.7 V, VCC = 0 or 2.7 V, VCC = 2.7 V VCC = 0, VCC = 2.3 V, VCC = 2.3 V, VCC = 2.7 V, VCC = 2.7 V, VCC = 2.3 V,
PRODUCT PREVIEW
Ioff IBHL IBHH IBHLO IBHHO# IEX|| IOZ(PU/PD)k
VCC 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don't care VCC = 2.7 V, IO = 0, VI = VCC or GND VCC = 2.5 V, VCC = 2.5 V, Outputs high Outputs low Outputs disabled VI = 2.5 V or 0 VO = 2.5 V or 0
ICC Ci Cio
pF All typical values are at VCC = 2.5 V, TA = 25C. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down
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SN54ALVTH32245, SN74ALVTH32245 2.5-V/3.3-V 32-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES333 - APRIL 2000
electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted)
PARAMETER VIK VOH TEST CONDITIONS VCC = 3 V, VCC = 3 V to 3.6 V, VCC = 3 V VCC = 3 V to 3.6 V, II = -18 mA IOH = -100 A IOH = -24 mA IOH = -32 mA IOL = 100 A IOL = 16 mA IOL = 24 mA IOL = 32 mA IOL = 48 mA IOL = 64 mA Control inputs II A or B ports Ioff IBHL IBHH IBHLO IBHHO# IEX|| IOZ(PU/PD)k VCC = 3.6 V VCC = 0, VCC = 3 V, VCC = 3 V, VCC = 3.6 V, VCC = 3.6 V, VCC = 3 V, VCC = 3.6 V, VCC = 0 or 3.6 V, VI = VCC or GND VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to VCC VI = 0 to VCC 75 -75 500 -500 125 100 0.07 3.2 0.07 0.1 5 0.1 0.2 0.07 3.2 0.07 SN54ALVTH32245 MIN TYP MAX -1.2 VCC-0.2 2 0.2 0.5 0.5 0.55 0.55 1 10 10 1 -5 75 -75 500 -500 125 100 0.1 5 0.1 0.2 mA pF mA 1 10 10 1 -5 100 A A A A A A A A VCC-0.2 V 2 0.2 0.4 V SN74ALVTH32245 MIN TYP MAX -1.2 UNIT V
VOL
VCC = 3 V
VO = 5.5 V VCC 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don't care VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high Outputs low Outputs disabled
ICC ICCh Ci
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VCC = 3.3 V, VCC = 3.3 V, VI = 3.3 V or 0 VO = 3.3 V or 0
Cio pF All typical values are at VCC = 3.3 V, TA = 25C. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down h This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
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PRODUCT PREVIEW
SN54ALVTH32245, SN74ALVTH32245 2.5-V/3.3-V 32-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES333 - APRIL 2000
switching characteristics over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B TO (OUTPUT) B or A A or B A or B SN54ALVTH32245 MIN MAX SN74ALVTH32245 MIN MAX UNIT ns ns ns
OE OE
switching characteristics over recommended operating free-air temperature range, CL = 50 pF, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B TO (OUTPUT) B or A A or B A or B SN54ALVTH32245 MIN MAX SN74ALVTH32245 MIN MAX UNIT ns ns ns
PRODUCT PREVIEW
OE OE
skew
tps (pin or transition skew), tps = |tPHL - tPHL|
VCC = 2.5 V tpsmax VCC = 3.3 V UNIT ps
tOST = |tpm - tpn|, where is any edge transition (high to low or low to high) measured between any two outputs (m or n) within any given device (see Note 4)
VCC = 2.5 V tOST NOTE 4: One output switching, TA = 25C A-B B-A VCC = 3.3 V UNIT ps
tOSHL/tOSLH (common edge skew), tOSHL = |tPHLmax - tPHLmin| (output skew for low-to-high transitions), and tOSLH = |tPLHmax - tPLHmin| (output skew for high-to-low transitions) (see Note 4)
VCC = 2.5 V tOSLH tOSHL tOSLH tOSHL NOTE 4: One output switching, TA = 25C A-B AB B-A BA VCC = 3.3 V UNIT ps ps
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SN54ALVTH32245, SN74ALVTH32245 2.5-V/3.3-V 32-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES333 - APRIL 2000
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC/2
VCC/2 0V tPLZ VCC
VCC/2
VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V
VCC/2
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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PRODUCT PREVIEW
VCC
SN54ALVTH32245, SN74ALVTH32245 2.5-V/3.3-V 32-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES333 - APRIL 2000
PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT tw 3V Timing Input tsu 3V 1.5 V 0V th 3V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Waveform 1 S1 at 6 V (see Note B) tPZH VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) 1.5 V 0V Output Control 1.5 V 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH Output tPHL tPLZ 3V 1.5 V VOL + 0.3 V tPHZ VOH VOH - 0.3 V 0V VOL 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION
PRODUCT PREVIEW
Data Input
1.5 V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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